[PATCH v6] Add AMD znver6 processor support

[Jan Beulich]

On 26.11.2025 12:41, Umesh Kalvakuntla wrote:
> --- a/opcodes/i386-opc.tbl
> +++ b/opcodes/i386-opc.tbl
> @@ -3145,6 +3145,17 @@ vcvtneps2bf16<Vxy>, 0xf372, AVX_NE_CONVERT, Modrm|<Vxy:vex>|Space0F38|VexW0|NoSu
>  
>  // AVX-NE-CONVERT instructions end.
>  
> +// AVX512_BMM instructions.
> +
> +vbmacor16x16x16, 0x80, AVX512_BMM&AVX512VL, Modrm|EVex256|VexW0|Src1VVVV|Map6|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegYMM|Unspecified|BaseIndex, RegYMM, RegYMM }
> +vbmacor16x16x16, 0x80, AVX512_BMM, Modrm|EVex512|VexW0|Src1VVVV|Map6|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegZMM|Unspecified|BaseIndex, RegZMM, RegZMM }
> +vbmacxor16x16x16, 0x80, AVX512_BMM&AVX512VL, Modrm|EVex256|VexW1|Src1VVVV|Map6|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegYMM|Unspecified|BaseIndex, RegYMM, RegYMM }
> +vbmacxor16x16x16, 0x80, AVX512_BMM, Modrm|EVex512|VexW1|Src1VVVV|Map6|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegZMM|Unspecified|BaseIndex, RegZMM, RegZMM }
> +vbitrevb, 0x81, AVX512_BMM&AVX512VL, Modrm|EVexDYN|VexW0|Masking|Map6|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM }
> +vbitrevb, 0x81, AVX512_BMM, Modrm|EVex512|VexW0|Masking|Map6|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegZMM|Unspecified|BaseIndex, RegZMM }

As already suggested by Haochen - please re-combine the respective templates.
AVX512VL aspects are dealt with elsewhere. If there are issues with that
logic, it wants fixing there. Please report if you have found any such issues.
(While you will find a number of instances of "&AVX512VL" in the table, you'll
notice that they're comparably rare. This really mainly should need using when
a template specifies only operand sizes below 512 bits.)

Jan