[PATCH 3/4] x86: sub-divide APX_F - NF

[Jan Beulich]

While spec version 007 introduced the three-way APX-NCI-NDD-NF, let's
split the three aspects (NCI, NDD, and NF) in gas. For NF we only need to
guard the {nf} pseudo-prefix.

--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -1242,6 +1242,7 @@ static const arch_entry cpu_arch[] =
   SUBARCH (apx_f, APX_F, ANY_APX_F, false),
   SUBARCH (apx_nci, APX_NCI, ANY_APX_NCI, false),
   SUBARCH (apx_ndd, APX_NDD, ANY_APX_NDD, false),
+  SUBARCH (apx_nf, APX_NF, ANY_APX_NF, false),
   VECARCH (avx10.2, AVX10_2, ANY_AVX10_2, set),
   SUBARCH (gmism2, GMISM2, GMISM2, false),
   SUBARCH (gmiccs, GMICCS, GMICCS, false),
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -222,6 +222,7 @@ accept various extension mnemonics.  For
 @code{apx_f},
 @code{apx_nci},
 @code{apx_ndd},
+@code{apx_nf},
 @code{avx10.2},
 @code{avx10.2/512},
 @code{avx10.2/256},
@@ -1734,7 +1735,7 @@ supported on the CPU specified.  The cho
 @item @samp{.padlock} @tab @samp{.clzero} @tab @samp{.mwaitx} @tab @samp{.rdpru}
 @item @samp{.mcommit} @tab @samp{.sev_es} @tab @samp{.snp} @tab @samp{.invlpgb}
 @item @samp{.tlbsync} @tab @samp{.rmpquery} @tab @samp{.rmpread} @tab @samp{.apx_f}
-@item @samp{.apx_nci} @tab @samp{.apx_ndd}
+@item @samp{.apx_nci} @tab @samp{.apx_ndd} @tab @samp{.apx_nf}
 @item @samp{.gmism2} @tab @samp{.gmiccs} @tab @samp{.padlockrng2} @tab @samp{.padlockphe2}
 @item @samp{.padlockxmodx}
 
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -303,6 +303,8 @@ static const dependency isa_dependencies
     "APX_F" },
   { "APX_NDD",
     "APX_F" },
+  { "APX_NF",
+    "APX_F" },
   { "PadLock",
     "FXSR" },
   { "PadLockRNG2",
@@ -486,6 +488,7 @@ static bitfield cpu_flags[] =
   BITFIELD (RMPREAD),
   BITFIELD (APX_NCI),
   BITFIELD (APX_NDD),
+  BITFIELD (APX_NF),
   BITFIELD (64),
   BITFIELD (No64),
 #ifdef CpuUnused
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -324,6 +324,8 @@ enum i386_cpu
   CpuAPX_NCI,
   /* Intel APX Non-Destructive Destination support required.  */
   CpuAPX_NDD,
+  /* Intel APX No-Flags-update support required.  */
+  CpuAPX_NF,
 
   /* NOTE: These items, which can be combined with other ISA flags above, need
      to remain second to last and in sync with CPU_FLAGS_COMMON. */
@@ -561,6 +563,7 @@ typedef union i386_cpu_flags
       unsigned int cpurmpread:1;
       unsigned int cpuapx_nci:1;
       unsigned int cpuapx_ndd:1;
+      unsigned int cpuapx_nf:1;
       CPU_FLAGS_COMMON;
 #ifdef CpuUnused
       unsigned int unused:(CpuNumOfBits - CpuUnused);
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -950,7 +950,7 @@ rex.wrxb, 0x4f, x64, NoSuf|IsPrefix, {}
 <pseudopfx:ident:cpu, disp8:Disp8:0, disp16:Disp16:No64, disp32:Disp32:i386, +
                       load:Load:0, store:Store:0, +
                       vex:VEX:0, vex2:VEX:0, vex3:VEX3:0, evex:EVEX:0, +
-                      rex:REX:x64, rex2:REX2:APX_F, nf:NF:APX_F, +
+                      rex:REX:x64, rex2:REX2:APX_F, nf:NF:APX_NF, +
                       nooptimize:NoOptimize:0, noimm8s:NoImm8s:0>
 
 {<pseudopfx>}, PSEUDO_PREFIX/Prefix_<pseudopfx:ident>, <pseudopfx:cpu>, NoSuf|IsPrefix, {}