[PATCH 0/3] RISC-V: Vendor relocation framework and XAndesPerf extension

[Ethan Y. C. Liang]

This series adds support for the Andes XAndesPerf extension [1] and
introduces two pieces of generic infrastructure that it depends on:

  1. A vendor relocation framework that implements the model defined in
     the RISC-V ELF specification [2] (relocation number 192–255
     preceded by R_RISCV_VENDOR and vendor identifier symbol).

  2. A refactoring of GAS branch relaxation, making the relaxation
     logic extensible so that any branch encoding, whether standard or
     vendor-defined, can participate in assembler-side relaxation.

The generic changes are submitted first and contain no
XAndesPerf-specific logic. XAndesPerf support is submitted afterward
and builds on these interfaces.
 
In particular, we would like to thank Alexey Lapshin for his earlier
patch on vendor relocations [3]. His work provided a helpful starting
point for this framework, and we are grateful for his contributions and
insights.

The series is ordered to maximize review clarity: generic
infrastructure first, extension support last. Feedback and suggestions
are very welcome.

[1] https://github.com/andestech/andes-v5-isa/releases/download/ast-v5_4_0-release/AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf
[2] https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc#nonstandard-relocations-aka-vendor-specific-relocations
[3] https://sourceware.org/pipermail/binutils/2025-April/140484.html

RISC-V: Add support for vendor-specific relocations
RISC-V: Refactor branch relaxation state encoding for extensibility
RISC-V: Add support for XAndesPerf extension

 bfd/bfd-in2.h                                 |  12 +
 bfd/elfnn-riscv.c                             | 797 +++++++++++++++++-
 bfd/elfxx-riscv.c                             | 404 ++++++++-
 bfd/elfxx-riscv.h                             |  23 +-
 bfd/libbfd.h                                  |  10 +
 bfd/reloc.c                                   |  23 +
 binutils/readelf.c                            |  22 +-
 gas/config/tc-riscv.c                         | 497 ++++++++++-
 gas/doc/c-riscv.texi                          |   5 +
 gas/testsuite/gas/riscv/march-help.l          |   1 +
 gas/testsuite/gas/riscv/x-andes-perf.d        | 107 +++
 gas/testsuite/gas/riscv/x-andes-perf.s        |  50 ++
 include/elf/riscv.h                           |  79 +-
 include/opcode/riscv-opc.h                    |  89 ++
 include/opcode/riscv.h                        |  78 ++
 ld/emultempl/riscvelf.em                      |   2 +-
 ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp    |   3 +
 .../ld-riscv-elf/x-andes-perf-relax.d         |  14 +
 .../ld-riscv-elf/x-andes-perf-relax.ld        |  11 +
 .../ld-riscv-elf/x-andes-perf-relax.s         |  23 +
 .../ld-riscv-elf/x-andes-perf-reloc.d         |  26 +
 .../ld-riscv-elf/x-andes-perf-reloc.s         |  20 +
 opcodes/riscv-dis.c                           |  89 ++
 opcodes/riscv-opc.c                           |  31 +
 24 files changed, 2338 insertions(+), 78 deletions(-)
 create mode 100644 gas/testsuite/gas/riscv/x-andes-perf.d
 create mode 100644 gas/testsuite/gas/riscv/x-andes-perf.s
 create mode 100644 ld/testsuite/ld-riscv-elf/x-andes-perf-relax.d
 create mode 100644 ld/testsuite/ld-riscv-elf/x-andes-perf-relax.ld
 create mode 100644 ld/testsuite/ld-riscv-elf/x-andes-perf-relax.s
 create mode 100644 ld/testsuite/ld-riscv-elf/x-andes-perf-reloc.d
 create mode 100644 ld/testsuite/ld-riscv-elf/x-andes-perf-reloc.s

-- 
2.49.0