[PATCH] AArch64: Add FEAT_SVE2p3 and FEAT_SME2p3 instructions.
Alice Carlotti
alice.carlotti@arm.com
Tue Nov 25 18:14:49 GMT 2025
On Tue, Oct 28, 2025 at 05:38:51PM +0000, Sivan Shani wrote:
A few general comments on tests:
- Some of the tests have an excessive number of cases and can be reduced - I've
commented on a couple of example inline.
- You're missing negative tests for your new operands (i.e. check that your new
operands don't accept input that they shouldn't, and see if the errors you
get out are sensible).
- The instructions that are available in both streaming and non-streaming mode
need to be tested separately with +sve2p3 and +sme2p3. You can do this by
specifying multiple #as lines in the .d file.
- There are too many individual files - please combine them into fewer files.
You could reduce it to just two files, sme2p3.s and sve2p3, with the sve2p3
file run twice under +sve2p3 and +sme2p3 (this would be slightly awkward for
the sve-only luti6 variant, but you can put that at the end of the file and
use a .arch directive to change the target for those few line sve2p3).
Other comments inline below.
> This patch includes:
>
> - Flags for the FEAT_SVE2p3 and FEAT_SME2p3 features.
> - Instructions:
> - ADDQP
> - ADDSUBP
> - FCVTZSN
> - FCVTZUN
> - LUTI6 16-bit
> - LUTI6 8-bit
> - SABAL
> - SCVTF
> - SCVTFLT
> - SDOT vectors
> - SDOT indexed
> - SQRSHRN
> - SQRSHRUN
> - SQSHRN
> - SQSHRUN
> - SUBP
> - UABAL
> - UCVTF
> - UCVTFLT
> - UDOT vectors
> - UDOT indexed
> - UQRSHRN
> - UQSHRN
> - LUTI6 vector
> - LUTI6 table, four registers
> - LUTI6 table, single, 8-bit
Typo: "Operands"
> - Opernads:
> - `OPND_SME_ZmxN_INDEX_22`: an operand represents a list of vector registers with an index.
> - `OPND_SME_Zn3_UNTYPED`: an operand represents an untyped list of vector registers.
> ---
> gas/config/tc-aarch64.c | 51 +-
> gas/doc/c-aarch64.texi | 4 +
> gas/testsuite/gas/aarch64/addqp.d | 24 +
> gas/testsuite/gas/aarch64/addqp.s | 16 +
> gas/testsuite/gas/aarch64/addsubp.d | 24 +
> gas/testsuite/gas/aarch64/addsubp.s | 16 +
> gas/testsuite/gas/aarch64/fcvtzsn.d | 17 +
> gas/testsuite/gas/aarch64/fcvtzsn.s | 9 +
> gas/testsuite/gas/aarch64/fcvtzun.d | 17 +
> gas/testsuite/gas/aarch64/fcvtzun.s | 9 +
> gas/testsuite/gas/aarch64/illegal-memtag.l | 2 +-
> gas/testsuite/gas/aarch64/luti6_16.d | 16 +
> gas/testsuite/gas/aarch64/luti6_16.s | 8 +
> gas/testsuite/gas/aarch64/luti6_8.d | 12 +
> gas/testsuite/gas/aarch64/luti6_8.s | 4 +
> gas/testsuite/gas/aarch64/luti6_table8.d | 17 +
> gas/testsuite/gas/aarch64/luti6_table8.s | 9 +
> gas/testsuite/gas/aarch64/luti6_vector16.d | 21 +
> gas/testsuite/gas/aarch64/luti6_vector16.s | 13 +
> gas/testsuite/gas/aarch64/luti6_vector16s4.d | 21 +
> gas/testsuite/gas/aarch64/luti6_vector16s4.s | 13 +
> gas/testsuite/gas/aarch64/sabal.d | 20 +
> gas/testsuite/gas/aarch64/sabal.s | 12 +
> gas/testsuite/gas/aarch64/scvtf.d | 17 +
> gas/testsuite/gas/aarch64/scvtf.s | 9 +
> gas/testsuite/gas/aarch64/scvtflt.d | 17 +
> gas/testsuite/gas/aarch64/scvtflt.s | 9 +
> gas/testsuite/gas/aarch64/sdot.d | 64 +++
> gas/testsuite/gas/aarch64/sdot.s | 56 +++
> gas/testsuite/gas/aarch64/sqrshrn.d | 32 ++
> gas/testsuite/gas/aarch64/sqrshrn.s | 24 +
> gas/testsuite/gas/aarch64/sqrshrn_imm.d | 80 +++
> gas/testsuite/gas/aarch64/sqrshrn_imm.s | 72 +++
> gas/testsuite/gas/aarch64/sqrshrun.d | 32 ++
> gas/testsuite/gas/aarch64/sqrshrun.s | 24 +
> gas/testsuite/gas/aarch64/sqshrun_imm.d | 80 +++
> gas/testsuite/gas/aarch64/sqshrun_imm.s | 72 +++
> gas/testsuite/gas/aarch64/subp.d | 24 +
> gas/testsuite/gas/aarch64/subp.s | 16 +
> gas/testsuite/gas/aarch64/sve-invalid.l | 8 +-
> .../gas/aarch64/sve2-sme2-6-invalid.l | 16 +-
> gas/testsuite/gas/aarch64/uabal.d | 20 +
> gas/testsuite/gas/aarch64/uabal.s | 12 +
> gas/testsuite/gas/aarch64/ucvtf.d | 17 +
> gas/testsuite/gas/aarch64/ucvtf.s | 9 +
> gas/testsuite/gas/aarch64/ucvtflt.d | 17 +
> gas/testsuite/gas/aarch64/ucvtflt.s | 9 +
> gas/testsuite/gas/aarch64/udot.d | 64 +++
> gas/testsuite/gas/aarch64/udot.s | 56 +++
> gas/testsuite/gas/aarch64/uqrshrn_imm.d | 81 ++++
> gas/testsuite/gas/aarch64/uqrshrn_imm.s | 73 +++
> gas/testsuite/gas/aarch64/uqshrn_imm.d | 81 ++++
> gas/testsuite/gas/aarch64/uqshrn_imm.s | 73 +++
> include/opcode/aarch64.h | 9 +
> opcodes/aarch64-asm-2.c | 5 +
> opcodes/aarch64-asm.c | 30 ++
> opcodes/aarch64-asm.h | 2 +
> opcodes/aarch64-dis-2.c | 455 ++++++++++++++----
> opcodes/aarch64-dis.c | 35 ++
> opcodes/aarch64-dis.h | 2 +
> opcodes/aarch64-opc-2.c | 3 +
> opcodes/aarch64-opc.c | 9 +
> opcodes/aarch64-opc.h | 1 +
> opcodes/aarch64-tbl-2.h | 28 ++
> opcodes/aarch64-tbl.h | 67 +++
> 65 files changed, 2048 insertions(+), 117 deletions(-)
> create mode 100644 gas/testsuite/gas/aarch64/addqp.d
> create mode 100644 gas/testsuite/gas/aarch64/addqp.s
> create mode 100644 gas/testsuite/gas/aarch64/addsubp.d
> create mode 100644 gas/testsuite/gas/aarch64/addsubp.s
> create mode 100644 gas/testsuite/gas/aarch64/fcvtzsn.d
> create mode 100644 gas/testsuite/gas/aarch64/fcvtzsn.s
> create mode 100644 gas/testsuite/gas/aarch64/fcvtzun.d
> create mode 100644 gas/testsuite/gas/aarch64/fcvtzun.s
> create mode 100644 gas/testsuite/gas/aarch64/luti6_16.d
> create mode 100644 gas/testsuite/gas/aarch64/luti6_16.s
> create mode 100644 gas/testsuite/gas/aarch64/luti6_8.d
> create mode 100644 gas/testsuite/gas/aarch64/luti6_8.s
> create mode 100644 gas/testsuite/gas/aarch64/luti6_table8.d
> create mode 100644 gas/testsuite/gas/aarch64/luti6_table8.s
> create mode 100644 gas/testsuite/gas/aarch64/luti6_vector16.d
> create mode 100644 gas/testsuite/gas/aarch64/luti6_vector16.s
> create mode 100644 gas/testsuite/gas/aarch64/luti6_vector16s4.d
> create mode 100644 gas/testsuite/gas/aarch64/luti6_vector16s4.s
> create mode 100644 gas/testsuite/gas/aarch64/sabal.d
> create mode 100644 gas/testsuite/gas/aarch64/sabal.s
> create mode 100644 gas/testsuite/gas/aarch64/scvtf.d
> create mode 100644 gas/testsuite/gas/aarch64/scvtf.s
> create mode 100644 gas/testsuite/gas/aarch64/scvtflt.d
> create mode 100644 gas/testsuite/gas/aarch64/scvtflt.s
> create mode 100644 gas/testsuite/gas/aarch64/sdot.d
> create mode 100644 gas/testsuite/gas/aarch64/sdot.s
> create mode 100644 gas/testsuite/gas/aarch64/sqrshrn.d
> create mode 100644 gas/testsuite/gas/aarch64/sqrshrn.s
> create mode 100644 gas/testsuite/gas/aarch64/sqrshrn_imm.d
> create mode 100644 gas/testsuite/gas/aarch64/sqrshrn_imm.s
> create mode 100644 gas/testsuite/gas/aarch64/sqrshrun.d
> create mode 100644 gas/testsuite/gas/aarch64/sqrshrun.s
> create mode 100644 gas/testsuite/gas/aarch64/sqshrun_imm.d
> create mode 100644 gas/testsuite/gas/aarch64/sqshrun_imm.s
> create mode 100644 gas/testsuite/gas/aarch64/subp.d
> create mode 100644 gas/testsuite/gas/aarch64/subp.s
> create mode 100644 gas/testsuite/gas/aarch64/uabal.d
> create mode 100644 gas/testsuite/gas/aarch64/uabal.s
> create mode 100644 gas/testsuite/gas/aarch64/ucvtf.d
> create mode 100644 gas/testsuite/gas/aarch64/ucvtf.s
> create mode 100644 gas/testsuite/gas/aarch64/ucvtflt.d
> create mode 100644 gas/testsuite/gas/aarch64/ucvtflt.s
> create mode 100644 gas/testsuite/gas/aarch64/udot.d
> create mode 100644 gas/testsuite/gas/aarch64/udot.s
> create mode 100644 gas/testsuite/gas/aarch64/uqrshrn_imm.d
> create mode 100644 gas/testsuite/gas/aarch64/uqrshrn_imm.s
> create mode 100644 gas/testsuite/gas/aarch64/uqshrn_imm.d
> create mode 100644 gas/testsuite/gas/aarch64/uqshrn_imm.s
>
> diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
> index 0ca54c3bd40..dcd5c2d45db 100644
> --- a/gas/config/tc-aarch64.c
> +++ b/gas/config/tc-aarch64.c
> @@ -1406,7 +1406,7 @@ reg_type_mask (aarch64_reg_type reg_type)
> static int
> parse_vector_reg_list (char **ccp, aarch64_reg_type type,
> struct vector_type_el *vectype,
> - bool has_qualifier)
> + bool has_qualifier, bool has_index)
> {
> char *str = *ccp;
> int nb_regs;
> @@ -1426,11 +1426,11 @@ parse_vector_reg_list (char **ccp, aarch64_reg_type type,
> str++;
>
> nb_regs = 0;
> - typeinfo_first.defined = 0;
> - typeinfo_first.type = NT_invtype;
> - typeinfo_first.width = -1;
> - typeinfo_first.element_size = 0;
> - typeinfo_first.index = 0;
> + typeinfo.defined = 0;
> + typeinfo.type = NT_invtype;
> + typeinfo.width = -1;
> + typeinfo.element_size = 0;
> + typeinfo.index = 0;
This part of the change looks wrong to me - can you explain what's going on
here?
> ret_val = 0;
> val = -1u;
> val_range = -1u;
> @@ -1451,6 +1451,8 @@ parse_vector_reg_list (char **ccp, aarch64_reg_type type,
> {
> reg = parse_reg (&str);
> typeinfo.defined = 0;
> + if (has_index)
> + typeinfo.defined = 2;
If retained, this constant should use the existing macro definition to make the
meaning clearer.
However, I think it would be better to leave this processing unchanged. We
could achieve the same effect by modifying the later check for expect_index
(e.g. by initialising expect_index as the new function parameter instead of a
zeroed local variable).
> }
> if (!reg)
> {
> @@ -7025,7 +7027,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
> case AARCH64_OPND_SME_Znx2_BIT_INDEX:
> // A vector register list encoding a bit index.
> reg_type = REG_TYPE_Z;
> - val = parse_vector_reg_list (&str, reg_type, &vectype, false);
> + val = parse_vector_reg_list (&str, reg_type, &vectype, false, false);
> if (val == PARSE_FAIL)
> goto failure;
>
> @@ -7045,8 +7047,10 @@ parse_operands (char *str, const aarch64_opcode *opcode)
> case AARCH64_OPND_SME_Zmx2_17_3:
> case AARCH64_OPND_SME_Zmx2:
> case AARCH64_OPND_SME_Zmx4:
> + case AARCH64_OPND_SME_ZmxN_INDEX_22:
> case AARCH64_OPND_SME_Znx2:
> case AARCH64_OPND_SME_Znx4:
> + case AARCH64_OPND_SME_Zn3_UNTYPED:
> case AARCH64_OPND_SME_Ztx2_STRIDED:
> case AARCH64_OPND_SME_Ztx4_STRIDED:
> reg_type = REG_TYPE_Z;
> @@ -7077,7 +7081,13 @@ parse_operands (char *str, const aarch64_opcode *opcode)
> }
> else
> {
> - val = parse_vector_reg_list (&str, reg_type, &vectype, true);
> + if (operands[i] == AARCH64_OPND_SME_ZmxN_INDEX_22)
> + val = parse_vector_reg_list (&str, reg_type, &vectype, false, true);
> + else if (operands[i] == AARCH64_OPND_SME_Zn3_UNTYPED)
> + val = parse_vector_reg_list (&str, reg_type, &vectype, false, false);
Can these cases be handled alongside the AARCH64_OPND_SME_Znx2_BIT_INDEX
instead? I think that would make the code much cleaner for now.
> + else
> + val = parse_vector_reg_list (&str, reg_type, &vectype, true, false);
> +
> if (val == PARSE_FAIL)
> goto failure;
>
> @@ -7087,14 +7097,14 @@ parse_operands (char *str, const aarch64_opcode *opcode)
> goto failure;
> }
>
> - if ((int) vectype.width > 0 && *str != ',')
> + if (operands[i] != AARCH64_OPND_SME_ZmxN_INDEX_22 && (int) vectype.width > 0 && *str != ',')
> {
> set_fatal_syntax_error
> (_("expected element type rather than vector type"));
> goto failure;
> }
> }
> - if (operands[i] == AARCH64_OPND_LEt)
> + if (operands[i] == AARCH64_OPND_LEt || operands[i] == AARCH64_OPND_SME_ZmxN_INDEX_22)
> {
> if (!(vectype.defined & NTA_HASINDEX))
> goto failure;
> @@ -7105,13 +7115,19 @@ parse_operands (char *str, const aarch64_opcode *opcode)
> {
> if (vectype.defined & NTA_HASINDEX)
> goto failure;
> + if (!(operands[i] == AARCH64_OPND_SME_Zn3_UNTYPED))
> if (!(vectype.defined & NTA_HASTYPE))
> - {
> - if (reg_type == REG_TYPE_Z || reg_type == REG_TYPE_P)
> - set_fatal_syntax_error (_("missing type suffix"));
> - goto failure;
> - }
> + {
> + if (reg_type == REG_TYPE_Z || reg_type == REG_TYPE_P)
> + set_fatal_syntax_error (_("missing type suffix"));
> + goto failure;
> + }
> }
> + if (operands[i] == AARCH64_OPND_SME_ZmxN_INDEX_22 || operands[i] == AARCH64_OPND_SME_Zn3_UNTYPED) {
> + info->qualifier = AARCH64_OPND_QLF_NIL;
> + break;
> + }
> +
> info->qualifier = vectype_to_qualifier (&vectype);
> if (info->qualifier == AARCH64_OPND_QLF_NIL)
> goto failure;
> @@ -7175,6 +7191,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
> case AARCH64_OPND_SVE_SHLIMM_PRED:
> case AARCH64_OPND_SVE_SHLIMM_UNPRED:
> case AARCH64_OPND_SVE_SHLIMM_UNPRED_22:
> + case AARCH64_OPND_SME_SHRIMM3:
> case AARCH64_OPND_SME_SHRIMM4:
> case AARCH64_OPND_SME_SHRIMM5:
> case AARCH64_OPND_SVE_SHRIMM_PRED:
> @@ -10905,6 +10922,8 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
> {"ssve-fexpa", AARCH64_FEATURE (SSVE_FEXPA), AARCH64_FEATURE (SME2)},
> {"sme-tmop", AARCH64_FEATURE (SME_TMOP), AARCH64_FEATURE (SME2)},
> {"sme-mop4", AARCH64_FEATURE (SME_MOP4), AARCH64_FEATURE (SME2)},
> + {"sve2p3", AARCH64_FEATURE (SVE2p3), AARCH64_FEATURE (SVE2p2)},
> + {"sme2p3", AARCH64_FEATURE (SME2p3), AARCH64_FEATURES (2, SME2p2, SME_LUTv2)},
> {NULL, AARCH64_NO_FEATURES, AARCH64_NO_FEATURES},
> };
>
> @@ -10938,6 +10957,8 @@ static const struct aarch64_virtual_dependency_table aarch64_dependencies[] = {
> {AARCH64_FEATURE (SME2p1), AARCH64_FEATURE (SVE2p1_SME2p1)},
> {AARCH64_FEATURE (SVE2p2), AARCH64_FEATURE (SVE2p2_SME2p2)},
> {AARCH64_FEATURE (SME2p2), AARCH64_FEATURES (2, SVE_SME2p2, SVE2p2_SME2p2)},
> + {AARCH64_FEATURE (SVE2p3), AARCH64_FEATURE (SVE2p3_SME2p3)},
> + {AARCH64_FEATURE (SME2p3), AARCH64_FEATURE (SVE2p3_SME2p3)},
> };
>
> static aarch64_feature_set
> diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
> index 9683d411ce9..bf9abbc478f 100644
> --- a/gas/doc/c-aarch64.texi
> +++ b/gas/doc/c-aarch64.texi
> @@ -319,6 +319,8 @@ automatically cause those extensions to be disabled.
> @tab Enable SME2.1.
> @item @code{sme2p2} @tab @code{sme2p1}
> @tab Enable SME2.2.
> +@item @code{sme2p3} @tab @code{sme2p2}
> + @tab Enable SME2.3.
> @item @code{ssbs} @tab
> @tab Enable Speculative Store Bypassing Safe state read and write.
> @item @code{ssve-aes} @tab @code{sme2}, @code{sve-aes}
> @@ -361,6 +363,8 @@ automatically cause those extensions to be disabled.
> @tab Enable SVE2.1.
> @item @code{sve2p2} @tab @code{sve2p1}
> @tab Enable SVE2.2.
> +@item @code{sve2p3} @tab @code{sve2p2}
> + @tab Enable SVE2.3.
> @item @code{the} @tab
> @tab Enable the Translation Hardening Extension.
> @item @code{tme} @tab
> diff --git a/gas/testsuite/gas/aarch64/addqp.d b/gas/testsuite/gas/aarch64/addqp.d
> new file mode 100644
> index 00000000000..a8e8818b2e0
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/addqp.d
> @@ -0,0 +1,24 @@
> +#as: -march=armv8-a+sve2p3
> +#objdump: -dr
> +
> +.*: file format .*
> +
> +Disassembly of section \.text:
> +
> +0+ <\.text>:
> + *[0-9a-f]+:[ \t]+04207800[ \t]+addqp[ \t]+z0\.b, z0\.b, z0\.b
> + *[0-9a-f]+:[ \t]+0420781f[ \t]+addqp[ \t]+z31\.b, z0\.b, z0\.b
> + *[0-9a-f]+:[ \t]+04207be0[ \t]+addqp[ \t]+z0\.b, z31\.b, z0\.b
> + *[0-9a-f]+:[ \t]+043f7800[ \t]+addqp[ \t]+z0\.b, z0\.b, z31\.b
> + *[0-9a-f]+:[ \t]+04607800[ \t]+addqp[ \t]+z0\.h, z0\.h, z0\.h
> + *[0-9a-f]+:[ \t]+0460781f[ \t]+addqp[ \t]+z31\.h, z0\.h, z0\.h
> + *[0-9a-f]+:[ \t]+04607be0[ \t]+addqp[ \t]+z0\.h, z31\.h, z0\.h
> + *[0-9a-f]+:[ \t]+047f7800[ \t]+addqp[ \t]+z0\.h, z0\.h, z31\.h
> + *[0-9a-f]+:[ \t]+04a07800[ \t]+addqp[ \t]+z0\.s, z0\.s, z0\.s
> + *[0-9a-f]+:[ \t]+04a0781f[ \t]+addqp[ \t]+z31\.s, z0\.s, z0\.s
> + *[0-9a-f]+:[ \t]+04a07be0[ \t]+addqp[ \t]+z0\.s, z31\.s, z0\.s
> + *[0-9a-f]+:[ \t]+04bf7800[ \t]+addqp[ \t]+z0\.s, z0\.s, z31\.s
> + *[0-9a-f]+:[ \t]+04e07800[ \t]+addqp[ \t]+z0\.d, z0\.d, z0\.d
> + *[0-9a-f]+:[ \t]+04e0781f[ \t]+addqp[ \t]+z31\.d, z0\.d, z0\.d
> + *[0-9a-f]+:[ \t]+04e07be0[ \t]+addqp[ \t]+z0\.d, z31\.d, z0\.d
> + *[0-9a-f]+:[ \t]+04ff7800[ \t]+addqp[ \t]+z0\.d, z0\.d, z31\.d
Existing test files specify the exact whitespace in the rest of the line after
the address, and use literal tabs (instead of \t). I don't see any reason to
do differently here.
> diff --git a/gas/testsuite/gas/aarch64/addqp.s b/gas/testsuite/gas/aarch64/addqp.s
> new file mode 100644
> index 00000000000..5a5feeb497b
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/addqp.s
> @@ -0,0 +1,16 @@
> +addqp z0.b, z0.b, z0.b
> +addqp z31.b, z0.b, z0.b
> +addqp z0.b, z31.b, z0.b
> +addqp z0.b, z0.b, z31.b
> +addqp z0.h, z0.h, z0.h
> +addqp z31.h, z0.h, z0.h
> +addqp z0.h, z31.h, z0.h
> +addqp z0.h, z0.h, z31.h
> +addqp z0.s, z0.s, z0.s
> +addqp z31.s, z0.s, z0.s
> +addqp z0.s, z31.s, z0.s
> +addqp z0.s, z0.s, z31.s
> +addqp z0.d, z0.d, z0.d
> +addqp z31.d, z0.d, z0.d
> +addqp z0.d, z31.d, z0.d
> +addqp z0.d, z0.d, z31.d
> diff --git a/gas/testsuite/gas/aarch64/addsubp.d b/gas/testsuite/gas/aarch64/addsubp.d
> new file mode 100644
> index 00000000000..7e0a3db5b1f
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/addsubp.d
> @@ -0,0 +1,24 @@
> +#as: -march=armv8-a+sve2p3
> +#objdump: -dr
> +
> +.*: file format .*
> +
> +Disassembly of section \.text:
> +
> +0+ <\.text>:
> + *[0-9a-f]+:[ \t]+04207c00[ \t]+addsubp[ \t]+z0\.b, z0\.b, z0\.b
> + *[0-9a-f]+:[ \t]+04207c1f[ \t]+addsubp[ \t]+z31\.b, z0\.b, z0\.b
> + *[0-9a-f]+:[ \t]+04207fe0[ \t]+addsubp[ \t]+z0\.b, z31\.b, z0\.b
> + *[0-9a-f]+:[ \t]+043f7c00[ \t]+addsubp[ \t]+z0\.b, z0\.b, z31\.b
> + *[0-9a-f]+:[ \t]+04607c00[ \t]+addsubp[ \t]+z0\.h, z0\.h, z0\.h
> + *[0-9a-f]+:[ \t]+04607c1f[ \t]+addsubp[ \t]+z31\.h, z0\.h, z0\.h
> + *[0-9a-f]+:[ \t]+04607fe0[ \t]+addsubp[ \t]+z0\.h, z31\.h, z0\.h
> + *[0-9a-f]+:[ \t]+047f7c00[ \t]+addsubp[ \t]+z0\.h, z0\.h, z31\.h
> + *[0-9a-f]+:[ \t]+04a07c00[ \t]+addsubp[ \t]+z0\.s, z0\.s, z0\.s
> + *[0-9a-f]+:[ \t]+04a07c1f[ \t]+addsubp[ \t]+z31\.s, z0\.s, z0\.s
> + *[0-9a-f]+:[ \t]+04a07fe0[ \t]+addsubp[ \t]+z0\.s, z31\.s, z0\.s
> + *[0-9a-f]+:[ \t]+04bf7c00[ \t]+addsubp[ \t]+z0\.s, z0\.s, z31\.s
> + *[0-9a-f]+:[ \t]+04e07c00[ \t]+addsubp[ \t]+z0\.d, z0\.d, z0\.d
> + *[0-9a-f]+:[ \t]+04e07c1f[ \t]+addsubp[ \t]+z31\.d, z0\.d, z0\.d
> + *[0-9a-f]+:[ \t]+04e07fe0[ \t]+addsubp[ \t]+z0\.d, z31\.d, z0\.d
> + *[0-9a-f]+:[ \t]+04ff7c00[ \t]+addsubp[ \t]+z0\.d, z0\.d, z31\.d
> diff --git a/gas/testsuite/gas/aarch64/addsubp.s b/gas/testsuite/gas/aarch64/addsubp.s
> new file mode 100644
> index 00000000000..920c7004f00
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/addsubp.s
> @@ -0,0 +1,16 @@
> +addsubp z0.b, z0.b, z0.b
> +addsubp z31.b, z0.b, z0.b
> +addsubp z0.b, z31.b, z0.b
> +addsubp z0.b, z0.b, z31.b
> +addsubp z0.h, z0.h, z0.h
> +addsubp z31.h, z0.h, z0.h
> +addsubp z0.h, z31.h, z0.h
> +addsubp z0.h, z0.h, z31.h
> +addsubp z0.s, z0.s, z0.s
> +addsubp z31.s, z0.s, z0.s
> +addsubp z0.s, z31.s, z0.s
> +addsubp z0.s, z0.s, z31.s
> +addsubp z0.d, z0.d, z0.d
> +addsubp z31.d, z0.d, z0.d
> +addsubp z0.d, z31.d, z0.d
> +addsubp z0.d, z0.d, z31.d
> diff --git a/gas/testsuite/gas/aarch64/fcvtzsn.d b/gas/testsuite/gas/aarch64/fcvtzsn.d
> new file mode 100644
> index 00000000000..0742bc1bad7
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/fcvtzsn.d
> @@ -0,0 +1,17 @@
> +#as: -march=armv8-a+sve2p3
> +#objdump: -dr
> +
> +.*: file format .*
> +
> +Disassembly of section \.text:
> +
> +0+ <\.text>:
> + *[0-9a-f]+:[ \t]+654d3000[ \t]+fcvtzsn[ \t]+z0\.b,[ \t]+{z0\.h-z1\.h}
> + *[0-9a-f]+:[ \t]+654d301f[ \t]+fcvtzsn[ \t]+z31\.b,[ \t]+{z0\.h-z1\.h}
> + *[0-9a-f]+:[ \t]+654d33c0[ \t]+fcvtzsn[ \t]+z0\.b,[ \t]+{z30\.h-z31\.h}
> + *[0-9a-f]+:[ \t]+658d3000[ \t]+fcvtzsn[ \t]+z0\.h,[ \t]+{z0\.s-z1\.s}
> + *[0-9a-f]+:[ \t]+658d301f[ \t]+fcvtzsn[ \t]+z31\.h,[ \t]+{z0\.s-z1\.s}
> + *[0-9a-f]+:[ \t]+658d33c0[ \t]+fcvtzsn[ \t]+z0\.h,[ \t]+{z30\.s-z31\.s}
> + *[0-9a-f]+:[ \t]+65cd3000[ \t]+fcvtzsn[ \t]+z0\.s,[ \t]+{z0\.d-z1\.d}
> + *[0-9a-f]+:[ \t]+65cd301f[ \t]+fcvtzsn[ \t]+z31\.s,[ \t]+{z0\.d-z1\.d}
> + *[0-9a-f]+:[ \t]+65cd33c0[ \t]+fcvtzsn[ \t]+z0\.s,[ \t]+{z30\.d-z31\.d}
> diff --git a/gas/testsuite/gas/aarch64/fcvtzsn.s b/gas/testsuite/gas/aarch64/fcvtzsn.s
> new file mode 100644
> index 00000000000..d3c2bf05b9c
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/fcvtzsn.s
> @@ -0,0 +1,9 @@
> +fcvtzsn z0.b, { z0.h-z1.h }
> +fcvtzsn z31.b, { z0.h-z1.h }
> +fcvtzsn z0.b, { z30.h-z31.h }
> +fcvtzsn z0.h, { z0.s-z1.s }
> +fcvtzsn z31.h, { z0.s-z1.s }
> +fcvtzsn z0.h, { z30.s-z31.s }
> +fcvtzsn z0.s, { z0.d-z1.d }
> +fcvtzsn z31.s, { z0.d-z1.d }
> +fcvtzsn z0.s, { z30.d-z31.d }
> diff --git a/gas/testsuite/gas/aarch64/fcvtzun.d b/gas/testsuite/gas/aarch64/fcvtzun.d
> new file mode 100644
> index 00000000000..576d4dd1c37
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/fcvtzun.d
> @@ -0,0 +1,17 @@
> +#as: -march=armv8-a+sve2p3
> +#objdump: -dr
> +
> +.*: file format .*
> +
> +Disassembly of section \.text:
> +
> +0+ <\.text>:
> + *[0-9a-f]+:[ \t]+654d3400[ \t]+fcvtzun[ \t]+z0\.b,[ \t]+{z0\.h-z1\.h}
> + *[0-9a-f]+:[ \t]+654d341f[ \t]+fcvtzun[ \t]+z31\.b,[ \t]+{z0\.h-z1\.h}
> + *[0-9a-f]+:[ \t]+654d37c0[ \t]+fcvtzun[ \t]+z0\.b,[ \t]+{z30\.h-z31\.h}
> + *[0-9a-f]+:[ \t]+658d3400[ \t]+fcvtzun[ \t]+z0\.h,[ \t]+{z0\.s-z1\.s}
> + *[0-9a-f]+:[ \t]+658d341f[ \t]+fcvtzun[ \t]+z31\.h,[ \t]+{z0\.s-z1\.s}
> + *[0-9a-f]+:[ \t]+658d37c0[ \t]+fcvtzun[ \t]+z0\.h,[ \t]+{z30\.s-z31\.s}
> + *[0-9a-f]+:[ \t]+65cd3400[ \t]+fcvtzun[ \t]+z0\.s,[ \t]+{z0\.d-z1\.d}
> + *[0-9a-f]+:[ \t]+65cd341f[ \t]+fcvtzun[ \t]+z31\.s,[ \t]+{z0\.d-z1\.d}
> + *[0-9a-f]+:[ \t]+65cd37c0[ \t]+fcvtzun[ \t]+z0\.s,[ \t]+{z30\.d-z31\.d}
> diff --git a/gas/testsuite/gas/aarch64/fcvtzun.s b/gas/testsuite/gas/aarch64/fcvtzun.s
> new file mode 100644
> index 00000000000..8bfa672587a
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/fcvtzun.s
> @@ -0,0 +1,9 @@
> +fcvtzun z0.b, { z0.h-z1.h }
> +fcvtzun z31.b, { z0.h-z1.h }
> +fcvtzun z0.b, { z30.h-z31.h }
> +fcvtzun z0.h, { z0.s-z1.s }
> +fcvtzun z31.h, { z0.s-z1.s }
> +fcvtzun z0.h, { z30.s-z31.s }
> +fcvtzun z0.s, { z0.d-z1.d }
> +fcvtzun z31.s, { z0.d-z1.d }
> +fcvtzun z0.s, { z30.d-z31.d }
> diff --git a/gas/testsuite/gas/aarch64/illegal-memtag.l b/gas/testsuite/gas/aarch64/illegal-memtag.l
> index 476c345d366..9e9d6bf0dae 100644
> --- a/gas/testsuite/gas/aarch64/illegal-memtag.l
> +++ b/gas/testsuite/gas/aarch64/illegal-memtag.l
> @@ -26,7 +26,7 @@
> [^:]*:[0-9]+: Error: expected an integer or stack pointer register at operand 2 -- `gmi x1,xzr,x3'
> [^:]*:[0-9]+: Error: expected an integer or stack pointer register at operand 1 -- `addg xzr,x2,#0,#0'
> [^:]*:[0-9]+: Error: expected an integer or stack pointer register at operand 2 -- `subg x1,xzr,#0,#0'
> -[^:]*:[0-9]+: Error: expected an integer or zero register at operand 1 -- `subp sp,x1,x2'
> +[^:]*:[0-9]+: Error: expected an integer register or SVE vector register at operand 1 -- `subp sp,x1,x2'
> [^:]*:[0-9]+: Error: expected an integer or stack pointer register at operand 2 -- `subp x1,xzr,x2'
> [^:]*:[0-9]+: Error: expected an integer or stack pointer register at operand 3 -- `subp x1,x2,xzr'
> [^:]*:[0-9]+: Error: expected an integer or zero register at operand 1 -- `subps sp,x1,x2'
> diff --git a/gas/testsuite/gas/aarch64/luti6_16.d b/gas/testsuite/gas/aarch64/luti6_16.d
> new file mode 100644
> index 00000000000..27893664f39
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/luti6_16.d
> @@ -0,0 +1,16 @@
> +#as: -march=armv8-a+sve2p3
> +#objdump: -dr
> +
> +.*: file format .*
> +
> +Disassembly of section \.text:
> +
> +0+ <\.text>:
> + *[0-9a-f]+:[ \t]+4560ac00[ \t]+luti6[ \t]+z0.h,[ \t]+{z0.h-z1.h}, z0\[0\]
> + *[0-9a-f]+:[ \t]+4560ac1f[ \t]+luti6[ \t]+z31.h,[ \t]+{z0.h-z1.h}, z0\[0\]
> + *[0-9a-f]+:[ \t]+4560afe0[ \t]+luti6[ \t]+z0.h,[ \t]+{z31.h-z0.h}, z0\[0\]
> + *[0-9a-f]+:[ \t]+457fac00[ \t]+luti6[ \t]+z0.h,[ \t]+{z0.h-z1.h}, z31\[0\]
> + *[0-9a-f]+:[ \t]+45e0ac00[ \t]+luti6[ \t]+z0.h,[ \t]+{z0.h-z1.h}, z0\[1\]
> + *[0-9a-f]+:[ \t]+45e0ac1f[ \t]+luti6[ \t]+z31.h,[ \t]+{z0.h-z1.h}, z0\[1\]
> + *[0-9a-f]+:[ \t]+45e0afe0[ \t]+luti6[ \t]+z0.h,[ \t]+{z31.h-z0.h}, z0\[1\]
> + *[0-9a-f]+:[ \t]+45ffac00[ \t]+luti6[ \t]+z0.h,[ \t]+{z0.h-z1.h}, z31\[1\]
> diff --git a/gas/testsuite/gas/aarch64/luti6_16.s b/gas/testsuite/gas/aarch64/luti6_16.s
> new file mode 100644
> index 00000000000..e73326ba517
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/luti6_16.s
> @@ -0,0 +1,8 @@
> +luti6 z0.h, { z0.h, z1.h }, z0[0]
> +luti6 z31.h, { z0.h, z1.h }, z0[0]
> +luti6 z0.h, { z31.h, z0.h }, z0[0]
> +luti6 z0.h, { z0.h, z1.h }, z31[0]
> +luti6 z0.h, { z0.h, z1.h }, z0[1]
> +luti6 z31.h, { z0.h, z1.h }, z0[1]
> +luti6 z0.h, { z31.h, z0.h }, z0[1]
> +luti6 z0.h, { z0.h, z1.h }, z31[1]
> diff --git a/gas/testsuite/gas/aarch64/luti6_8.d b/gas/testsuite/gas/aarch64/luti6_8.d
> new file mode 100644
> index 00000000000..3e9a853a53d
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/luti6_8.d
> @@ -0,0 +1,12 @@
> +#as: -march=armv8-a+sve2p3
> +#objdump: -dr
> +
> +.*: file format .*
> +
> +Disassembly of section \.text:
> +
> +0+ <\.text>:
> + *[0-9a-f]+:[ \t]+4520ac00[ \t]+luti6[ \t]+z0.b,[ \t]+{z0.b-z1.b},[ \t]+z0
> + *[0-9a-f]+:[ \t]+4520ac1f[ \t]+luti6[ \t]+z31.b,[ \t]+{z0.b-z1.b},[ \t]+z0
> + *[0-9a-f]+:[ \t]+4520afe0[ \t]+luti6[ \t]+z0.b,[ \t]+{z31.b-z0.b},[ \t]+z0
> + *[0-9a-f]+:[ \t]+453fac00[ \t]+luti6[ \t]+z0.b,[ \t]+{z0.b-z1.b},[ \t]+z31
> diff --git a/gas/testsuite/gas/aarch64/luti6_8.s b/gas/testsuite/gas/aarch64/luti6_8.s
> new file mode 100644
> index 00000000000..afe837f9879
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/luti6_8.s
> @@ -0,0 +1,4 @@
> +luti6 z0.b, { z0.b, z1.b }, z0
> +luti6 z31.b, { z0.b, z1.b }, z0
> +luti6 z0.b, { z31.b, z0.b }, z0
> +luti6 z0.b, { z0.b, z1.b }, z31
> diff --git a/gas/testsuite/gas/aarch64/luti6_table8.d b/gas/testsuite/gas/aarch64/luti6_table8.d
> new file mode 100644
> index 00000000000..f34a59d2b73
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/luti6_table8.d
> @@ -0,0 +1,17 @@
> +#as: -march=armv8-a+sme2p3
> +#objdump: -dr
> +
> +.*: file format .*
> +
> +Disassembly of section \.text:
> +
> +0+ <\.text>:
> + *[0-9a-f]+:[ \t]+c08a0000[ \t]+luti6[ \t]+{z0.b-z3.b},[ \t]+zt0,[ \t]+{z0-z2}
> + *[0-9a-f]+:[ \t]+c08a001c[ \t]+luti6[ \t]+{z28.b-z31.b},[ \t]+zt0,[ \t]+{z0-z2}
> + *[0-9a-f]+:[ \t]+c08a0380[ \t]+luti6[ \t]+{z0.b-z3.b},[ \t]+zt0,[ \t]+{z7-z9}
> + *[0-9a-f]+:[ \t]+c09a0000[ \t]+luti6[ \t]+{z0.b, z4.b, z8.b, z12.b},[ \t]+zt0,[ \t]+{z0-z2}
> + *[0-9a-f]+:[ \t]+c09a0013[ \t]+luti6[ \t]+{z19.b, z23.b, z27.b, z31.b},[ \t]+zt0,[ \t]+{z0-z2}
> + *[0-9a-f]+:[ \t]+c09a0380[ \t]+luti6[ \t]+{z0.b, z4.b, z8.b, z12.b},[ \t]+zt0,[ \t]+{z7-z9}
> + *[0-9a-f]+:[ \t]+c0c84000[ \t]+luti6[ \t]+z0.b,[ \t]+zt0,[ \t]+z0
> + *[0-9a-f]+:[ \t]+c0c8401f[ \t]+luti6[ \t]+z31.b,[ \t]+zt0,[ \t]+z0
> + *[0-9a-f]+:[ \t]+c0c843e0[ \t]+luti6[ \t]+z0.b,[ \t]+zt0,[ \t]+z31
> diff --git a/gas/testsuite/gas/aarch64/luti6_table8.s b/gas/testsuite/gas/aarch64/luti6_table8.s
> new file mode 100644
> index 00000000000..e4cd81f5835
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/luti6_table8.s
> @@ -0,0 +1,9 @@
> +luti6 { z0.b-z3.b }, zt0, { z0-z2 }
> +luti6 { z28.b-z31.b }, zt0, { z0-z2 }
> +luti6 { z0.b-z3.b }, zt0, { z7-z9 }
> +luti6 { z0.b, z4.b, z8.b, z12.b }, zt0, { z0-z2 }
> +luti6 { z19.b, z23.b, z27.b, z31.b }, zt0, { z0-z2 }
> +luti6 { z0.b, z4.b, z8.b, z12.b }, zt0, { z7-z9 }
> +luti6 z0.b, zt0, z0
> +luti6 z31.b, zt0, z0
> +luti6 z0.b, zt0, z31
> diff --git a/gas/testsuite/gas/aarch64/luti6_vector16.d b/gas/testsuite/gas/aarch64/luti6_vector16.d
> new file mode 100644
> index 00000000000..b2e32c76236
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/luti6_vector16.d
> @@ -0,0 +1,21 @@
> +#as: -march=armv8-a+sme2p3
> +#objdump: -dr
> +
> +.*: file format .*
> +
> +Disassembly of section \.text:
> +
> +0+ <\.text>:
> + *[0-9a-f]+:[ \t]+c120f400[ \t]+luti6[ \t]+{z0.h-z3.h},[ \t]+{z0.h-z1.h},[ \t]+{z0-z1}\[0\]
> + *[0-9a-f]+:[ \t]+c120f41c[ \t]+luti6[ \t]+{z28.h-z31.h},[ \t]+{z0.h-z1.h},[ \t]+{z0-z1}\[0\]
> + *[0-9a-f]+:[ \t]+c120f7c0[ \t]+luti6[ \t]+{z0.h-z3.h},[ \t]+{z30.h-z31.h},[ \t]+{z0-z1}\[0\]
> + *[0-9a-f]+:[ \t]+c120f7e0[ \t]+luti6[ \t]+{z0.h-z3.h},[ \t]+{z31.h-z0.h},[ \t]+{z0-z1}\[0\]
> + *[0-9a-f]+:[ \t]+c13ef400[ \t]+luti6[ \t]+{z0.h-z3.h},[ \t]+{z0.h-z1.h},[ \t]+{z30-z31}\[0\]
> + *[0-9a-f]+:[ \t]+c13ff400[ \t]+luti6[ \t]+{z0.h-z3.h},[ \t]+{z0.h-z1.h},[ \t]+{z31-z0}\[0\]
> +
> + *[0-9a-f]+:[ \t]+c160f400[ \t]+luti6[ \t]+{z0.h-z3.h},[ \t]+{z0.h-z1.h},[ \t]+{z0-z1}\[1\]
> + *[0-9a-f]+:[ \t]+c160f41c[ \t]+luti6[ \t]+{z28.h-z31.h},[ \t]+{z0.h-z1.h},[ \t]+{z0-z1}\[1\]
> + *[0-9a-f]+:[ \t]+c160f7c0[ \t]+luti6[ \t]+{z0.h-z3.h},[ \t]+{z30.h-z31.h},[ \t]+{z0-z1}\[1\]
> + *[0-9a-f]+:[ \t]+c160f7e0[ \t]+luti6[ \t]+{z0.h-z3.h},[ \t]+{z31.h-z0.h},[ \t]+{z0-z1}\[1\]
> + *[0-9a-f]+:[ \t]+c17ef400[ \t]+luti6[ \t]+{z0.h-z3.h},[ \t]+{z0.h-z1.h},[ \t]+{z30-z31}\[1\]
> + *[0-9a-f]+:[ \t]+c17ff400[ \t]+luti6[ \t]+{z0.h-z3.h},[ \t]+{z0.h-z1.h},[ \t]+{z31-z0}\[1\]
> diff --git a/gas/testsuite/gas/aarch64/luti6_vector16.s b/gas/testsuite/gas/aarch64/luti6_vector16.s
> new file mode 100644
> index 00000000000..02f5771b64a
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/luti6_vector16.s
> @@ -0,0 +1,13 @@
> +luti6 { z0.h-z3.h }, { z0.h-z1.h }, { z0-z1 }[0]
> +luti6 { z28.h-z31.h }, { z0.h-z1.h }, { z0-z1 }[0]
> +luti6 { z0.h-z3.h }, { z30.h-z31.h }, { z0-z1 }[0]
> +luti6 { z0.h-z3.h }, { z31.h-z0.h }, { z0-z1 }[0]
> +luti6 { z0.h-z3.h }, { z0.h-z1.h }, { z30-z31 }[0]
> +luti6 { z0.h-z3.h }, { z0.h-z1.h }, { z31-z0 }[0]
> +
> +luti6 { z0.h-z3.h }, { z0.h-z1.h }, { z0-z1 }[1]
> +luti6 { z28.h-z31.h }, { z0.h-z1.h }, { z0-z1 }[1]
> +luti6 { z0.h-z3.h }, { z30.h-z31.h }, { z0-z1 }[1]
> +luti6 { z0.h-z3.h }, { z31.h-z0.h }, { z0-z1 }[1]
> +luti6 { z0.h-z3.h }, { z0.h-z1.h }, { z30-z31 }[1]
> +luti6 { z0.h-z3.h }, { z0.h-z1.h }, { z31-z0 }[1]
> diff --git a/gas/testsuite/gas/aarch64/luti6_vector16s4.d b/gas/testsuite/gas/aarch64/luti6_vector16s4.d
> new file mode 100644
> index 00000000000..8ca9c5e821b
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/luti6_vector16s4.d
> @@ -0,0 +1,21 @@
> +#as: -march=armv8-a+sme2p3
> +#objdump: -dr
> +
> +.*: file format .*
> +
> +Disassembly of section \.text:
> +
> +0+ <\.text>:
> + *[0-9a-f]+:[ \t]+c120fc00[ \t]+luti6[ \t]+{z0.h, z4.h, z8.h, z12.h},[ \t]+{z0.h-z1.h},[ \t]+{z0-z1}\[0\]
> + *[0-9a-f]+:[ \t]+c120fc13[ \t]+luti6[ \t]+{z19\.h, z23\.h, z27\.h, z31\.h},[ \t]+{z0\.h-z1\.h},[ \t]+{z0-z1}\[0\]
> + *[0-9a-f]+:[ \t]+c120ffc0[ \t]+luti6[ \t]+{z0\.h, z4\.h, z8\.h, z12\.h},[ \t]+{z30\.h-z31\.h},[ \t]+{z0-z1}\[0\]
> + *[0-9a-f]+:[ \t]+c120ffe0[ \t]+luti6[ \t]+{z0\.h, z4\.h, z8\.h, z12\.h},[ \t]+{z31\.h-z0\.h},[ \t]+{z0-z1}\[0\]
> + *[0-9a-f]+:[ \t]+c13efc00[ \t]+luti6[ \t]+{z0\.h, z4\.h, z8\.h, z12\.h},[ \t]+{z0\.h-z1\.h},[ \t]+{z30-z31}\[0\]
> + *[0-9a-f]+:[ \t]+c13ffc00[ \t]+luti6[ \t]+{z0\.h, z4\.h, z8\.h, z12\.h},[ \t]+{z0\.h-z1\.h},[ \t]+{z31-z0}\[0\]
> +
> + *[0-9a-f]+:[ \t]+c160fc00[ \t]+luti6[ \t]+{z0\.h, z4\.h, z8\.h, z12\.h},[ \t]+{z0\.h-z1\.h},[ \t]+{z0-z1}\[1\]
> + *[0-9a-f]+:[ \t]+c160fc13[ \t]+luti6[ \t]+{z19\.h, z23\.h, z27\.h, z31\.h},[ \t]+{z0\.h-z1\.h},[ \t]+{z0-z1}\[1\]
> + *[0-9a-f]+:[ \t]+c160ffc0[ \t]+luti6[ \t]+{z0\.h, z4\.h, z8\.h, z12\.h},[ \t]+{z30\.h-z31\.h},[ \t]+{z0-z1}\[1\]
> + *[0-9a-f]+:[ \t]+c160ffe0[ \t]+luti6[ \t]+{z0\.h, z4\.h, z8\.h, z12\.h},[ \t]+{z31\.h-z0\.h},[ \t]+{z0-z1}\[1\]
> + *[0-9a-f]+:[ \t]+c17efc00[ \t]+luti6[ \t]+{z0\.h, z4\.h, z8\.h, z12\.h},[ \t]+{z0\.h-z1\.h},[ \t]+{z30-z31}\[1\]
> + *[0-9a-f]+:[ \t]+c17ffc00[ \t]+luti6[ \t]+{z0\.h, z4\.h, z8\.h, z12\.h},[ \t]+{z0\.h-z1\.h},[ \t]+{z31-z0}\[1\]
> diff --git a/gas/testsuite/gas/aarch64/luti6_vector16s4.s b/gas/testsuite/gas/aarch64/luti6_vector16s4.s
> new file mode 100644
> index 00000000000..374d954c277
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/luti6_vector16s4.s
> @@ -0,0 +1,13 @@
> +luti6 { z0.h, z4.h, z8.h, z12.h }, { z0.h, z1.h }, { z0-z1 }[0]
> +luti6 { z19.h, z23.h, z27.h, z31.h }, { z0.h, z1.h }, { z0-z1 }[0]
> +luti6 { z0.h, z4.h, z8.h, z12.h }, { z30.h, z31.h }, { z0-z1 }[0]
> +luti6 { z0.h, z4.h, z8.h, z12.h }, { z31.h, z0.h }, { z0-z1 }[0]
> +luti6 { z0.h, z4.h, z8.h, z12.h }, { z0.h, z1.h }, { z30-z31 }[0]
> +luti6 { z0.h, z4.h, z8.h, z12.h }, { z0.h, z1.h }, { z31-z0 }[0]
> +
> +luti6 { z0.h, z4.h, z8.h, z12.h }, { z0.h, z1.h }, { z0-z1 }[1]
> +luti6 { z19.h, z23.h, z27.h, z31.h }, { z0.h, z1.h }, { z0-z1 }[1]
> +luti6 { z0.h, z4.h, z8.h, z12.h }, { z30.h, z31.h }, { z0-z1 }[1]
> +luti6 { z0.h, z4.h, z8.h, z12.h }, { z31.h, z0.h }, { z0-z1 }[1]
> +luti6 { z0.h, z4.h, z8.h, z12.h }, { z0.h, z1.h }, { z30-z31 }[1]
> +luti6 { z0.h, z4.h, z8.h, z12.h }, { z0.h, z1.h }, { z31-z0 }[1]
> diff --git a/gas/testsuite/gas/aarch64/sabal.d b/gas/testsuite/gas/aarch64/sabal.d
> new file mode 100644
> index 00000000000..cb98f59e5cd
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/sabal.d
> @@ -0,0 +1,20 @@
> +#as: -march=armv8-a+sve2p3
> +#objdump: -dr
> +
> +.*: file format .*
> +
> +Disassembly of section \.text:
> +
> +0+ <\.text>:
> + *[0-9a-f]+:[ \t]+4440d400[ \t]+sabal[ \t]+z0\.h, z0\.b, z0\.b
> + *[0-9a-f]+:[ \t]+4440d41f[ \t]+sabal[ \t]+z31\.h, z0\.b, z0\.b
> + *[0-9a-f]+:[ \t]+4440d7e0[ \t]+sabal[ \t]+z0\.h, z31\.b, z0\.b
> + *[0-9a-f]+:[ \t]+445fd400[ \t]+sabal[ \t]+z0\.h, z0\.b, z31\.b
> + *[0-9a-f]+:[ \t]+4480d400[ \t]+sabal[ \t]+z0\.s, z0\.h, z0\.h
> + *[0-9a-f]+:[ \t]+4480d41f[ \t]+sabal[ \t]+z31\.s, z0\.h, z0\.h
> + *[0-9a-f]+:[ \t]+4480d7e0[ \t]+sabal[ \t]+z0\.s, z31\.h, z0\.h
> + *[0-9a-f]+:[ \t]+449fd400[ \t]+sabal[ \t]+z0\.s, z0\.h, z31\.h
> + *[0-9a-f]+:[ \t]+44c0d400[ \t]+sabal[ \t]+z0\.d, z0\.s, z0\.s
> + *[0-9a-f]+:[ \t]+44c0d41f[ \t]+sabal[ \t]+z31\.d, z0\.s, z0\.s
> + *[0-9a-f]+:[ \t]+44c0d7e0[ \t]+sabal[ \t]+z0\.d, z31\.s, z0\.s
> + *[0-9a-f]+:[ \t]+44dfd400[ \t]+sabal[ \t]+z0\.d, z0\.s, z31\.s
> diff --git a/gas/testsuite/gas/aarch64/sabal.s b/gas/testsuite/gas/aarch64/sabal.s
> new file mode 100644
> index 00000000000..fb6ad0c3a3a
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/sabal.s
> @@ -0,0 +1,12 @@
> +sabal z0.h, z0.b, z0.b
> +sabal z31.h, z0.b, z0.b
> +sabal z0.h, z31.b, z0.b
> +sabal z0.h, z0.b, z31.b
> +sabal z0.s, z0.h, z0.h
> +sabal z31.s, z0.h, z0.h
> +sabal z0.s, z31.h, z0.h
> +sabal z0.s, z0.h, z31.h
> +sabal z0.d, z0.s, z0.s
> +sabal z31.d, z0.s, z0.s
> +sabal z0.d, z31.s, z0.s
> +sabal z0.d, z0.s, z31.s
> diff --git a/gas/testsuite/gas/aarch64/scvtf.d b/gas/testsuite/gas/aarch64/scvtf.d
> new file mode 100644
> index 00000000000..5514fec364d
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/scvtf.d
> @@ -0,0 +1,17 @@
> +#as: -march=armv8-a+sve2p3
> +#objdump: -dr
> +
> +.*: file format .*
> +
> +Disassembly of section \.text:
> +
> +0+ <\.text>:
> + *[0-9a-f]+:[ \t]+654c3000[ \t]+scvtf[ \t]+z0\.h, z0\.b
> + *[0-9a-f]+:[ \t]+654c301f[ \t]+scvtf[ \t]+z31\.h, z0\.b
> + *[0-9a-f]+:[ \t]+654c33e0[ \t]+scvtf[ \t]+z0\.h, z31\.b
> + *[0-9a-f]+:[ \t]+658c3000[ \t]+scvtf[ \t]+z0\.s, z0\.h
> + *[0-9a-f]+:[ \t]+658c301f[ \t]+scvtf[ \t]+z31\.s, z0\.h
> + *[0-9a-f]+:[ \t]+658c33e0[ \t]+scvtf[ \t]+z0\.s, z31\.h
> + *[0-9a-f]+:[ \t]+65cc3000[ \t]+scvtf[ \t]+z0\.d, z0\.s
> + *[0-9a-f]+:[ \t]+65cc301f[ \t]+scvtf[ \t]+z31\.d, z0\.s
> + *[0-9a-f]+:[ \t]+65cc33e0[ \t]+scvtf[ \t]+z0\.d, z31\.s
> diff --git a/gas/testsuite/gas/aarch64/scvtf.s b/gas/testsuite/gas/aarch64/scvtf.s
> new file mode 100644
> index 00000000000..aa5ea8eaac4
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/scvtf.s
> @@ -0,0 +1,9 @@
> +scvtf z0.h, z0.b
> +scvtf z31.h, z0.b
> +scvtf z0.h, z31.b
> +scvtf z0.s, z0.h
> +scvtf z31.s, z0.h
> +scvtf z0.s, z31.h
> +scvtf z0.d, z0.s
> +scvtf z31.d, z0.s
> +scvtf z0.d, z31.s
> diff --git a/gas/testsuite/gas/aarch64/scvtflt.d b/gas/testsuite/gas/aarch64/scvtflt.d
> new file mode 100644
> index 00000000000..e1d5f6d9ca2
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/scvtflt.d
> @@ -0,0 +1,17 @@
> +#as: -march=armv8-a+sve2p3
> +#objdump: -dr
> +
> +.*: file format .*
> +
> +Disassembly of section \.text:
> +
> +0+ <\.text>:
> + *[0-9a-f]+:[ \t]+654c3800[ \t]+scvtflt[ \t]+z0\.h, z0\.b
> + *[0-9a-f]+:[ \t]+654c381f[ \t]+scvtflt[ \t]+z31\.h, z0\.b
> + *[0-9a-f]+:[ \t]+654c3be0[ \t]+scvtflt[ \t]+z0\.h, z31\.b
> + *[0-9a-f]+:[ \t]+658c3800[ \t]+scvtflt[ \t]+z0\.s, z0\.h
> + *[0-9a-f]+:[ \t]+658c381f[ \t]+scvtflt[ \t]+z31\.s, z0\.h
> + *[0-9a-f]+:[ \t]+658c3be0[ \t]+scvtflt[ \t]+z0\.s, z31\.h
> + *[0-9a-f]+:[ \t]+65cc3800[ \t]+scvtflt[ \t]+z0\.d, z0\.s
> + *[0-9a-f]+:[ \t]+65cc381f[ \t]+scvtflt[ \t]+z31\.d, z0\.s
> + *[0-9a-f]+:[ \t]+65cc3be0[ \t]+scvtflt[ \t]+z0\.d, z31\.s
> diff --git a/gas/testsuite/gas/aarch64/scvtflt.s b/gas/testsuite/gas/aarch64/scvtflt.s
> new file mode 100644
> index 00000000000..667fc581ecd
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/scvtflt.s
> @@ -0,0 +1,9 @@
> +scvtflt z0.h, z0.b
> +scvtflt z31.h, z0.b
> +scvtflt z0.h, z31.b
> +scvtflt z0.s, z0.h
> +scvtflt z31.s, z0.h
> +scvtflt z0.s, z31.h
> +scvtflt z0.d, z0.s
> +scvtflt z31.d, z0.s
> +scvtflt z0.d, z31.s
> diff --git a/gas/testsuite/gas/aarch64/sdot.d b/gas/testsuite/gas/aarch64/sdot.d
> new file mode 100644
> index 00000000000..dc64578a0af
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/sdot.d
> @@ -0,0 +1,64 @@
> +#as: -march=armv8-a+sve2p3
> +#objdump: -dr
> +
> +.*: file format .*
> +
> +Disassembly of section \.text:
> +
> +0+ <\.text>:
> + *[0-9a-f]+:[ \t]+44400000[ \t]+sdot[ \t]+z0\.h, z0\.b, z0\.b
> + *[0-9a-f]+:[ \t]+4440001f[ \t]+sdot[ \t]+z31\.h, z0\.b, z0\.b
> + *[0-9a-f]+:[ \t]+444003e0[ \t]+sdot[ \t]+z0\.h, z31\.b, z0\.b
> + *[0-9a-f]+:[ \t]+445f0000[ \t]+sdot[ \t]+z0\.h, z0\.b, z31\.b
> + *[0-9a-f]+:[ \t]+4400c800[ \t]+sdot[ \t]+z0\.s, z0.h, z0\.h
> + *[0-9a-f]+:[ \t]+4400c81f[ \t]+sdot[ \t]+z31\.s, z0.h, z0\.h
> + *[0-9a-f]+:[ \t]+4400cbe0[ \t]+sdot[ \t]+z0\.s, z31.h, z0\.h
> + *[0-9a-f]+:[ \t]+441fc800[ \t]+sdot[ \t]+z0\.s, z0.h, z31\.h
> + *[0-9a-f]+:[ \t]+44200000[ \t]+sdot[ \t]+z0\.h, z0\.b, z0\.b\[0\]
> + *[0-9a-f]+:[ \t]+4420001f[ \t]+sdot[ \t]+z31\.h, z0\.b, z0\.b\[0\]
> + *[0-9a-f]+:[ \t]+442003e0[ \t]+sdot[ \t]+z0\.h, z31\.b, z0\.b\[0\]
> + *[0-9a-f]+:[ \t]+44270000[ \t]+sdot[ \t]+z0\.h, z0\.b, z7\.b\[0\]
> + *[0-9a-f]+:[ \t]+44280000[ \t]+sdot[ \t]+z0\.h, z0\.b, z0\.b\[1\]
> + *[0-9a-f]+:[ \t]+4428001f[ \t]+sdot[ \t]+z31\.h, z0\.b, z0\.b\[1\]
> + *[0-9a-f]+:[ \t]+442803e0[ \t]+sdot[ \t]+z0\.h, z31\.b, z0\.b\[1\]
> + *[0-9a-f]+:[ \t]+442f0000[ \t]+sdot[ \t]+z0\.h, z0\.b, z7\.b\[1\]
> + *[0-9a-f]+:[ \t]+44300000[ \t]+sdot[ \t]+z0\.h, z0\.b, z0\.b\[2\]
> + *[0-9a-f]+:[ \t]+4430001f[ \t]+sdot[ \t]+z31\.h, z0\.b, z0\.b\[2\]
> + *[0-9a-f]+:[ \t]+443003e0[ \t]+sdot[ \t]+z0\.h, z31\.b, z0\.b\[2\]
> + *[0-9a-f]+:[ \t]+44370000[ \t]+sdot[ \t]+z0\.h, z0\.b, z7\.b\[2\]
> + *[0-9a-f]+:[ \t]+44380000[ \t]+sdot[ \t]+z0\.h, z0\.b, z0\.b\[3\]
> + *[0-9a-f]+:[ \t]+4438001f[ \t]+sdot[ \t]+z31\.h, z0\.b, z0\.b\[3\]
> + *[0-9a-f]+:[ \t]+443803e0[ \t]+sdot[ \t]+z0\.h, z31\.b, z0\.b\[3\]
> + *[0-9a-f]+:[ \t]+443f0000[ \t]+sdot[ \t]+z0\.h, z0\.b, z7\.b\[3\]
> + *[0-9a-f]+:[ \t]+44600000[ \t]+sdot[ \t]+z0\.h, z0\.b, z0\.b\[4\]
> + *[0-9a-f]+:[ \t]+4460001f[ \t]+sdot[ \t]+z31\.h, z0\.b, z0\.b\[4\]
> + *[0-9a-f]+:[ \t]+446003e0[ \t]+sdot[ \t]+z0\.h, z31\.b, z0\.b\[4\]
> + *[0-9a-f]+:[ \t]+44670000[ \t]+sdot[ \t]+z0\.h, z0\.b, z7\.b\[4\]
> + *[0-9a-f]+:[ \t]+44680000[ \t]+sdot[ \t]+z0\.h, z0\.b, z0\.b\[5\]
> + *[0-9a-f]+:[ \t]+4468001f[ \t]+sdot[ \t]+z31\.h, z0\.b, z0\.b\[5\]
> + *[0-9a-f]+:[ \t]+446803e0[ \t]+sdot[ \t]+z0\.h, z31\.b, z0\.b\[5\]
> + *[0-9a-f]+:[ \t]+446f0000[ \t]+sdot[ \t]+z0\.h, z0\.b, z7\.b\[5\]
> + *[0-9a-f]+:[ \t]+44700000[ \t]+sdot[ \t]+z0\.h, z0\.b, z0\.b\[6\]
> + *[0-9a-f]+:[ \t]+4470001f[ \t]+sdot[ \t]+z31\.h, z0\.b, z0\.b\[6\]
> + *[0-9a-f]+:[ \t]+447003e0[ \t]+sdot[ \t]+z0\.h, z31\.b, z0\.b\[6\]
> + *[0-9a-f]+:[ \t]+44770000[ \t]+sdot[ \t]+z0\.h, z0\.b, z7\.b\[6\]
> + *[0-9a-f]+:[ \t]+44780000[ \t]+sdot[ \t]+z0\.h, z0\.b, z0\.b\[7\]
> + *[0-9a-f]+:[ \t]+4478001f[ \t]+sdot[ \t]+z31\.h, z0\.b, z0\.b\[7\]
> + *[0-9a-f]+:[ \t]+447803e0[ \t]+sdot[ \t]+z0\.h, z31\.b, z0\.b\[7\]
> + *[0-9a-f]+:[ \t]+447f0000[ \t]+sdot[ \t]+z0\.h, z0\.b, z7\.b\[7\]
> + *[0-9a-f]+:[ \t]+4480c800[ \t]+sdot[ \t]+z0\.s, z0\.h, z0\.h\[0\]
> + *[0-9a-f]+:[ \t]+4480c81f[ \t]+sdot[ \t]+z31\.s, z0\.h, z0\.h\[0\]
> + *[0-9a-f]+:[ \t]+4480cbe0[ \t]+sdot[ \t]+z0\.s, z31\.h, z0\.h\[0\]
> + *[0-9a-f]+:[ \t]+4487c800[ \t]+sdot[ \t]+z0\.s, z0\.h, z7\.h\[0\]
> + *[0-9a-f]+:[ \t]+4488c800[ \t]+sdot[ \t]+z0\.s, z0\.h, z0\.h\[1\]
> + *[0-9a-f]+:[ \t]+4488c81f[ \t]+sdot[ \t]+z31\.s, z0\.h, z0\.h\[1\]
> + *[0-9a-f]+:[ \t]+4488cbe0[ \t]+sdot[ \t]+z0\.s, z31\.h, z0\.h\[1\]
> + *[0-9a-f]+:[ \t]+448fc800[ \t]+sdot[ \t]+z0\.s, z0\.h, z7\.h\[1\]
> + *[0-9a-f]+:[ \t]+4490c800[ \t]+sdot[ \t]+z0\.s, z0\.h, z0\.h\[2\]
> + *[0-9a-f]+:[ \t]+4490c81f[ \t]+sdot[ \t]+z31\.s, z0\.h, z0\.h\[2\]
> + *[0-9a-f]+:[ \t]+4490cbe0[ \t]+sdot[ \t]+z0\.s, z31\.h, z0\.h\[2\]
> + *[0-9a-f]+:[ \t]+4497c800[ \t]+sdot[ \t]+z0\.s, z0\.h, z7\.h\[2\]
> + *[0-9a-f]+:[ \t]+4498c800[ \t]+sdot[ \t]+z0\.s, z0\.h, z0\.h\[3\]
> + *[0-9a-f]+:[ \t]+4498c81f[ \t]+sdot[ \t]+z31\.s, z0\.h, z0\.h\[3\]
> + *[0-9a-f]+:[ \t]+4498cbe0[ \t]+sdot[ \t]+z0\.s, z31\.h, z0\.h\[3\]
> + *[0-9a-f]+:[ \t]+449fc800[ \t]+sdot[ \t]+z0\.s, z0\.h, z7\.h\[3\]
> diff --git a/gas/testsuite/gas/aarch64/sdot.s b/gas/testsuite/gas/aarch64/sdot.s
> new file mode 100644
> index 00000000000..ef59faa939f
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/sdot.s
> @@ -0,0 +1,56 @@
> +sdot z0.h, z0.b, z0.b
> +sdot z31.h, z0.b, z0.b
> +sdot z0.h, z31.b, z0.b
> +sdot z0.h, z0.b, z31.b
> +sdot z0.s, z0.h, z0.h
> +sdot z31.s, z0.h, z0.h
> +sdot z0.s, z31.h, z0.h
> +sdot z0.s, z0.h, z31.h
The half->single form is existing, so it doesn't need new tests.
> +sdot z0.h, z0.b, z0.b[0]
> +sdot z31.h, z0.b, z0.b[0]
> +sdot z0.h, z31.b, z0.b[0]
> +sdot z0.h, z0.b, z7.b[0]
> +sdot z0.h, z0.b, z0.b[1]
> +sdot z31.h, z0.b, z0.b[1]
> +sdot z0.h, z31.b, z0.b[1]
> +sdot z0.h, z0.b, z7.b[1]
> +sdot z0.h, z0.b, z0.b[2]
> +sdot z31.h, z0.b, z0.b[2]
> +sdot z0.h, z31.b, z0.b[2]
> +sdot z0.h, z0.b, z7.b[2]
> +sdot z0.h, z0.b, z0.b[3]
> +sdot z31.h, z0.b, z0.b[3]
> +sdot z0.h, z31.b, z0.b[3]
> +sdot z0.h, z0.b, z7.b[3]
> +sdot z0.h, z0.b, z0.b[4]
> +sdot z31.h, z0.b, z0.b[4]
> +sdot z0.h, z31.b, z0.b[4]
> +sdot z0.h, z0.b, z7.b[4]
> +sdot z0.h, z0.b, z0.b[5]
> +sdot z31.h, z0.b, z0.b[5]
> +sdot z0.h, z31.b, z0.b[5]
> +sdot z0.h, z0.b, z7.b[5]
> +sdot z0.h, z0.b, z0.b[6]
> +sdot z31.h, z0.b, z0.b[6]
> +sdot z0.h, z31.b, z0.b[6]
> +sdot z0.h, z0.b, z7.b[6]
> +sdot z0.h, z0.b, z0.b[7]
> +sdot z31.h, z0.b, z0.b[7]
> +sdot z0.h, z31.b, z0.b[7]
> +sdot z0.h, z0.b, z7.b[7]
You don't need this many cases to verify the instruction assembly - the index
and register numbers are unrelated so you don't need to test all combinations,
and you can test fewer indexes while still verifying that the opcode fields are
in the correct order. In this case I would only use:
+sdot z0.h, z0.b, z0.b[0]
+sdot z31.h, z0.b, z0.b[0]
+sdot z0.h, z31.b, z0.b[0]
+sdot z0.h, z0.b, z7.b[0]
+sdot z0.h, z0.b, z0.b[3]
+sdot z0.h, z0.b, z0.b[7]
> +sdot z0.s, z0.h, z0.h[0]
> +sdot z31.s, z0.h, z0.h[0]
> +sdot z0.s, z31.h, z0.h[0]
> +sdot z0.s, z0.h, z7.h[0]
> +sdot z0.s, z0.h, z0.h[1]
> +sdot z31.s, z0.h, z0.h[1]
> +sdot z0.s, z31.h, z0.h[1]
> +sdot z0.s, z0.h, z7.h[1]
> +sdot z0.s, z0.h, z0.h[2]
> +sdot z31.s, z0.h, z0.h[2]
> +sdot z0.s, z31.h, z0.h[2]
> +sdot z0.s, z0.h, z7.h[2]
> +sdot z0.s, z0.h, z0.h[3]
> +sdot z31.s, z0.h, z0.h[3]
> +sdot z0.s, z31.h, z0.h[3]
> +sdot z0.s, z0.h, z7.h[3]
> diff --git a/gas/testsuite/gas/aarch64/sqrshrn.d b/gas/testsuite/gas/aarch64/sqrshrn.d
> new file mode 100644
> index 00000000000..469c2e74f9c
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/sqrshrn.d
> @@ -0,0 +1,32 @@
> +#as: -march=armv8-a+sme2p3
> +#objdump: -dr
> +
> +.*: file format .*
> +
> +Disassembly of section \.text:
> +
> +0+ <\.text>:
> + *[0-9a-f]+:[ \t]+45a82800[ \t]+sqrshrn[ \t]+z0\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#8
> + *[0-9a-f]+:[ \t]+45a8281f[ \t]+sqrshrn[ \t]+z31\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#8
> + *[0-9a-f]+:[ \t]+45a82bc0[ \t]+sqrshrn[ \t]+z0\.b,[ \t]+{z30\.h-z31\.h},[ \t]+#8
> + *[0-9a-f]+:[ \t]+45a92800[ \t]+sqrshrn[ \t]+z0\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#7
> + *[0-9a-f]+:[ \t]+45a9281f[ \t]+sqrshrn[ \t]+z31\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#7
> + *[0-9a-f]+:[ \t]+45a92bc0[ \t]+sqrshrn[ \t]+z0\.b,[ \t]+{z30\.h-z31\.h},[ \t]+#7
> + *[0-9a-f]+:[ \t]+45aa2800[ \t]+sqrshrn[ \t]+z0\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#6
> + *[0-9a-f]+:[ \t]+45aa281f[ \t]+sqrshrn[ \t]+z31\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#6
> + *[0-9a-f]+:[ \t]+45aa2bc0[ \t]+sqrshrn[ \t]+z0\.b,[ \t]+{z30\.h-z31\.h},[ \t]+#6
> + *[0-9a-f]+:[ \t]+45ab2800[ \t]+sqrshrn[ \t]+z0\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#5
> + *[0-9a-f]+:[ \t]+45ab281f[ \t]+sqrshrn[ \t]+z31\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#5
> + *[0-9a-f]+:[ \t]+45ab2bc0[ \t]+sqrshrn[ \t]+z0\.b,[ \t]+{z30\.h-z31\.h},[ \t]+#5
> + *[0-9a-f]+:[ \t]+45ac2800[ \t]+sqrshrn[ \t]+z0\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#4
> + *[0-9a-f]+:[ \t]+45ac281f[ \t]+sqrshrn[ \t]+z31\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#4
> + *[0-9a-f]+:[ \t]+45ac2bc0[ \t]+sqrshrn[ \t]+z0\.b,[ \t]+{z30\.h-z31\.h},[ \t]+#4
> + *[0-9a-f]+:[ \t]+45ad2800[ \t]+sqrshrn[ \t]+z0\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#3
> + *[0-9a-f]+:[ \t]+45ad281f[ \t]+sqrshrn[ \t]+z31\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#3
> + *[0-9a-f]+:[ \t]+45ad2bc0[ \t]+sqrshrn[ \t]+z0\.b,[ \t]+{z30\.h-z31\.h},[ \t]+#3
> + *[0-9a-f]+:[ \t]+45ae2800[ \t]+sqrshrn[ \t]+z0\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#2
> + *[0-9a-f]+:[ \t]+45ae281f[ \t]+sqrshrn[ \t]+z31\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#2
> + *[0-9a-f]+:[ \t]+45ae2bc0[ \t]+sqrshrn[ \t]+z0\.b,[ \t]+{z30\.h-z31\.h},[ \t]+#2
> + *[0-9a-f]+:[ \t]+45af2800[ \t]+sqrshrn[ \t]+z0\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#1
> + *[0-9a-f]+:[ \t]+45af281f[ \t]+sqrshrn[ \t]+z31\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#1
> + *[0-9a-f]+:[ \t]+45af2bc0[ \t]+sqrshrn[ \t]+z0\.b,[ \t]+{z30\.h-z31\.h},[ \t]+#1
> diff --git a/gas/testsuite/gas/aarch64/sqrshrn.s b/gas/testsuite/gas/aarch64/sqrshrn.s
> new file mode 100644
> index 00000000000..50aec806180
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/sqrshrn.s
> @@ -0,0 +1,24 @@
> +sqrshrn z0.b, { z0.h-z1.h }, #8
> +sqrshrn z31.b, { z0.h-z1.h }, #8
> +sqrshrn z0.b, { z30.h-z31.h }, #8
> +sqrshrn z0.b, { z0.h-z1.h }, #7
> +sqrshrn z31.b, { z0.h-z1.h }, #7
> +sqrshrn z0.b, { z30.h-z31.h }, #7
> +sqrshrn z0.b, { z0.h-z1.h }, #6
> +sqrshrn z31.b, { z0.h-z1.h }, #6
> +sqrshrn z0.b, { z30.h-z31.h }, #6
> +sqrshrn z0.b, { z0.h-z1.h }, #5
> +sqrshrn z31.b, { z0.h-z1.h }, #5
> +sqrshrn z0.b, { z30.h-z31.h }, #5
> +sqrshrn z0.b, { z0.h-z1.h }, #4
> +sqrshrn z31.b, { z0.h-z1.h }, #4
> +sqrshrn z0.b, { z30.h-z31.h }, #4
> +sqrshrn z0.b, { z0.h-z1.h }, #3
> +sqrshrn z31.b, { z0.h-z1.h }, #3
> +sqrshrn z0.b, { z30.h-z31.h }, #3
> +sqrshrn z0.b, { z0.h-z1.h }, #2
> +sqrshrn z31.b, { z0.h-z1.h }, #2
> +sqrshrn z0.b, { z30.h-z31.h }, #2
> +sqrshrn z0.b, { z0.h-z1.h }, #1
> +sqrshrn z31.b, { z0.h-z1.h }, #1
> +sqrshrn z0.b, { z30.h-z31.h }, #1
Similarly, here I think it would be sufficient to test:
+sqrshrn z0.b, { z0.h-z1.h }, #8
+sqrshrn z31.b, { z0.h-z1.h }, #8
+sqrshrn z0.b, { z30.h-z31.h }, #8
+sqrshrn z0.b, { z0.h-z1.h }, #1
> diff --git a/gas/testsuite/gas/aarch64/sqrshrn_imm.d b/gas/testsuite/gas/aarch64/sqrshrn_imm.d
> new file mode 100644
> index 00000000000..3cb62d35c6d
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/sqrshrn_imm.d
> @@ -0,0 +1,80 @@
> +#as: -march=armv8-a+sme2p3
> +#objdump: -dr
> +
> +.*: file format .*
> +
> +Disassembly of section \.text:
> +
> +0+ <\.text>:
> + *[0-9a-f]+:[ \t]+45a80000[ \t]+sqshrn[ \t]+z0\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#8
> + *[0-9a-f]+:[ \t]+45a8001f[ \t]+sqshrn[ \t]+z31\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#8
> + *[0-9a-f]+:[ \t]+45a803c0[ \t]+sqshrn[ \t]+z0\.b,[ \t]+{z30\.h-z31\.h},[ \t]+#8
> + *[0-9a-f]+:[ \t]+45a90000[ \t]+sqshrn[ \t]+z0\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#7
> + *[0-9a-f]+:[ \t]+45a9001f[ \t]+sqshrn[ \t]+z31\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#7
> + *[0-9a-f]+:[ \t]+45a903c0[ \t]+sqshrn[ \t]+z0\.b,[ \t]+{z30\.h-z31\.h},[ \t]+#7
> + *[0-9a-f]+:[ \t]+45aa0000[ \t]+sqshrn[ \t]+z0\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#6
> + *[0-9a-f]+:[ \t]+45aa001f[ \t]+sqshrn[ \t]+z31\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#6
> + *[0-9a-f]+:[ \t]+45aa03c0[ \t]+sqshrn[ \t]+z0\.b,[ \t]+{z30\.h-z31\.h},[ \t]+#6
> + *[0-9a-f]+:[ \t]+45ab0000[ \t]+sqshrn[ \t]+z0\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#5
> + *[0-9a-f]+:[ \t]+45ab001f[ \t]+sqshrn[ \t]+z31\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#5
> + *[0-9a-f]+:[ \t]+45ab03c0[ \t]+sqshrn[ \t]+z0\.b,[ \t]+{z30\.h-z31\.h},[ \t]+#5
> + *[0-9a-f]+:[ \t]+45ac0000[ \t]+sqshrn[ \t]+z0\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#4
> + *[0-9a-f]+:[ \t]+45ac001f[ \t]+sqshrn[ \t]+z31\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#4
> + *[0-9a-f]+:[ \t]+45ac03c0[ \t]+sqshrn[ \t]+z0\.b,[ \t]+{z30\.h-z31\.h},[ \t]+#4
> + *[0-9a-f]+:[ \t]+45ad0000[ \t]+sqshrn[ \t]+z0\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#3
> + *[0-9a-f]+:[ \t]+45ad001f[ \t]+sqshrn[ \t]+z31\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#3
> + *[0-9a-f]+:[ \t]+45ad03c0[ \t]+sqshrn[ \t]+z0\.b,[ \t]+{z30\.h-z31\.h},[ \t]+#3
> + *[0-9a-f]+:[ \t]+45ae0000[ \t]+sqshrn[ \t]+z0\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#2
> + *[0-9a-f]+:[ \t]+45ae001f[ \t]+sqshrn[ \t]+z31\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#2
> + *[0-9a-f]+:[ \t]+45ae03c0[ \t]+sqshrn[ \t]+z0\.b,[ \t]+{z30\.h-z31\.h},[ \t]+#2
> + *[0-9a-f]+:[ \t]+45af0000[ \t]+sqshrn[ \t]+z0\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#1
> + *[0-9a-f]+:[ \t]+45af001f[ \t]+sqshrn[ \t]+z31\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#1
> + *[0-9a-f]+:[ \t]+45af03c0[ \t]+sqshrn[ \t]+z0\.b,[ \t]+{z30\.h-z31\.h},[ \t]+#1
> + *[0-9a-f]+:[ \t]+45b00000[ \t]+sqshrn[ \t]+z0\.h,[ \t]+{z0\.s-z1\.s},[ \t]+#16
> + *[0-9a-f]+:[ \t]+45b0001f[ \t]+sqshrn[ \t]+z31\.h,[ \t]+{z0\.s-z1\.s},[ \t]+#16
> + *[0-9a-f]+:[ \t]+45b003c0[ \t]+sqshrn[ \t]+z0\.h,[ \t]+{z30\.s-z31\.s},[ \t]+#16
> + *[0-9a-f]+:[ \t]+45b10000[ \t]+sqshrn[ \t]+z0\.h,[ \t]+{z0\.s-z1\.s},[ \t]+#15
> + *[0-9a-f]+:[ \t]+45b1001f[ \t]+sqshrn[ \t]+z31\.h,[ \t]+{z0\.s-z1\.s},[ \t]+#15
> + *[0-9a-f]+:[ \t]+45b103c0[ \t]+sqshrn[ \t]+z0\.h,[ \t]+{z30\.s-z31\.s},[ \t]+#15
> + *[0-9a-f]+:[ \t]+45b20000[ \t]+sqshrn[ \t]+z0\.h,[ \t]+{z0\.s-z1\.s},[ \t]+#14
> + *[0-9a-f]+:[ \t]+45b2001f[ \t]+sqshrn[ \t]+z31\.h,[ \t]+{z0\.s-z1\.s},[ \t]+#14
> + *[0-9a-f]+:[ \t]+45b203c0[ \t]+sqshrn[ \t]+z0\.h,[ \t]+{z30\.s-z31\.s},[ \t]+#14
> + *[0-9a-f]+:[ \t]+45b30000[ \t]+sqshrn[ \t]+z0\.h,[ \t]+{z0\.s-z1\.s},[ \t]+#13
> + *[0-9a-f]+:[ \t]+45b3001f[ \t]+sqshrn[ \t]+z31\.h,[ \t]+{z0\.s-z1\.s},[ \t]+#13
> + *[0-9a-f]+:[ \t]+45b303c0[ \t]+sqshrn[ \t]+z0\.h,[ \t]+{z30\.s-z31\.s},[ \t]+#13
> + *[0-9a-f]+:[ \t]+45b40000[ \t]+sqshrn[ \t]+z0\.h,[ \t]+{z0\.s-z1\.s},[ \t]+#12
> + *[0-9a-f]+:[ \t]+45b4001f[ \t]+sqshrn[ \t]+z31\.h,[ \t]+{z0\.s-z1\.s},[ \t]+#12
> + *[0-9a-f]+:[ \t]+45b403c0[ \t]+sqshrn[ \t]+z0\.h,[ \t]+{z30\.s-z31\.s},[ \t]+#12
> + *[0-9a-f]+:[ \t]+45b50000[ \t]+sqshrn[ \t]+z0\.h,[ \t]+{z0\.s-z1\.s},[ \t]+#11
> + *[0-9a-f]+:[ \t]+45b5001f[ \t]+sqshrn[ \t]+z31\.h,[ \t]+{z0\.s-z1\.s},[ \t]+#11
> + *[0-9a-f]+:[ \t]+45b503c0[ \t]+sqshrn[ \t]+z0\.h,[ \t]+{z30\.s-z31\.s},[ \t]+#11
> + *[0-9a-f]+:[ \t]+45b60000[ \t]+sqshrn[ \t]+z0\.h,[ \t]+{z0\.s-z1\.s},[ \t]+#10
> + *[0-9a-f]+:[ \t]+45b6001f[ \t]+sqshrn[ \t]+z31\.h,[ \t]+{z0\.s-z1\.s},[ \t]+#10
> + *[0-9a-f]+:[ \t]+45b603c0[ \t]+sqshrn[ \t]+z0\.h,[ \t]+{z30\.s-z31\.s},[ \t]+#10
> + *[0-9a-f]+:[ \t]+45b70000[ \t]+sqshrn[ \t]+z0\.h,[ \t]+{z0\.s-z1\.s},[ \t]+#9
> + *[0-9a-f]+:[ \t]+45b7001f[ \t]+sqshrn[ \t]+z31\.h,[ \t]+{z0\.s-z1\.s},[ \t]+#9
> + *[0-9a-f]+:[ \t]+45b703c0[ \t]+sqshrn[ \t]+z0\.h,[ \t]+{z30\.s-z31\.s},[ \t]+#9
> + *[0-9a-f]+:[ \t]+45b80000[ \t]+sqshrn[ \t]+z0\.h,[ \t]+{z0\.s-z1\.s},[ \t]+#8
> + *[0-9a-f]+:[ \t]+45b8001f[ \t]+sqshrn[ \t]+z31\.h,[ \t]+{z0\.s-z1\.s},[ \t]+#8
> + *[0-9a-f]+:[ \t]+45b803c0[ \t]+sqshrn[ \t]+z0\.h,[ \t]+{z30\.s-z31\.s},[ \t]+#8
> + *[0-9a-f]+:[ \t]+45b90000[ \t]+sqshrn[ \t]+z0\.h,[ \t]+{z0\.s-z1\.s},[ \t]+#7
> + *[0-9a-f]+:[ \t]+45b9001f[ \t]+sqshrn[ \t]+z31\.h,[ \t]+{z0\.s-z1\.s},[ \t]+#7
> + *[0-9a-f]+:[ \t]+45b903c0[ \t]+sqshrn[ \t]+z0\.h,[ \t]+{z30\.s-z31\.s},[ \t]+#7
> + *[0-9a-f]+:[ \t]+45ba0000[ \t]+sqshrn[ \t]+z0\.h,[ \t]+{z0\.s-z1\.s},[ \t]+#6
> + *[0-9a-f]+:[ \t]+45ba001f[ \t]+sqshrn[ \t]+z31\.h,[ \t]+{z0\.s-z1\.s},[ \t]+#6
> + *[0-9a-f]+:[ \t]+45ba03c0[ \t]+sqshrn[ \t]+z0\.h,[ \t]+{z30\.s-z31\.s},[ \t]+#6
> + *[0-9a-f]+:[ \t]+45bb0000[ \t]+sqshrn[ \t]+z0\.h,[ \t]+{z0\.s-z1\.s},[ \t]+#5
> + *[0-9a-f]+:[ \t]+45bb001f[ \t]+sqshrn[ \t]+z31\.h,[ \t]+{z0\.s-z1\.s},[ \t]+#5
> + *[0-9a-f]+:[ \t]+45bb03c0[ \t]+sqshrn[ \t]+z0\.h,[ \t]+{z30\.s-z31\.s},[ \t]+#5
> + *[0-9a-f]+:[ \t]+45bc0000[ \t]+sqshrn[ \t]+z0\.h,[ \t]+{z0\.s-z1\.s},[ \t]+#4
> + *[0-9a-f]+:[ \t]+45bc001f[ \t]+sqshrn[ \t]+z31\.h,[ \t]+{z0\.s-z1\.s},[ \t]+#4
> + *[0-9a-f]+:[ \t]+45bc03c0[ \t]+sqshrn[ \t]+z0\.h,[ \t]+{z30\.s-z31\.s},[ \t]+#4
> + *[0-9a-f]+:[ \t]+45bd0000[ \t]+sqshrn[ \t]+z0\.h,[ \t]+{z0\.s-z1\.s},[ \t]+#3
> + *[0-9a-f]+:[ \t]+45bd001f[ \t]+sqshrn[ \t]+z31\.h,[ \t]+{z0\.s-z1\.s},[ \t]+#3
> + *[0-9a-f]+:[ \t]+45bd03c0[ \t]+sqshrn[ \t]+z0\.h,[ \t]+{z30\.s-z31\.s},[ \t]+#3
> + *[0-9a-f]+:[ \t]+45be0000[ \t]+sqshrn[ \t]+z0\.h,[ \t]+{z0\.s-z1\.s},[ \t]+#2
> + *[0-9a-f]+:[ \t]+45be001f[ \t]+sqshrn[ \t]+z31\.h,[ \t]+{z0\.s-z1\.s},[ \t]+#2
> + *[0-9a-f]+:[ \t]+45be03c0[ \t]+sqshrn[ \t]+z0\.h,[ \t]+{z30\.s-z31\.s},[ \t]+#2
> + *[0-9a-f]+:[ \t]+45bf0000[ \t]+sqshrn[ \t]+z0\.h,[ \t]+{z0\.s-z1\.s},[ \t]+#1
> + *[0-9a-f]+:[ \t]+45bf001f[ \t]+sqshrn[ \t]+z31\.h,[ \t]+{z0\.s-z1\.s},[ \t]+#1
> + *[0-9a-f]+:[ \t]+45bf03c0[ \t]+sqshrn[ \t]+z0\.h,[ \t]+{z30\.s-z31\.s},[ \t]+#1
> diff --git a/gas/testsuite/gas/aarch64/sqrshrn_imm.s b/gas/testsuite/gas/aarch64/sqrshrn_imm.s
> new file mode 100644
> index 00000000000..1978909f292
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/sqrshrn_imm.s
> @@ -0,0 +1,72 @@
> +sqshrn z0.b, { z0.h-z1.h }, #8
> +sqshrn z31.b, { z0.h-z1.h }, #8
> +sqshrn z0.b, { z30.h-z31.h }, #8
> +sqshrn z0.b, { z0.h-z1.h }, #7
> +sqshrn z31.b, { z0.h-z1.h }, #7
> +sqshrn z0.b, { z30.h-z31.h }, #7
> +sqshrn z0.b, { z0.h-z1.h }, #6
> +sqshrn z31.b, { z0.h-z1.h }, #6
> +sqshrn z0.b, { z30.h-z31.h }, #6
> +sqshrn z0.b, { z0.h-z1.h }, #5
> +sqshrn z31.b, { z0.h-z1.h }, #5
> +sqshrn z0.b, { z30.h-z31.h }, #5
> +sqshrn z0.b, { z0.h-z1.h }, #4
> +sqshrn z31.b, { z0.h-z1.h }, #4
> +sqshrn z0.b, { z30.h-z31.h }, #4
> +sqshrn z0.b, { z0.h-z1.h }, #3
> +sqshrn z31.b, { z0.h-z1.h }, #3
> +sqshrn z0.b, { z30.h-z31.h }, #3
> +sqshrn z0.b, { z0.h-z1.h }, #2
> +sqshrn z31.b, { z0.h-z1.h }, #2
> +sqshrn z0.b, { z30.h-z31.h }, #2
> +sqshrn z0.b, { z0.h-z1.h }, #1
> +sqshrn z31.b, { z0.h-z1.h }, #1
> +sqshrn z0.b, { z30.h-z31.h }, #1
> +sqshrn z0.h, { z0.s-z1.s }, #16
> +sqshrn z31.h, { z0.s-z1.s }, #16
> +sqshrn z0.h, { z30.s-z31.s }, #16
> +sqshrn z0.h, { z0.s-z1.s }, #15
> +sqshrn z31.h, { z0.s-z1.s }, #15
> +sqshrn z0.h, { z30.s-z31.s }, #15
> +sqshrn z0.h, { z0.s-z1.s }, #14
> +sqshrn z31.h, { z0.s-z1.s }, #14
> +sqshrn z0.h, { z30.s-z31.s }, #14
> +sqshrn z0.h, { z0.s-z1.s }, #13
> +sqshrn z31.h, { z0.s-z1.s }, #13
> +sqshrn z0.h, { z30.s-z31.s }, #13
> +sqshrn z0.h, { z0.s-z1.s }, #12
> +sqshrn z31.h, { z0.s-z1.s }, #12
> +sqshrn z0.h, { z30.s-z31.s }, #12
> +sqshrn z0.h, { z0.s-z1.s }, #11
> +sqshrn z31.h, { z0.s-z1.s }, #11
> +sqshrn z0.h, { z30.s-z31.s }, #11
> +sqshrn z0.h, { z0.s-z1.s }, #10
> +sqshrn z31.h, { z0.s-z1.s }, #10
> +sqshrn z0.h, { z30.s-z31.s }, #10
> +sqshrn z0.h, { z0.s-z1.s }, #9
> +sqshrn z31.h, { z0.s-z1.s }, #9
> +sqshrn z0.h, { z30.s-z31.s }, #9
> +sqshrn z0.h, { z0.s-z1.s }, #8
> +sqshrn z31.h, { z0.s-z1.s }, #8
> +sqshrn z0.h, { z30.s-z31.s }, #8
> +sqshrn z0.h, { z0.s-z1.s }, #7
> +sqshrn z31.h, { z0.s-z1.s }, #7
> +sqshrn z0.h, { z30.s-z31.s }, #7
> +sqshrn z0.h, { z0.s-z1.s }, #6
> +sqshrn z31.h, { z0.s-z1.s }, #6
> +sqshrn z0.h, { z30.s-z31.s }, #6
> +sqshrn z0.h, { z0.s-z1.s }, #5
> +sqshrn z31.h, { z0.s-z1.s }, #5
> +sqshrn z0.h, { z30.s-z31.s }, #5
> +sqshrn z0.h, { z0.s-z1.s }, #4
> +sqshrn z31.h, { z0.s-z1.s }, #4
> +sqshrn z0.h, { z30.s-z31.s }, #4
> +sqshrn z0.h, { z0.s-z1.s }, #3
> +sqshrn z31.h, { z0.s-z1.s }, #3
> +sqshrn z0.h, { z30.s-z31.s }, #3
> +sqshrn z0.h, { z0.s-z1.s }, #2
> +sqshrn z31.h, { z0.s-z1.s }, #2
> +sqshrn z0.h, { z30.s-z31.s }, #2
> +sqshrn z0.h, { z0.s-z1.s }, #1
> +sqshrn z31.h, { z0.s-z1.s }, #1
> +sqshrn z0.h, { z30.s-z31.s }, #1
> diff --git a/gas/testsuite/gas/aarch64/sqrshrun.d b/gas/testsuite/gas/aarch64/sqrshrun.d
> new file mode 100644
> index 00000000000..265b4b8c5e6
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/sqrshrun.d
> @@ -0,0 +1,32 @@
> +#as: -march=armv8-a+sme2p3
> +#objdump: -dr
> +
> +.*: file format .*
> +
> +Disassembly of section \.text:
> +
> +0+ <\.text>:
> + *[0-9a-f]+:[ \t]+45a80800[ \t]+sqrshrun[ \t]+z0\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#8
> + *[0-9a-f]+:[ \t]+45a8081f[ \t]+sqrshrun[ \t]+z31\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#8
> + *[0-9a-f]+:[ \t]+45a80bc0[ \t]+sqrshrun[ \t]+z0\.b,[ \t]+{z30\.h-z31\.h},[ \t]+#8
> + *[0-9a-f]+:[ \t]+45a90800[ \t]+sqrshrun[ \t]+z0\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#7
> + *[0-9a-f]+:[ \t]+45a9081f[ \t]+sqrshrun[ \t]+z31\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#7
> + *[0-9a-f]+:[ \t]+45a90bc0[ \t]+sqrshrun[ \t]+z0\.b,[ \t]+{z30\.h-z31\.h},[ \t]+#7
> + *[0-9a-f]+:[ \t]+45aa0800[ \t]+sqrshrun[ \t]+z0\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#6
> + *[0-9a-f]+:[ \t]+45aa081f[ \t]+sqrshrun[ \t]+z31\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#6
> + *[0-9a-f]+:[ \t]+45aa0bc0[ \t]+sqrshrun[ \t]+z0\.b,[ \t]+{z30\.h-z31\.h},[ \t]+#6
> + *[0-9a-f]+:[ \t]+45ab0800[ \t]+sqrshrun[ \t]+z0\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#5
> + *[0-9a-f]+:[ \t]+45ab081f[ \t]+sqrshrun[ \t]+z31\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#5
> + *[0-9a-f]+:[ \t]+45ab0bc0[ \t]+sqrshrun[ \t]+z0\.b,[ \t]+{z30\.h-z31\.h},[ \t]+#5
> + *[0-9a-f]+:[ \t]+45ac0800[ \t]+sqrshrun[ \t]+z0\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#4
> + *[0-9a-f]+:[ \t]+45ac081f[ \t]+sqrshrun[ \t]+z31\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#4
> + *[0-9a-f]+:[ \t]+45ac0bc0[ \t]+sqrshrun[ \t]+z0\.b,[ \t]+{z30\.h-z31\.h},[ \t]+#4
> + *[0-9a-f]+:[ \t]+45ad0800[ \t]+sqrshrun[ \t]+z0\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#3
> + *[0-9a-f]+:[ \t]+45ad081f[ \t]+sqrshrun[ \t]+z31\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#3
> + *[0-9a-f]+:[ \t]+45ad0bc0[ \t]+sqrshrun[ \t]+z0\.b,[ \t]+{z30\.h-z31\.h},[ \t]+#3
> + *[0-9a-f]+:[ \t]+45ae0800[ \t]+sqrshrun[ \t]+z0\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#2
> + *[0-9a-f]+:[ \t]+45ae081f[ \t]+sqrshrun[ \t]+z31\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#2
> + *[0-9a-f]+:[ \t]+45ae0bc0[ \t]+sqrshrun[ \t]+z0\.b,[ \t]+{z30\.h-z31\.h},[ \t]+#2
> + *[0-9a-f]+:[ \t]+45af0800[ \t]+sqrshrun[ \t]+z0\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#1
> + *[0-9a-f]+:[ \t]+45af081f[ \t]+sqrshrun[ \t]+z31\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#1
> + *[0-9a-f]+:[ \t]+45af0bc0[ \t]+sqrshrun[ \t]+z0\.b,[ \t]+{z30\.h-z31\.h},[ \t]+#1
> diff --git a/gas/testsuite/gas/aarch64/sqrshrun.s b/gas/testsuite/gas/aarch64/sqrshrun.s
> new file mode 100644
> index 00000000000..ebd8fa13e5e
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/sqrshrun.s
> @@ -0,0 +1,24 @@
> +sqrshrun z0.b, { z0.h-z1.h }, #8
> +sqrshrun z31.b, { z0.h-z1.h }, #8
> +sqrshrun z0.b, { z30.h-z31.h }, #8
> +sqrshrun z0.b, { z0.h-z1.h }, #7
> +sqrshrun z31.b, { z0.h-z1.h }, #7
> +sqrshrun z0.b, { z30.h-z31.h }, #7
> +sqrshrun z0.b, { z0.h-z1.h }, #6
> +sqrshrun z31.b, { z0.h-z1.h }, #6
> +sqrshrun z0.b, { z30.h-z31.h }, #6
> +sqrshrun z0.b, { z0.h-z1.h }, #5
> +sqrshrun z31.b, { z0.h-z1.h }, #5
> +sqrshrun z0.b, { z30.h-z31.h }, #5
> +sqrshrun z0.b, { z0.h-z1.h }, #4
> +sqrshrun z31.b, { z0.h-z1.h }, #4
> +sqrshrun z0.b, { z30.h-z31.h }, #4
> +sqrshrun z0.b, { z0.h-z1.h }, #3
> +sqrshrun z31.b, { z0.h-z1.h }, #3
> +sqrshrun z0.b, { z30.h-z31.h }, #3
> +sqrshrun z0.b, { z0.h-z1.h }, #2
> +sqrshrun z31.b, { z0.h-z1.h }, #2
> +sqrshrun z0.b, { z30.h-z31.h }, #2
> +sqrshrun z0.b, { z0.h-z1.h }, #1
> +sqrshrun z31.b, { z0.h-z1.h }, #1
> +sqrshrun z0.b, { z30.h-z31.h }, #1
> diff --git a/gas/testsuite/gas/aarch64/sqshrun_imm.d b/gas/testsuite/gas/aarch64/sqshrun_imm.d
> new file mode 100644
> index 00000000000..f8663b1e3d6
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/sqshrun_imm.d
> @@ -0,0 +1,80 @@
> +#as: -march=armv8-a+sme2p3
> +#objdump: -dr
> +
> +.*: file format .*
> +
> +Disassembly of section \.text:
> +
> +0+ <\.text>:
> + *[0-9a-f]+:[ \t]+45a82000[ \t]+sqshrun[ \t]+z0\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#8
> + *[0-9a-f]+:[ \t]+45a8201f[ \t]+sqshrun[ \t]+z31\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#8
> + *[0-9a-f]+:[ \t]+45a823c0[ \t]+sqshrun[ \t]+z0\.b,[ \t]+{z30\.h-z31\.h},[ \t]+#8
> + *[0-9a-f]+:[ \t]+45a92000[ \t]+sqshrun[ \t]+z0\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#7
> + *[0-9a-f]+:[ \t]+45a9201f[ \t]+sqshrun[ \t]+z31\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#7
> + *[0-9a-f]+:[ \t]+45a923c0[ \t]+sqshrun[ \t]+z0\.b,[ \t]+{z30\.h-z31\.h},[ \t]+#7
> + *[0-9a-f]+:[ \t]+45aa2000[ \t]+sqshrun[ \t]+z0\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#6
> + *[0-9a-f]+:[ \t]+45aa201f[ \t]+sqshrun[ \t]+z31\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#6
> + *[0-9a-f]+:[ \t]+45aa23c0[ \t]+sqshrun[ \t]+z0\.b,[ \t]+{z30\.h-z31\.h},[ \t]+#6
> + *[0-9a-f]+:[ \t]+45ab2000[ \t]+sqshrun[ \t]+z0\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#5
> + *[0-9a-f]+:[ \t]+45ab201f[ \t]+sqshrun[ \t]+z31\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#5
> + *[0-9a-f]+:[ \t]+45ab23c0[ \t]+sqshrun[ \t]+z0\.b,[ \t]+{z30\.h-z31\.h},[ \t]+#5
> + *[0-9a-f]+:[ \t]+45ac2000[ \t]+sqshrun[ \t]+z0\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#4
> + *[0-9a-f]+:[ \t]+45ac201f[ \t]+sqshrun[ \t]+z31\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#4
> + *[0-9a-f]+:[ \t]+45ac23c0[ \t]+sqshrun[ \t]+z0\.b,[ \t]+{z30\.h-z31\.h},[ \t]+#4
> + *[0-9a-f]+:[ \t]+45ad2000[ \t]+sqshrun[ \t]+z0\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#3
> + *[0-9a-f]+:[ \t]+45ad201f[ \t]+sqshrun[ \t]+z31\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#3
> + *[0-9a-f]+:[ \t]+45ad23c0[ \t]+sqshrun[ \t]+z0\.b,[ \t]+{z30\.h-z31\.h},[ \t]+#3
> + *[0-9a-f]+:[ \t]+45ae2000[ \t]+sqshrun[ \t]+z0\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#2
> + *[0-9a-f]+:[ \t]+45ae201f[ \t]+sqshrun[ \t]+z31\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#2
> + *[0-9a-f]+:[ \t]+45ae23c0[ \t]+sqshrun[ \t]+z0\.b,[ \t]+{z30\.h-z31\.h},[ \t]+#2
> + *[0-9a-f]+:[ \t]+45af2000[ \t]+sqshrun[ \t]+z0\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#1
> + *[0-9a-f]+:[ \t]+45af201f[ \t]+sqshrun[ \t]+z31\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#1
> + *[0-9a-f]+:[ \t]+45af23c0[ \t]+sqshrun[ \t]+z0\.b,[ \t]+{z30\.h-z31\.h},[ \t]+#1
> + *[0-9a-f]+:[ \t]+45b02000[ \t]+sqshrun[ \t]+z0\.h,[ \t]+{z0\.s-z1\.s},[ \t]+#16
> + *[0-9a-f]+:[ \t]+45b0201f[ \t]+sqshrun[ \t]+z31\.h,[ \t]+{z0\.s-z1\.s},[ \t]+#16
> + *[0-9a-f]+:[ \t]+45b023c0[ \t]+sqshrun[ \t]+z0\.h,[ \t]+{z30\.s-z31\.s},[ \t]+#16
> + *[0-9a-f]+:[ \t]+45b12000[ \t]+sqshrun[ \t]+z0\.h,[ \t]+{z0\.s-z1\.s},[ \t]+#15
> + *[0-9a-f]+:[ \t]+45b1201f[ \t]+sqshrun[ \t]+z31\.h,[ \t]+{z0\.s-z1\.s},[ \t]+#15
> + *[0-9a-f]+:[ \t]+45b123c0[ \t]+sqshrun[ \t]+z0\.h,[ \t]+{z30\.s-z31\.s},[ \t]+#15
> + *[0-9a-f]+:[ \t]+45b22000[ \t]+sqshrun[ \t]+z0\.h,[ \t]+{z0\.s-z1\.s},[ \t]+#14
> + *[0-9a-f]+:[ \t]+45b2201f[ \t]+sqshrun[ \t]+z31\.h,[ \t]+{z0\.s-z1\.s},[ \t]+#14
> + *[0-9a-f]+:[ \t]+45b223c0[ \t]+sqshrun[ \t]+z0\.h,[ \t]+{z30\.s-z31\.s},[ \t]+#14
> + *[0-9a-f]+:[ \t]+45b32000[ \t]+sqshrun[ \t]+z0\.h,[ \t]+{z0\.s-z1\.s},[ \t]+#13
> + *[0-9a-f]+:[ \t]+45b3201f[ \t]+sqshrun[ \t]+z31\.h,[ \t]+{z0\.s-z1\.s},[ \t]+#13
> + *[0-9a-f]+:[ \t]+45b323c0[ \t]+sqshrun[ \t]+z0\.h,[ \t]+{z30\.s-z31\.s},[ \t]+#13
> + *[0-9a-f]+:[ \t]+45b42000[ \t]+sqshrun[ \t]+z0\.h,[ \t]+{z0\.s-z1\.s},[ \t]+#12
> + *[0-9a-f]+:[ \t]+45b4201f[ \t]+sqshrun[ \t]+z31\.h,[ \t]+{z0\.s-z1\.s},[ \t]+#12
> + *[0-9a-f]+:[ \t]+45b423c0[ \t]+sqshrun[ \t]+z0\.h,[ \t]+{z30\.s-z31\.s},[ \t]+#12
> + *[0-9a-f]+:[ \t]+45b52000[ \t]+sqshrun[ \t]+z0\.h,[ \t]+{z0\.s-z1\.s},[ \t]+#11
> + *[0-9a-f]+:[ \t]+45b5201f[ \t]+sqshrun[ \t]+z31\.h,[ \t]+{z0\.s-z1\.s},[ \t]+#11
> + *[0-9a-f]+:[ \t]+45b523c0[ \t]+sqshrun[ \t]+z0\.h,[ \t]+{z30\.s-z31\.s},[ \t]+#11
> + *[0-9a-f]+:[ \t]+45b62000[ \t]+sqshrun[ \t]+z0\.h,[ \t]+{z0\.s-z1\.s},[ \t]+#10
> + *[0-9a-f]+:[ \t]+45b6201f[ \t]+sqshrun[ \t]+z31\.h,[ \t]+{z0\.s-z1\.s},[ \t]+#10
> + *[0-9a-f]+:[ \t]+45b623c0[ \t]+sqshrun[ \t]+z0\.h,[ \t]+{z30\.s-z31\.s},[ \t]+#10
> + *[0-9a-f]+:[ \t]+45b72000[ \t]+sqshrun[ \t]+z0\.h,[ \t]+{z0\.s-z1\.s},[ \t]+#9
> + *[0-9a-f]+:[ \t]+45b7201f[ \t]+sqshrun[ \t]+z31\.h,[ \t]+{z0\.s-z1\.s},[ \t]+#9
> + *[0-9a-f]+:[ \t]+45b723c0[ \t]+sqshrun[ \t]+z0\.h,[ \t]+{z30\.s-z31\.s},[ \t]+#9
> + *[0-9a-f]+:[ \t]+45b82000[ \t]+sqshrun[ \t]+z0\.h,[ \t]+{z0\.s-z1\.s},[ \t]+#8
> + *[0-9a-f]+:[ \t]+45b8201f[ \t]+sqshrun[ \t]+z31\.h,[ \t]+{z0\.s-z1\.s},[ \t]+#8
> + *[0-9a-f]+:[ \t]+45b823c0[ \t]+sqshrun[ \t]+z0\.h,[ \t]+{z30\.s-z31\.s},[ \t]+#8
> + *[0-9a-f]+:[ \t]+45b92000[ \t]+sqshrun[ \t]+z0\.h,[ \t]+{z0\.s-z1\.s},[ \t]+#7
> + *[0-9a-f]+:[ \t]+45b9201f[ \t]+sqshrun[ \t]+z31\.h,[ \t]+{z0\.s-z1\.s},[ \t]+#7
> + *[0-9a-f]+:[ \t]+45b923c0[ \t]+sqshrun[ \t]+z0\.h,[ \t]+{z30\.s-z31\.s},[ \t]+#7
> + *[0-9a-f]+:[ \t]+45ba2000[ \t]+sqshrun[ \t]+z0\.h,[ \t]+{z0\.s-z1\.s},[ \t]+#6
> + *[0-9a-f]+:[ \t]+45ba201f[ \t]+sqshrun[ \t]+z31\.h,[ \t]+{z0\.s-z1\.s},[ \t]+#6
> + *[0-9a-f]+:[ \t]+45ba23c0[ \t]+sqshrun[ \t]+z0\.h,[ \t]+{z30\.s-z31\.s},[ \t]+#6
> + *[0-9a-f]+:[ \t]+45bb2000[ \t]+sqshrun[ \t]+z0\.h,[ \t]+{z0\.s-z1\.s},[ \t]+#5
> + *[0-9a-f]+:[ \t]+45bb201f[ \t]+sqshrun[ \t]+z31\.h,[ \t]+{z0\.s-z1\.s},[ \t]+#5
> + *[0-9a-f]+:[ \t]+45bb23c0[ \t]+sqshrun[ \t]+z0\.h,[ \t]+{z30\.s-z31\.s},[ \t]+#5
> + *[0-9a-f]+:[ \t]+45bc2000[ \t]+sqshrun[ \t]+z0\.h,[ \t]+{z0\.s-z1\.s},[ \t]+#4
> + *[0-9a-f]+:[ \t]+45bc201f[ \t]+sqshrun[ \t]+z31\.h,[ \t]+{z0\.s-z1\.s},[ \t]+#4
> + *[0-9a-f]+:[ \t]+45bc23c0[ \t]+sqshrun[ \t]+z0\.h,[ \t]+{z30\.s-z31\.s},[ \t]+#4
> + *[0-9a-f]+:[ \t]+45bd2000[ \t]+sqshrun[ \t]+z0\.h,[ \t]+{z0\.s-z1\.s},[ \t]+#3
> + *[0-9a-f]+:[ \t]+45bd201f[ \t]+sqshrun[ \t]+z31\.h,[ \t]+{z0\.s-z1\.s},[ \t]+#3
> + *[0-9a-f]+:[ \t]+45bd23c0[ \t]+sqshrun[ \t]+z0\.h,[ \t]+{z30\.s-z31\.s},[ \t]+#3
> + *[0-9a-f]+:[ \t]+45be2000[ \t]+sqshrun[ \t]+z0\.h,[ \t]+{z0\.s-z1\.s},[ \t]+#2
> + *[0-9a-f]+:[ \t]+45be201f[ \t]+sqshrun[ \t]+z31\.h,[ \t]+{z0\.s-z1\.s},[ \t]+#2
> + *[0-9a-f]+:[ \t]+45be23c0[ \t]+sqshrun[ \t]+z0\.h,[ \t]+{z30\.s-z31\.s},[ \t]+#2
> + *[0-9a-f]+:[ \t]+45bf2000[ \t]+sqshrun[ \t]+z0\.h,[ \t]+{z0\.s-z1\.s},[ \t]+#1
> + *[0-9a-f]+:[ \t]+45bf201f[ \t]+sqshrun[ \t]+z31\.h,[ \t]+{z0\.s-z1\.s},[ \t]+#1
> + *[0-9a-f]+:[ \t]+45bf23c0[ \t]+sqshrun[ \t]+z0\.h,[ \t]+{z30\.s-z31\.s},[ \t]+#1
> diff --git a/gas/testsuite/gas/aarch64/sqshrun_imm.s b/gas/testsuite/gas/aarch64/sqshrun_imm.s
> new file mode 100644
> index 00000000000..827baf8b0dc
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/sqshrun_imm.s
> @@ -0,0 +1,72 @@
> +sqshrun z0.b, { z0.h-z1.h }, #8
> +sqshrun z31.b, { z0.h-z1.h }, #8
> +sqshrun z0.b, { z30.h-z31.h }, #8
> +sqshrun z0.b, { z0.h-z1.h }, #7
> +sqshrun z31.b, { z0.h-z1.h }, #7
> +sqshrun z0.b, { z30.h-z31.h }, #7
> +sqshrun z0.b, { z0.h-z1.h }, #6
> +sqshrun z31.b, { z0.h-z1.h }, #6
> +sqshrun z0.b, { z30.h-z31.h }, #6
> +sqshrun z0.b, { z0.h-z1.h }, #5
> +sqshrun z31.b, { z0.h-z1.h }, #5
> +sqshrun z0.b, { z30.h-z31.h }, #5
> +sqshrun z0.b, { z0.h-z1.h }, #4
> +sqshrun z31.b, { z0.h-z1.h }, #4
> +sqshrun z0.b, { z30.h-z31.h }, #4
> +sqshrun z0.b, { z0.h-z1.h }, #3
> +sqshrun z31.b, { z0.h-z1.h }, #3
> +sqshrun z0.b, { z30.h-z31.h }, #3
> +sqshrun z0.b, { z0.h-z1.h }, #2
> +sqshrun z31.b, { z0.h-z1.h }, #2
> +sqshrun z0.b, { z30.h-z31.h }, #2
> +sqshrun z0.b, { z0.h-z1.h }, #1
> +sqshrun z31.b, { z0.h-z1.h }, #1
> +sqshrun z0.b, { z30.h-z31.h }, #1
> +sqshrun z0.h, { z0.s-z1.s }, #16
> +sqshrun z31.h, { z0.s-z1.s }, #16
> +sqshrun z0.h, { z30.s-z31.s }, #16
> +sqshrun z0.h, { z0.s-z1.s }, #15
> +sqshrun z31.h, { z0.s-z1.s }, #15
> +sqshrun z0.h, { z30.s-z31.s }, #15
> +sqshrun z0.h, { z0.s-z1.s }, #14
> +sqshrun z31.h, { z0.s-z1.s }, #14
> +sqshrun z0.h, { z30.s-z31.s }, #14
> +sqshrun z0.h, { z0.s-z1.s }, #13
> +sqshrun z31.h, { z0.s-z1.s }, #13
> +sqshrun z0.h, { z30.s-z31.s }, #13
> +sqshrun z0.h, { z0.s-z1.s }, #12
> +sqshrun z31.h, { z0.s-z1.s }, #12
> +sqshrun z0.h, { z30.s-z31.s }, #12
> +sqshrun z0.h, { z0.s-z1.s }, #11
> +sqshrun z31.h, { z0.s-z1.s }, #11
> +sqshrun z0.h, { z30.s-z31.s }, #11
> +sqshrun z0.h, { z0.s-z1.s }, #10
> +sqshrun z31.h, { z0.s-z1.s }, #10
> +sqshrun z0.h, { z30.s-z31.s }, #10
> +sqshrun z0.h, { z0.s-z1.s }, #9
> +sqshrun z31.h, { z0.s-z1.s }, #9
> +sqshrun z0.h, { z30.s-z31.s }, #9
> +sqshrun z0.h, { z0.s-z1.s }, #8
> +sqshrun z31.h, { z0.s-z1.s }, #8
> +sqshrun z0.h, { z30.s-z31.s }, #8
> +sqshrun z0.h, { z0.s-z1.s }, #7
> +sqshrun z31.h, { z0.s-z1.s }, #7
> +sqshrun z0.h, { z30.s-z31.s }, #7
> +sqshrun z0.h, { z0.s-z1.s }, #6
> +sqshrun z31.h, { z0.s-z1.s }, #6
> +sqshrun z0.h, { z30.s-z31.s }, #6
> +sqshrun z0.h, { z0.s-z1.s }, #5
> +sqshrun z31.h, { z0.s-z1.s }, #5
> +sqshrun z0.h, { z30.s-z31.s }, #5
> +sqshrun z0.h, { z0.s-z1.s }, #4
> +sqshrun z31.h, { z0.s-z1.s }, #4
> +sqshrun z0.h, { z30.s-z31.s }, #4
> +sqshrun z0.h, { z0.s-z1.s }, #3
> +sqshrun z31.h, { z0.s-z1.s }, #3
> +sqshrun z0.h, { z30.s-z31.s }, #3
> +sqshrun z0.h, { z0.s-z1.s }, #2
> +sqshrun z31.h, { z0.s-z1.s }, #2
> +sqshrun z0.h, { z30.s-z31.s }, #2
> +sqshrun z0.h, { z0.s-z1.s }, #1
> +sqshrun z31.h, { z0.s-z1.s }, #1
> +sqshrun z0.h, { z30.s-z31.s }, #1
> diff --git a/gas/testsuite/gas/aarch64/subp.d b/gas/testsuite/gas/aarch64/subp.d
> new file mode 100644
> index 00000000000..7eeed244587
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/subp.d
> @@ -0,0 +1,24 @@
> +#as: -march=armv8-a+sve2p3
> +#objdump: -dr
> +
> +.*: file format .*
> +
> +Disassembly of section \.text:
> +
> +0+ <\.text>:
> + *[0-9a-f]+:[ \t]+4410a000[ \t]+subp[ \t]+z0\.b, p0/m, z0\.b, z0\.b
> + *[0-9a-f]+:[ \t]+4410a01f[ \t]+subp[ \t]+z31\.b, p0/m, z31\.b, z0\.b
> + *[0-9a-f]+:[ \t]+4410a3e0[ \t]+subp[ \t]+z0\.b, p0/m, z0\.b, z31\.b
> + *[0-9a-f]+:[ \t]+4410bc00[ \t]+subp[ \t]+z0\.b, p7/m, z0\.b, z0\.b
> + *[0-9a-f]+:[ \t]+4450a000[ \t]+subp[ \t]+z0\.h, p0/m, z0\.h, z0\.h
> + *[0-9a-f]+:[ \t]+4450a01f[ \t]+subp[ \t]+z31\.h, p0/m, z31\.h, z0\.h
> + *[0-9a-f]+:[ \t]+4450a3e0[ \t]+subp[ \t]+z0\.h, p0/m, z0\.h, z31\.h
> + *[0-9a-f]+:[ \t]+4450bc00[ \t]+subp[ \t]+z0\.h, p7/m, z0\.h, z0\.h
> + *[0-9a-f]+:[ \t]+4490a000[ \t]+subp[ \t]+z0\.s, p0/m, z0\.s, z0\.s
> + *[0-9a-f]+:[ \t]+4490a01f[ \t]+subp[ \t]+z31\.s, p0/m, z31\.s, z0\.s
> + *[0-9a-f]+:[ \t]+4490a3e0[ \t]+subp[ \t]+z0\.s, p0/m, z0\.s, z31\.s
> + *[0-9a-f]+:[ \t]+4490bc00[ \t]+subp[ \t]+z0\.s, p7/m, z0\.s, z0\.s
> + *[0-9a-f]+:[ \t]+44d0a000[ \t]+subp[ \t]+z0\.d, p0/m, z0\.d, z0\.d
> + *[0-9a-f]+:[ \t]+44d0a01f[ \t]+subp[ \t]+z31\.d, p0/m, z31\.d, z0\.d
> + *[0-9a-f]+:[ \t]+44d0a3e0[ \t]+subp[ \t]+z0\.d, p0/m, z0\.d, z31\.d
> + *[0-9a-f]+:[ \t]+44d0bc00[ \t]+subp[ \t]+z0\.d, p7/m, z0\.d, z0\.d
> diff --git a/gas/testsuite/gas/aarch64/subp.s b/gas/testsuite/gas/aarch64/subp.s
> new file mode 100644
> index 00000000000..4b319508229
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/subp.s
> @@ -0,0 +1,16 @@
> +subp z0.b, p0/m, z0.b, z0.b
> +subp z31.b, p0/m, z31.b, z0.b
> +subp z0.b, p0/m, z0.b, z31.b
> +subp z0.b, p7/m, z0.b, z0.b
> +subp z0.h, p0/m, z0.h, z0.h
> +subp z31.h, p0/m, z31.h, z0.h
> +subp z0.h, p0/m, z0.h, z31.h
> +subp z0.h, p7/m, z0.h, z0.h
> +subp z0.s, p0/m, z0.s, z0.s
> +subp z31.s, p0/m, z31.s, z0.s
> +subp z0.s, p0/m, z0.s, z31.s
> +subp z0.s, p7/m, z0.s, z0.s
> +subp z0.d, p0/m, z0.d, z0.d
> +subp z31.d, p0/m, z31.d, z0.d
> +subp z0.d, p0/m, z0.d, z31.d
> +subp z0.d, p7/m, z0.d, z0.d
> diff --git a/gas/testsuite/gas/aarch64/sve-invalid.l b/gas/testsuite/gas/aarch64/sve-invalid.l
> index 6b5f38f3d0f..1e54e43d14b 100644
> --- a/gas/testsuite/gas/aarch64/sve-invalid.l
> +++ b/gas/testsuite/gas/aarch64/sve-invalid.l
> @@ -1150,9 +1150,7 @@
> .*: Error: invalid addressing mode at operand 3 -- `ld1rqd {z0\.d},p0/z,\[x0,x1,lsl ?#2\]'
> .*: Error: operand mismatch -- `sdot z0\.b,z1\.b,z2\.b'
> .*: Info: did you mean this\?
> -.*: Info: sdot z0\.s, z1\.b, z2\.b
> -.*: Info: other valid variant\(s\):
> -.*: Info: sdot z0\.d, z1\.h, z2\.h
> +.*: Info: sdot z0\.h, z1\.b, z2\.b
> .*: Error: operand mismatch -- `sdot z0\.h,z1\.h,z2\.h'
> .*: Info: did you mean this\?
> .*: Info: sdot z0\.s, z1\.h, z2\.h
> @@ -1178,9 +1176,7 @@
> .*: Info: sdot z0\.d, z1\.h, z2\.h\[0\]
> .*: Error: operand mismatch -- `udot z0\.b,z1\.b,z2\.b'
> .*: Info: did you mean this\?
> -.*: Info: udot z0\.s, z1\.b, z2\.b
> -.*: Info: other valid variant\(s\):
> -.*: Info: udot z0\.d, z1\.h, z2\.h
> +.*: Info: udot z0\.h, z1\.b, z2\.b
> .*: Error: operand mismatch -- `udot z0\.h,z1\.h,z2\.h'
> .*: Info: did you mean this\?
> .*: Info: udot z0\.s, z1\.h, z2\.h
> diff --git a/gas/testsuite/gas/aarch64/sve2-sme2-6-invalid.l b/gas/testsuite/gas/aarch64/sve2-sme2-6-invalid.l
> index 7792afa90ea..1b79ca8211f 100644
> --- a/gas/testsuite/gas/aarch64/sve2-sme2-6-invalid.l
> +++ b/gas/testsuite/gas/aarch64/sve2-sme2-6-invalid.l
> @@ -7,14 +7,10 @@
> [^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `sqrshrn z0\.h,{ ?z0\.s ?- ?z1\.s ?},#0'
> [^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `sqrshrn z0\.h,{ ?z0\.s ?- ?z1\.s ?},#17'
> [^ :]+:[0-9]+: Error: immediate operand required at operand 3 -- `sqrshrn z0\.h,{ ?z0\.s ?- ?z1\.s ?},x0'
> -[^ :]+:[0-9]+: Error: operand mismatch -- `sqrshrn z0\.b,{ ?z0\.h ?- ?z1\.h ?},#1'
> -[^ :]+:[0-9]+: Info: did you mean this\?
> -[^ :]+:[0-9]+: Info: sqrshrn z0\.b, {z0\.s-z1\.s}, #1
> -[^ :]+:[0-9]+: Info: other valid variant\(s\):
> -[^ :]+:[0-9]+: Info: sqrshrn z0\.h, {z0\.d-z1\.d}, #1
> -[^ :]+:[0-9]+: Error: operand mismatch -- `sqrshrn z0\.s,{ ?z0\.d ?- ?z1\.d ?},#1'
> -[^ :]+:[0-9]+: Info: did you mean this\?
> -[^ :]+:[0-9]+: Info: sqrshrn z0\.h, {z0\.d-z1\.d}, #1
> -[^ :]+:[0-9]+: Info: other valid variant\(s\):
> -[^ :]+:[0-9]+: Info: sqrshrn z0\.b, {z0\.s-z1\.s}, #1
> +[^ :]+:[0-9]+: Error: selected processor does not support `sqrshrn z0\.b,{ ?z0\.h ?- ?z1\.h ?},#1'
> +[^ :]+:[0-9]+: Error: operand mismatch -- `sqrshrn z0\.s,{ ?z0\.d- ?z1\.d},#1'
> +[^ :]+:[0-9]+: Info:\s+did you mean this\?
> +[^ :]+:[0-9]+: Info:\s+sqrshrn z0\.h, { ?z0\.d- ?z1\.d}, #1
> +[^ :]+:[0-9]+: Info:\s+other valid variant\(s\):
> +[^ :]+:[0-9]+: Info:\s+sqrshrn z0\.b, { ?z0\.s ?- ?z1\.s ?}, #1
Can you retain the literal whitespace please?
Incidentally, this incomplete list of valid variants is a longstanding issue
that I intend to fix at some point.
> [^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `sqrshrn z0\.h,{ ?z2\.s ?- ?z3\.s ?},#1'
> diff --git a/gas/testsuite/gas/aarch64/uabal.d b/gas/testsuite/gas/aarch64/uabal.d
> new file mode 100644
> index 00000000000..2f1fa98cacd
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/uabal.d
> @@ -0,0 +1,20 @@
> +#as: -march=armv8-a+sve2p3
> +#objdump: -dr
> +
> +.*: file format .*
> +
> +Disassembly of section \.text:
> +
> +0+ <\.text>:
> + *[0-9a-f]+:[ \t]+4440dc00[ \t]+uabal[ \t]+z0\.h,[ \t]+z0\.b,[ \t]+z0\.b
> + *[0-9a-f]+:[ \t]+4440dc1f[ \t]+uabal[ \t]+z31\.h,[ \t]+z0\.b,[ \t]+z0\.b
> + *[0-9a-f]+:[ \t]+4440dfe0[ \t]+uabal[ \t]+z0\.h,[ \t]+z31\.b,[ \t]+z0\.b
> + *[0-9a-f]+:[ \t]+445fdc00[ \t]+uabal[ \t]+z0\.h,[ \t]+z0\.b,[ \t]+z31\.b
> + *[0-9a-f]+:[ \t]+4480dc00[ \t]+uabal[ \t]+z0\.s,[ \t]+z0\.h,[ \t]+z0\.h
> + *[0-9a-f]+:[ \t]+4480dc1f[ \t]+uabal[ \t]+z31\.s,[ \t]+z0\.h,[ \t]+z0\.h
> + *[0-9a-f]+:[ \t]+4480dfe0[ \t]+uabal[ \t]+z0\.s,[ \t]+z31\.h,[ \t]+z0\.h
> + *[0-9a-f]+:[ \t]+449fdc00[ \t]+uabal[ \t]+z0\.s,[ \t]+z0\.h,[ \t]+z31\.h
> + *[0-9a-f]+:[ \t]+44c0dc00[ \t]+uabal[ \t]+z0\.d,[ \t]+z0\.s,[ \t]+z0\.s
> + *[0-9a-f]+:[ \t]+44c0dc1f[ \t]+uabal[ \t]+z31\.d,[ \t]+z0\.s,[ \t]+z0\.s
> + *[0-9a-f]+:[ \t]+44c0dfe0[ \t]+uabal[ \t]+z0\.d,[ \t]+z31\.s,[ \t]+z0\.s
> + *[0-9a-f]+:[ \t]+44dfdc00[ \t]+uabal[ \t]+z0\.d,[ \t]+z0\.s,[ \t]+z31\.s
> diff --git a/gas/testsuite/gas/aarch64/uabal.s b/gas/testsuite/gas/aarch64/uabal.s
> new file mode 100644
> index 00000000000..c077504b04f
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/uabal.s
> @@ -0,0 +1,12 @@
> +uabal z0.h, z0.b, z0.b
> +uabal z31.h, z0.b, z0.b
> +uabal z0.h, z31.b, z0.b
> +uabal z0.h, z0.b, z31.b
> +uabal z0.s, z0.h, z0.h
> +uabal z31.s, z0.h, z0.h
> +uabal z0.s, z31.h, z0.h
> +uabal z0.s, z0.h, z31.h
> +uabal z0.d, z0.s, z0.s
> +uabal z31.d, z0.s, z0.s
> +uabal z0.d, z31.s, z0.s
> +uabal z0.d, z0.s, z31.s
> diff --git a/gas/testsuite/gas/aarch64/ucvtf.d b/gas/testsuite/gas/aarch64/ucvtf.d
> new file mode 100644
> index 00000000000..f6d681b80e3
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/ucvtf.d
> @@ -0,0 +1,17 @@
> +#as: -march=armv8-a+sve2p3
> +#objdump: -dr
> +
> +.*: file format .*
> +
> +Disassembly of section \.text:
> +
> +0+ <\.text>:
> + *[0-9a-f]+:[ \t]+654c3400[ \t]+ucvtf[ \t]+z0.h,[ \t]+z0.b
> + *[0-9a-f]+:[ \t]+654c341f[ \t]+ucvtf[ \t]+z31.h,[ \t]+z0.b
> + *[0-9a-f]+:[ \t]+654c37e0[ \t]+ucvtf[ \t]+z0.h,[ \t]+z31.b
> + *[0-9a-f]+:[ \t]+658c3400[ \t]+ucvtf[ \t]+z0.s,[ \t]+z0.h
> + *[0-9a-f]+:[ \t]+658c341f[ \t]+ucvtf[ \t]+z31.s,[ \t]+z0.h
> + *[0-9a-f]+:[ \t]+658c37e0[ \t]+ucvtf[ \t]+z0.s,[ \t]+z31.h
> + *[0-9a-f]+:[ \t]+65cc3400[ \t]+ucvtf[ \t]+z0.d,[ \t]+z0.s
> + *[0-9a-f]+:[ \t]+65cc341f[ \t]+ucvtf[ \t]+z31.d,[ \t]+z0.s
> + *[0-9a-f]+:[ \t]+65cc37e0[ \t]+ucvtf[ \t]+z0.d,[ \t]+z31.s
> diff --git a/gas/testsuite/gas/aarch64/ucvtf.s b/gas/testsuite/gas/aarch64/ucvtf.s
> new file mode 100644
> index 00000000000..c77a495d18f
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/ucvtf.s
> @@ -0,0 +1,9 @@
> +ucvtf z0.h, z0.b
> +ucvtf z31.h, z0.b
> +ucvtf z0.h, z31.b
> +ucvtf z0.s, z0.h
> +ucvtf z31.s, z0.h
> +ucvtf z0.s, z31.h
> +ucvtf z0.d, z0.s
> +ucvtf z31.d, z0.s
> +ucvtf z0.d, z31.s
> diff --git a/gas/testsuite/gas/aarch64/ucvtflt.d b/gas/testsuite/gas/aarch64/ucvtflt.d
> new file mode 100644
> index 00000000000..4c7a5cdb806
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/ucvtflt.d
> @@ -0,0 +1,17 @@
> +#as: -march=armv8-a+sve2p3
> +#objdump: -dr
> +
> +.*: file format .*
> +
> +Disassembly of section \.text:
> +
> +0+ <\.text>:
> + *[0-9a-f]+:[ \t]+654c3c00[ \t]+ucvtflt[ \t]+z0.h,[ \t]+z0.b
> + *[0-9a-f]+:[ \t]+654c3c1f[ \t]+ucvtflt[ \t]+z31.h,[ \t]+z0.b
> + *[0-9a-f]+:[ \t]+654c3fe0[ \t]+ucvtflt[ \t]+z0.h,[ \t]+z31.b
> + *[0-9a-f]+:[ \t]+658c3c00[ \t]+ucvtflt[ \t]+z0.s,[ \t]+z0.h
> + *[0-9a-f]+:[ \t]+658c3c1f[ \t]+ucvtflt[ \t]+z31.s,[ \t]+z0.h
> + *[0-9a-f]+:[ \t]+658c3fe0[ \t]+ucvtflt[ \t]+z0.s,[ \t]+z31.h
> + *[0-9a-f]+:[ \t]+65cc3c00[ \t]+ucvtflt[ \t]+z0.d,[ \t]+z0.s
> + *[0-9a-f]+:[ \t]+65cc3c1f[ \t]+ucvtflt[ \t]+z31.d,[ \t]+z0.s
> + *[0-9a-f]+:[ \t]+65cc3fe0[ \t]+ucvtflt[ \t]+z0.d,[ \t]+z31.s
> diff --git a/gas/testsuite/gas/aarch64/ucvtflt.s b/gas/testsuite/gas/aarch64/ucvtflt.s
> new file mode 100644
> index 00000000000..e67d7df7de2
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/ucvtflt.s
> @@ -0,0 +1,9 @@
> +ucvtflt z0.h, z0.b
> +ucvtflt z31.h, z0.b
> +ucvtflt z0.h, z31.b
> +ucvtflt z0.s, z0.h
> +ucvtflt z31.s, z0.h
> +ucvtflt z0.s, z31.h
> +ucvtflt z0.d, z0.s
> +ucvtflt z31.d, z0.s
> +ucvtflt z0.d, z31.s
> diff --git a/gas/testsuite/gas/aarch64/udot.d b/gas/testsuite/gas/aarch64/udot.d
> new file mode 100644
> index 00000000000..29474cf8140
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/udot.d
> @@ -0,0 +1,64 @@
> +#as: -march=armv8-a+sve2p3
> +#objdump: -dr
> +
> +.*: file format .*
> +
> +Disassembly of section \.text:
> +
> +0+ <\.text>:
> + *[0-9a-f]+:[ \t]+44400400[ \t]+udot[ \t]+z0\.h, z0\.b, z0\.b
> + *[0-9a-f]+:[ \t]+4440041f[ \t]+udot[ \t]+z31\.h, z0\.b, z0\.b
> + *[0-9a-f]+:[ \t]+444007e0[ \t]+udot[ \t]+z0\.h, z31\.b, z0\.b
> + *[0-9a-f]+:[ \t]+445f0400[ \t]+udot[ \t]+z0\.h, z0\.b, z31\.b
> + *[0-9a-f]+:[ \t]+4400cc00[ \t]+udot[ \t]+z0\.s, z0.h, z0\.h
> + *[0-9a-f]+:[ \t]+4400cc1f[ \t]+udot[ \t]+z31\.s, z0.h, z0\.h
> + *[0-9a-f]+:[ \t]+4400cfe0[ \t]+udot[ \t]+z0\.s, z31.h, z0\.h
> + *[0-9a-f]+:[ \t]+441fcc00[ \t]+udot[ \t]+z0\.s, z0.h, z31\.h
> + *[0-9a-f]+:[ \t]+44200400[ \t]+udot[ \t]+z0\.h, z0\.b, z0\.b\[0\]
> + *[0-9a-f]+:[ \t]+4420041f[ \t]+udot[ \t]+z31\.h, z0\.b, z0\.b\[0\]
> + *[0-9a-f]+:[ \t]+442007e0[ \t]+udot[ \t]+z0\.h, z31\.b, z0\.b\[0\]
> + *[0-9a-f]+:[ \t]+44270400[ \t]+udot[ \t]+z0\.h, z0\.b, z7\.b\[0\]
> + *[0-9a-f]+:[ \t]+44280400[ \t]+udot[ \t]+z0\.h, z0\.b, z0\.b\[1\]
> + *[0-9a-f]+:[ \t]+4428041f[ \t]+udot[ \t]+z31\.h, z0\.b, z0\.b\[1\]
> + *[0-9a-f]+:[ \t]+442807e0[ \t]+udot[ \t]+z0\.h, z31\.b, z0\.b\[1\]
> + *[0-9a-f]+:[ \t]+442f0400[ \t]+udot[ \t]+z0\.h, z0\.b, z7\.b\[1\]
> + *[0-9a-f]+:[ \t]+44300400[ \t]+udot[ \t]+z0\.h, z0\.b, z0\.b\[2\]
> + *[0-9a-f]+:[ \t]+4430041f[ \t]+udot[ \t]+z31\.h, z0\.b, z0\.b\[2\]
> + *[0-9a-f]+:[ \t]+443007e0[ \t]+udot[ \t]+z0\.h, z31\.b, z0\.b\[2\]
> + *[0-9a-f]+:[ \t]+44370400[ \t]+udot[ \t]+z0\.h, z0\.b, z7\.b\[2\]
> + *[0-9a-f]+:[ \t]+44380400[ \t]+udot[ \t]+z0\.h, z0\.b, z0\.b\[3\]
> + *[0-9a-f]+:[ \t]+4438041f[ \t]+udot[ \t]+z31\.h, z0\.b, z0\.b\[3\]
> + *[0-9a-f]+:[ \t]+443807e0[ \t]+udot[ \t]+z0\.h, z31\.b, z0\.b\[3\]
> + *[0-9a-f]+:[ \t]+443f0400[ \t]+udot[ \t]+z0\.h, z0\.b, z7\.b\[3\]
> + *[0-9a-f]+:[ \t]+44600400[ \t]+udot[ \t]+z0\.h, z0\.b, z0\.b\[4\]
> + *[0-9a-f]+:[ \t]+4460041f[ \t]+udot[ \t]+z31\.h, z0\.b, z0\.b\[4\]
> + *[0-9a-f]+:[ \t]+446007e0[ \t]+udot[ \t]+z0\.h, z31\.b, z0\.b\[4\]
> + *[0-9a-f]+:[ \t]+44670400[ \t]+udot[ \t]+z0\.h, z0\.b, z7\.b\[4\]
> + *[0-9a-f]+:[ \t]+44680400[ \t]+udot[ \t]+z0\.h, z0\.b, z0\.b\[5\]
> + *[0-9a-f]+:[ \t]+4468041f[ \t]+udot[ \t]+z31\.h, z0\.b, z0\.b\[5\]
> + *[0-9a-f]+:[ \t]+446807e0[ \t]+udot[ \t]+z0\.h, z31\.b, z0\.b\[5\]
> + *[0-9a-f]+:[ \t]+446f0400[ \t]+udot[ \t]+z0\.h, z0\.b, z7\.b\[5\]
> + *[0-9a-f]+:[ \t]+44700400[ \t]+udot[ \t]+z0\.h, z0\.b, z0\.b\[6\]
> + *[0-9a-f]+:[ \t]+4470041f[ \t]+udot[ \t]+z31\.h, z0\.b, z0\.b\[6\]
> + *[0-9a-f]+:[ \t]+447007e0[ \t]+udot[ \t]+z0\.h, z31\.b, z0\.b\[6\]
> + *[0-9a-f]+:[ \t]+44770400[ \t]+udot[ \t]+z0\.h, z0\.b, z7\.b\[6\]
> + *[0-9a-f]+:[ \t]+44780400[ \t]+udot[ \t]+z0\.h, z0\.b, z0\.b\[7\]
> + *[0-9a-f]+:[ \t]+4478041f[ \t]+udot[ \t]+z31\.h, z0\.b, z0\.b\[7\]
> + *[0-9a-f]+:[ \t]+447807e0[ \t]+udot[ \t]+z0\.h, z31\.b, z0\.b\[7\]
> + *[0-9a-f]+:[ \t]+447f0400[ \t]+udot[ \t]+z0\.h, z0\.b, z7\.b\[7\]
> + *[0-9a-f]+:[ \t]+4480cc00[ \t]+udot[ \t]+z0\.s, z0\.h, z0\.h\[0\]
> + *[0-9a-f]+:[ \t]+4480cc1f[ \t]+udot[ \t]+z31\.s, z0\.h, z0\.h\[0\]
> + *[0-9a-f]+:[ \t]+4480cfe0[ \t]+udot[ \t]+z0\.s, z31\.h, z0\.h\[0\]
> + *[0-9a-f]+:[ \t]+4487cc00[ \t]+udot[ \t]+z0\.s, z0\.h, z7\.h\[0\]
> + *[0-9a-f]+:[ \t]+4488cc00[ \t]+udot[ \t]+z0\.s, z0\.h, z0\.h\[1\]
> + *[0-9a-f]+:[ \t]+4488cc1f[ \t]+udot[ \t]+z31\.s, z0\.h, z0\.h\[1\]
> + *[0-9a-f]+:[ \t]+4488cfe0[ \t]+udot[ \t]+z0\.s, z31\.h, z0\.h\[1\]
> + *[0-9a-f]+:[ \t]+448fcc00[ \t]+udot[ \t]+z0\.s, z0\.h, z7\.h\[1\]
> + *[0-9a-f]+:[ \t]+4490cc00[ \t]+udot[ \t]+z0\.s, z0\.h, z0\.h\[2\]
> + *[0-9a-f]+:[ \t]+4490cc1f[ \t]+udot[ \t]+z31\.s, z0\.h, z0\.h\[2\]
> + *[0-9a-f]+:[ \t]+4490cfe0[ \t]+udot[ \t]+z0\.s, z31\.h, z0\.h\[2\]
> + *[0-9a-f]+:[ \t]+4497cc00[ \t]+udot[ \t]+z0\.s, z0\.h, z7\.h\[2\]
> + *[0-9a-f]+:[ \t]+4498cc00[ \t]+udot[ \t]+z0\.s, z0\.h, z0\.h\[3\]
> + *[0-9a-f]+:[ \t]+4498cc1f[ \t]+udot[ \t]+z31\.s, z0\.h, z0\.h\[3\]
> + *[0-9a-f]+:[ \t]+4498cfe0[ \t]+udot[ \t]+z0\.s, z31\.h, z0\.h\[3\]
> + *[0-9a-f]+:[ \t]+449fcc00[ \t]+udot[ \t]+z0\.s, z0\.h, z7\.h\[3\]
> diff --git a/gas/testsuite/gas/aarch64/udot.s b/gas/testsuite/gas/aarch64/udot.s
> new file mode 100644
> index 00000000000..2de370b4269
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/udot.s
> @@ -0,0 +1,56 @@
> +udot z0.h, z0.b, z0.b
> +udot z31.h, z0.b, z0.b
> +udot z0.h, z31.b, z0.b
> +udot z0.h, z0.b, z31.b
> +udot z0.s, z0.h, z0.h
> +udot z31.s, z0.h, z0.h
> +udot z0.s, z31.h, z0.h
> +udot z0.s, z0.h, z31.h
> +udot z0.h, z0.b, z0.b[0]
> +udot z31.h, z0.b, z0.b[0]
> +udot z0.h, z31.b, z0.b[0]
> +udot z0.h, z0.b, z7.b[0]
> +udot z0.h, z0.b, z0.b[1]
> +udot z31.h, z0.b, z0.b[1]
> +udot z0.h, z31.b, z0.b[1]
> +udot z0.h, z0.b, z7.b[1]
> +udot z0.h, z0.b, z0.b[2]
> +udot z31.h, z0.b, z0.b[2]
> +udot z0.h, z31.b, z0.b[2]
> +udot z0.h, z0.b, z7.b[2]
> +udot z0.h, z0.b, z0.b[3]
> +udot z31.h, z0.b, z0.b[3]
> +udot z0.h, z31.b, z0.b[3]
> +udot z0.h, z0.b, z7.b[3]
> +udot z0.h, z0.b, z0.b[4]
> +udot z31.h, z0.b, z0.b[4]
> +udot z0.h, z31.b, z0.b[4]
> +udot z0.h, z0.b, z7.b[4]
> +udot z0.h, z0.b, z0.b[5]
> +udot z31.h, z0.b, z0.b[5]
> +udot z0.h, z31.b, z0.b[5]
> +udot z0.h, z0.b, z7.b[5]
> +udot z0.h, z0.b, z0.b[6]
> +udot z31.h, z0.b, z0.b[6]
> +udot z0.h, z31.b, z0.b[6]
> +udot z0.h, z0.b, z7.b[6]
> +udot z0.h, z0.b, z0.b[7]
> +udot z31.h, z0.b, z0.b[7]
> +udot z0.h, z31.b, z0.b[7]
> +udot z0.h, z0.b, z7.b[7]
> +udot z0.s, z0.h, z0.h[0]
> +udot z31.s, z0.h, z0.h[0]
> +udot z0.s, z31.h, z0.h[0]
> +udot z0.s, z0.h, z7.h[0]
> +udot z0.s, z0.h, z0.h[1]
> +udot z31.s, z0.h, z0.h[1]
> +udot z0.s, z31.h, z0.h[1]
> +udot z0.s, z0.h, z7.h[1]
> +udot z0.s, z0.h, z0.h[2]
> +udot z31.s, z0.h, z0.h[2]
> +udot z0.s, z31.h, z0.h[2]
> +udot z0.s, z0.h, z7.h[2]
> +udot z0.s, z0.h, z0.h[3]
> +udot z31.s, z0.h, z0.h[3]
> +udot z0.s, z31.h, z0.h[3]
> +udot z0.s, z0.h, z7.h[3]
> diff --git a/gas/testsuite/gas/aarch64/uqrshrn_imm.d b/gas/testsuite/gas/aarch64/uqrshrn_imm.d
> new file mode 100644
> index 00000000000..9e8ac180081
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/uqrshrn_imm.d
> @@ -0,0 +1,81 @@
> +#as: -march=armv8-a+sme2p3
> +#objdump: -dr
> +
> +.*: file format .*
> +
> +Disassembly of section \.text:
> +
> +0+ <\.text>:
> + *[0-9a-f]+:[ \t]+45a83800[ \t]+uqrshrn[ \t]+z0\.b,[ \t]{z0\.h-z1\.h},[ \t]+#8
> + *[0-9a-f]+:[ \t]+45a8381f[ \t]+uqrshrn[ \t]+z31\.b,[ \t]{z0\.h-z1\.h},[ \t]+#8
> + *[0-9a-f]+:[ \t]+45a83bc0[ \t]+uqrshrn[ \t]+z0\.b,[ \t]{z30\.h-z31\.h},[ \t]+#8
> + *[0-9a-f]+:[ \t]+45a93800[ \t]+uqrshrn[ \t]+z0\.b,[ \t]{z0\.h-z1\.h},[ \t]+#7
> + *[0-9a-f]+:[ \t]+45a9381f[ \t]+uqrshrn[ \t]+z31\.b,[ \t]{z0\.h-z1\.h},[ \t]+#7
> + *[0-9a-f]+:[ \t]+45a93bc0[ \t]+uqrshrn[ \t]+z0\.b,[ \t]{z30\.h-z31\.h},[ \t]+#7
> + *[0-9a-f]+:[ \t]+45aa3800[ \t]+uqrshrn[ \t]+z0\.b,[ \t]{z0\.h-z1\.h},[ \t]+#6
> + *[0-9a-f]+:[ \t]+45aa381f[ \t]+uqrshrn[ \t]+z31\.b,[ \t]{z0\.h-z1\.h},[ \t]+#6
> + *[0-9a-f]+:[ \t]+45aa3bc0[ \t]+uqrshrn[ \t]+z0\.b,[ \t]{z30\.h-z31\.h},[ \t]+#6
> + *[0-9a-f]+:[ \t]+45ab3800[ \t]+uqrshrn[ \t]+z0\.b,[ \t]{z0\.h-z1\.h},[ \t]+#5
> + *[0-9a-f]+:[ \t]+45ab381f[ \t]+uqrshrn[ \t]+z31\.b,[ \t]{z0\.h-z1\.h},[ \t]+#5
> + *[0-9a-f]+:[ \t]+45ab3bc0[ \t]+uqrshrn[ \t]+z0\.b,[ \t]{z30\.h-z31\.h},[ \t]+#5
> + *[0-9a-f]+:[ \t]+45ac3800[ \t]+uqrshrn[ \t]+z0\.b,[ \t]{z0\.h-z1\.h},[ \t]+#4
> + *[0-9a-f]+:[ \t]+45ac381f[ \t]+uqrshrn[ \t]+z31\.b,[ \t]{z0\.h-z1\.h},[ \t]+#4
> + *[0-9a-f]+:[ \t]+45ac3bc0[ \t]+uqrshrn[ \t]+z0\.b,[ \t]{z30\.h-z31\.h},[ \t]+#4
> + *[0-9a-f]+:[ \t]+45ad3800[ \t]+uqrshrn[ \t]+z0\.b,[ \t]{z0\.h-z1\.h},[ \t]+#3
> + *[0-9a-f]+:[ \t]+45ad381f[ \t]+uqrshrn[ \t]+z31\.b,[ \t]{z0\.h-z1\.h},[ \t]+#3
> + *[0-9a-f]+:[ \t]+45ad3bc0[ \t]+uqrshrn[ \t]+z0\.b,[ \t]{z30\.h-z31\.h},[ \t]+#3
> + *[0-9a-f]+:[ \t]+45ae3800[ \t]+uqrshrn[ \t]+z0\.b,[ \t]{z0\.h-z1\.h},[ \t]+#2
> + *[0-9a-f]+:[ \t]+45ae381f[ \t]+uqrshrn[ \t]+z31\.b,[ \t]{z0\.h-z1\.h},[ \t]+#2
> + *[0-9a-f]+:[ \t]+45ae3bc0[ \t]+uqrshrn[ \t]+z0\.b,[ \t]{z30\.h-z31\.h},[ \t]+#2
> + *[0-9a-f]+:[ \t]+45af3800[ \t]+uqrshrn[ \t]+z0\.b,[ \t]{z0\.h-z1\.h},[ \t]+#1
> + *[0-9a-f]+:[ \t]+45af381f[ \t]+uqrshrn[ \t]+z31\.b,[ \t]{z0\.h-z1\.h},[ \t]+#1
> + *[0-9a-f]+:[ \t]+45af3bc0[ \t]+uqrshrn[ \t]+z0\.b,[ \t]{z30\.h-z31\.h},[ \t]+#1
> +
> + *[0-9a-f]+:[ \t]+45b03800[ \t]+uqrshrn[ \t]+z0\.h,[ \t]{z0.s-z1.s}, #16
> + *[0-9a-f]+:[ \t]+45b0381f[ \t]+uqrshrn[ \t]+z31\.h,[ \t]{z0.s-z1.s}, #16
> + *[0-9a-f]+:[ \t]+45b03bc0[ \t]+uqrshrn[ \t]+z0\.h,[ \t]{z30.s-z31.s}, #16
> + *[0-9a-f]+:[ \t]+45b13800[ \t]+uqrshrn[ \t]+z0\.h,[ \t]{z0.s-z1.s}, #15
> + *[0-9a-f]+:[ \t]+45b1381f[ \t]+uqrshrn[ \t]+z31\.h,[ \t]{z0.s-z1.s}, #15
> + *[0-9a-f]+:[ \t]+45b13bc0[ \t]+uqrshrn[ \t]+z0\.h,[ \t]{z30.s-z31.s}, #15
> + *[0-9a-f]+:[ \t]+45b23800[ \t]+uqrshrn[ \t]+z0\.h,[ \t]{z0.s-z1.s}, #14
> + *[0-9a-f]+:[ \t]+45b2381f[ \t]+uqrshrn[ \t]+z31\.h,[ \t]{z0.s-z1.s}, #14
> + *[0-9a-f]+:[ \t]+45b23bc0[ \t]+uqrshrn[ \t]+z0\.h,[ \t]{z30.s-z31.s}, #14
> + *[0-9a-f]+:[ \t]+45b33800[ \t]+uqrshrn[ \t]+z0\.h,[ \t]{z0.s-z1.s}, #13
> + *[0-9a-f]+:[ \t]+45b3381f[ \t]+uqrshrn[ \t]+z31\.h,[ \t]{z0.s-z1.s}, #13
> + *[0-9a-f]+:[ \t]+45b33bc0[ \t]+uqrshrn[ \t]+z0\.h,[ \t]{z30.s-z31.s}, #13
> + *[0-9a-f]+:[ \t]+45b43800[ \t]+uqrshrn[ \t]+z0\.h,[ \t]{z0.s-z1.s}, #12
> + *[0-9a-f]+:[ \t]+45b4381f[ \t]+uqrshrn[ \t]+z31\.h,[ \t]{z0.s-z1.s}, #12
> + *[0-9a-f]+:[ \t]+45b43bc0[ \t]+uqrshrn[ \t]+z0\.h,[ \t]{z30.s-z31.s}, #12
> + *[0-9a-f]+:[ \t]+45b53800[ \t]+uqrshrn[ \t]+z0\.h,[ \t]{z0.s-z1.s}, #11
> + *[0-9a-f]+:[ \t]+45b5381f[ \t]+uqrshrn[ \t]+z31\.h,[ \t]{z0.s-z1.s}, #11
> + *[0-9a-f]+:[ \t]+45b53bc0[ \t]+uqrshrn[ \t]+z0\.h,[ \t]{z30.s-z31.s}, #11
> + *[0-9a-f]+:[ \t]+45b63800[ \t]+uqrshrn[ \t]+z0\.h,[ \t]{z0.s-z1.s}, #10
> + *[0-9a-f]+:[ \t]+45b6381f[ \t]+uqrshrn[ \t]+z31\.h,[ \t]{z0.s-z1.s}, #10
> + *[0-9a-f]+:[ \t]+45b63bc0[ \t]+uqrshrn[ \t]+z0\.h,[ \t]{z30.s-z31.s}, #10
> + *[0-9a-f]+:[ \t]+45b73800[ \t]+uqrshrn[ \t]+z0\.h,[ \t]{z0.s-z1.s}, #9
> + *[0-9a-f]+:[ \t]+45b7381f[ \t]+uqrshrn[ \t]+z31\.h,[ \t]{z0.s-z1.s}, #9
> + *[0-9a-f]+:[ \t]+45b73bc0[ \t]+uqrshrn[ \t]+z0\.h,[ \t]{z30.s-z31.s}, #9
> + *[0-9a-f]+:[ \t]+45b83800[ \t]+uqrshrn[ \t]+z0\.h,[ \t]{z0.s-z1.s}, #8
> + *[0-9a-f]+:[ \t]+45b8381f[ \t]+uqrshrn[ \t]+z31\.h,[ \t]{z0.s-z1.s}, #8
> + *[0-9a-f]+:[ \t]+45b83bc0[ \t]+uqrshrn[ \t]+z0\.h,[ \t]{z30.s-z31.s}, #8
> + *[0-9a-f]+:[ \t]+45b93800[ \t]+uqrshrn[ \t]+z0\.h,[ \t]{z0.s-z1.s}, #7
> + *[0-9a-f]+:[ \t]+45b9381f[ \t]+uqrshrn[ \t]+z31\.h,[ \t]{z0.s-z1.s}, #7
> + *[0-9a-f]+:[ \t]+45b93bc0[ \t]+uqrshrn[ \t]+z0\.h,[ \t]{z30.s-z31.s}, #7
> + *[0-9a-f]+:[ \t]+45ba3800[ \t]+uqrshrn[ \t]+z0\.h,[ \t]{z0.s-z1.s}, #6
> + *[0-9a-f]+:[ \t]+45ba381f[ \t]+uqrshrn[ \t]+z31\.h,[ \t]{z0.s-z1.s}, #6
> + *[0-9a-f]+:[ \t]+45ba3bc0[ \t]+uqrshrn[ \t]+z0\.h,[ \t]{z30.s-z31.s}, #6
> + *[0-9a-f]+:[ \t]+45bb3800[ \t]+uqrshrn[ \t]+z0\.h,[ \t]{z0.s-z1.s}, #5
> + *[0-9a-f]+:[ \t]+45bb381f[ \t]+uqrshrn[ \t]+z31\.h,[ \t]{z0.s-z1.s}, #5
> + *[0-9a-f]+:[ \t]+45bb3bc0[ \t]+uqrshrn[ \t]+z0\.h,[ \t]{z30.s-z31.s}, #5
> + *[0-9a-f]+:[ \t]+45bc3800[ \t]+uqrshrn[ \t]+z0\.h,[ \t]{z0.s-z1.s}, #4
> + *[0-9a-f]+:[ \t]+45bc381f[ \t]+uqrshrn[ \t]+z31\.h,[ \t]{z0.s-z1.s}, #4
> + *[0-9a-f]+:[ \t]+45bc3bc0[ \t]+uqrshrn[ \t]+z0\.h,[ \t]{z30.s-z31.s}, #4
> + *[0-9a-f]+:[ \t]+45bd3800[ \t]+uqrshrn[ \t]+z0\.h,[ \t]{z0.s-z1.s}, #3
> + *[0-9a-f]+:[ \t]+45bd381f[ \t]+uqrshrn[ \t]+z31\.h,[ \t]{z0.s-z1.s}, #3
> + *[0-9a-f]+:[ \t]+45bd3bc0[ \t]+uqrshrn[ \t]+z0\.h,[ \t]{z30.s-z31.s}, #3
> + *[0-9a-f]+:[ \t]+45be3800[ \t]+uqrshrn[ \t]+z0\.h,[ \t]{z0.s-z1.s}, #2
> + *[0-9a-f]+:[ \t]+45be381f[ \t]+uqrshrn[ \t]+z31\.h,[ \t]{z0.s-z1.s}, #2
> + *[0-9a-f]+:[ \t]+45be3bc0[ \t]+uqrshrn[ \t]+z0\.h,[ \t]{z30.s-z31.s}, #2
> + *[0-9a-f]+:[ \t]+45bf3800[ \t]+uqrshrn[ \t]+z0\.h,[ \t]{z0.s-z1.s}, #1
> + *[0-9a-f]+:[ \t]+45bf381f[ \t]+uqrshrn[ \t]+z31\.h,[ \t]{z0.s-z1.s}, #1
> + *[0-9a-f]+:[ \t]+45bf3bc0[ \t]+uqrshrn[ \t]+z0\.h,[ \t]{z30.s-z31.s}, #1
> diff --git a/gas/testsuite/gas/aarch64/uqrshrn_imm.s b/gas/testsuite/gas/aarch64/uqrshrn_imm.s
> new file mode 100644
> index 00000000000..1d2ff5a7d78
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/uqrshrn_imm.s
> @@ -0,0 +1,73 @@
> +uqrshrn z0.b, { z0.h-z1.h }, #8
> +uqrshrn z31.b, { z0.h-z1.h }, #8
> +uqrshrn z0.b, { z30.h-z31.h }, #8
> +uqrshrn z0.b, { z0.h-z1.h }, #7
> +uqrshrn z31.b, { z0.h-z1.h }, #7
> +uqrshrn z0.b, { z30.h-z31.h }, #7
> +uqrshrn z0.b, { z0.h-z1.h }, #6
> +uqrshrn z31.b, { z0.h-z1.h }, #6
> +uqrshrn z0.b, { z30.h-z31.h }, #6
> +uqrshrn z0.b, { z0.h-z1.h }, #5
> +uqrshrn z31.b, { z0.h-z1.h }, #5
> +uqrshrn z0.b, { z30.h-z31.h }, #5
> +uqrshrn z0.b, { z0.h-z1.h }, #4
> +uqrshrn z31.b, { z0.h-z1.h }, #4
> +uqrshrn z0.b, { z30.h-z31.h }, #4
> +uqrshrn z0.b, { z0.h-z1.h }, #3
> +uqrshrn z31.b, { z0.h-z1.h }, #3
> +uqrshrn z0.b, { z30.h-z31.h }, #3
> +uqrshrn z0.b, { z0.h-z1.h }, #2
> +uqrshrn z31.b, { z0.h-z1.h }, #2
> +uqrshrn z0.b, { z30.h-z31.h }, #2
> +uqrshrn z0.b, { z0.h-z1.h }, #1
> +uqrshrn z31.b, { z0.h-z1.h }, #1
> +uqrshrn z0.b, { z30.h-z31.h }, #1
> +
> +uqrshrn z0.h, { z0.s-z1.s }, #16
> +uqrshrn z31.h, { z0.s-z1.s }, #16
> +uqrshrn z0.h, { z30.s-z31.s }, #16
> +uqrshrn z0.h, { z0.s-z1.s }, #15
> +uqrshrn z31.h, { z0.s-z1.s }, #15
> +uqrshrn z0.h, { z30.s-z31.s }, #15
> +uqrshrn z0.h, { z0.s-z1.s }, #14
> +uqrshrn z31.h, { z0.s-z1.s }, #14
> +uqrshrn z0.h, { z30.s-z31.s }, #14
> +uqrshrn z0.h, { z0.s-z1.s }, #13
> +uqrshrn z31.h, { z0.s-z1.s }, #13
> +uqrshrn z0.h, { z30.s-z31.s }, #13
> +uqrshrn z0.h, { z0.s-z1.s }, #12
> +uqrshrn z31.h, { z0.s-z1.s }, #12
> +uqrshrn z0.h, { z30.s-z31.s }, #12
> +uqrshrn z0.h, { z0.s-z1.s }, #11
> +uqrshrn z31.h, { z0.s-z1.s }, #11
> +uqrshrn z0.h, { z30.s-z31.s }, #11
> +uqrshrn z0.h, { z0.s-z1.s }, #10
> +uqrshrn z31.h, { z0.s-z1.s }, #10
> +uqrshrn z0.h, { z30.s-z31.s }, #10
> +uqrshrn z0.h, { z0.s-z1.s }, #9
> +uqrshrn z31.h, { z0.s-z1.s }, #9
> +uqrshrn z0.h, { z30.s-z31.s }, #9
> +uqrshrn z0.h, { z0.s-z1.s }, #8
> +uqrshrn z31.h, { z0.s-z1.s }, #8
> +uqrshrn z0.h, { z30.s-z31.s }, #8
> +uqrshrn z0.h, { z0.s-z1.s }, #7
> +uqrshrn z31.h, { z0.s-z1.s }, #7
> +uqrshrn z0.h, { z30.s-z31.s }, #7
> +uqrshrn z0.h, { z0.s-z1.s }, #6
> +uqrshrn z31.h, { z0.s-z1.s }, #6
> +uqrshrn z0.h, { z30.s-z31.s }, #6
> +uqrshrn z0.h, { z0.s-z1.s }, #5
> +uqrshrn z31.h, { z0.s-z1.s }, #5
> +uqrshrn z0.h, { z30.s-z31.s }, #5
> +uqrshrn z0.h, { z0.s-z1.s }, #4
> +uqrshrn z31.h, { z0.s-z1.s }, #4
> +uqrshrn z0.h, { z30.s-z31.s }, #4
> +uqrshrn z0.h, { z0.s-z1.s }, #3
> +uqrshrn z31.h, { z0.s-z1.s }, #3
> +uqrshrn z0.h, { z30.s-z31.s }, #3
> +uqrshrn z0.h, { z0.s-z1.s }, #2
> +uqrshrn z31.h, { z0.s-z1.s }, #2
> +uqrshrn z0.h, { z30.s-z31.s }, #2
> +uqrshrn z0.h, { z0.s-z1.s }, #1
> +uqrshrn z31.h, { z0.s-z1.s }, #1
> +uqrshrn z0.h, { z30.s-z31.h }, #1
> diff --git a/gas/testsuite/gas/aarch64/uqshrn_imm.d b/gas/testsuite/gas/aarch64/uqshrn_imm.d
> new file mode 100644
> index 00000000000..3b3e0dc3577
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/uqshrn_imm.d
> @@ -0,0 +1,81 @@
> +#as: -march=armv8-a+sme2p3
> +#objdump: -dr
> +
> +.*: file format .*
> +
> +Disassembly of section \.text:
> +
> +0+ <\.text>:
> + *[0-9a-f]+:[ \t]+45a81000[ \t]+uqshrn[ \t]+z0\.b,[ \t]{z0\.h-z1\.h},[ \t]+#8
> + *[0-9a-f]+:[ \t]+45a8101f[ \t]+uqshrn[ \t]+z31\.b,[ \t]{z0\.h-z1\.h},[ \t]+#8
> + *[0-9a-f]+:[ \t]+45a813c0[ \t]+uqshrn[ \t]+z0\.b,[ \t]{z30\.h-z31\.h},[ \t]+#8
> + *[0-9a-f]+:[ \t]+45a91000[ \t]+uqshrn[ \t]+z0\.b,[ \t]{z0\.h-z1\.h},[ \t]+#7
> + *[0-9a-f]+:[ \t]+45a9101f[ \t]+uqshrn[ \t]+z31\.b,[ \t]{z0\.h-z1\.h},[ \t]+#7
> + *[0-9a-f]+:[ \t]+45a913c0[ \t]+uqshrn[ \t]+z0\.b,[ \t]{z30\.h-z31\.h},[ \t]+#7
> + *[0-9a-f]+:[ \t]+45aa1000[ \t]+uqshrn[ \t]+z0\.b,[ \t]{z0\.h-z1\.h},[ \t]+#6
> + *[0-9a-f]+:[ \t]+45aa101f[ \t]+uqshrn[ \t]+z31\.b,[ \t]{z0\.h-z1\.h},[ \t]+#6
> + *[0-9a-f]+:[ \t]+45aa13c0[ \t]+uqshrn[ \t]+z0\.b,[ \t]{z30\.h-z31\.h},[ \t]+#6
> + *[0-9a-f]+:[ \t]+45ab1000[ \t]+uqshrn[ \t]+z0\.b,[ \t]{z0\.h-z1\.h},[ \t]+#5
> + *[0-9a-f]+:[ \t]+45ab101f[ \t]+uqshrn[ \t]+z31\.b,[ \t]{z0\.h-z1\.h},[ \t]+#5
> + *[0-9a-f]+:[ \t]+45ab13c0[ \t]+uqshrn[ \t]+z0\.b,[ \t]{z30\.h-z31\.h},[ \t]+#5
> + *[0-9a-f]+:[ \t]+45ac1000[ \t]+uqshrn[ \t]+z0\.b,[ \t]{z0\.h-z1\.h},[ \t]+#4
> + *[0-9a-f]+:[ \t]+45ac101f[ \t]+uqshrn[ \t]+z31\.b,[ \t]{z0\.h-z1\.h},[ \t]+#4
> + *[0-9a-f]+:[ \t]+45ac13c0[ \t]+uqshrn[ \t]+z0\.b,[ \t]{z30\.h-z31\.h},[ \t]+#4
> + *[0-9a-f]+:[ \t]+45ad1000[ \t]+uqshrn[ \t]+z0\.b,[ \t]{z0\.h-z1\.h},[ \t]+#3
> + *[0-9a-f]+:[ \t]+45ad101f[ \t]+uqshrn[ \t]+z31\.b,[ \t]{z0\.h-z1\.h},[ \t]+#3
> + *[0-9a-f]+:[ \t]+45ad13c0[ \t]+uqshrn[ \t]+z0\.b,[ \t]{z30\.h-z31\.h},[ \t]+#3
> + *[0-9a-f]+:[ \t]+45ae1000[ \t]+uqshrn[ \t]+z0\.b,[ \t]{z0\.h-z1\.h},[ \t]+#2
> + *[0-9a-f]+:[ \t]+45ae101f[ \t]+uqshrn[ \t]+z31\.b,[ \t]{z0\.h-z1\.h},[ \t]+#2
> + *[0-9a-f]+:[ \t]+45ae13c0[ \t]+uqshrn[ \t]+z0\.b,[ \t]{z30\.h-z31\.h},[ \t]+#2
> + *[0-9a-f]+:[ \t]+45af1000[ \t]+uqshrn[ \t]+z0\.b,[ \t]{z0\.h-z1\.h},[ \t]+#1
> + *[0-9a-f]+:[ \t]+45af101f[ \t]+uqshrn[ \t]+z31\.b,[ \t]{z0\.h-z1\.h},[ \t]+#1
> + *[0-9a-f]+:[ \t]+45af13c0[ \t]+uqshrn[ \t]+z0\.b,[ \t]{z30\.h-z31\.h},[ \t]+#1
> +
> + *[0-9a-f]+:[ \t]+45b01000[ \t]+uqshrn[ \t]+z0\.h,[ \t]{z0.s-z1.s}, #16
> + *[0-9a-f]+:[ \t]+45b0101f[ \t]+uqshrn[ \t]+z31\.h,[ \t]{z0.s-z1.s}, #16
> + *[0-9a-f]+:[ \t]+45b013c0[ \t]+uqshrn[ \t]+z0\.h,[ \t]{z30.s-z31.s}, #16
> + *[0-9a-f]+:[ \t]+45b11000[ \t]+uqshrn[ \t]+z0\.h,[ \t]{z0.s-z1.s}, #15
> + *[0-9a-f]+:[ \t]+45b1101f[ \t]+uqshrn[ \t]+z31\.h,[ \t]{z0.s-z1.s}, #15
> + *[0-9a-f]+:[ \t]+45b113c0[ \t]+uqshrn[ \t]+z0\.h,[ \t]{z30.s-z31.s}, #15
> + *[0-9a-f]+:[ \t]+45b21000[ \t]+uqshrn[ \t]+z0\.h,[ \t]{z0.s-z1.s}, #14
> + *[0-9a-f]+:[ \t]+45b2101f[ \t]+uqshrn[ \t]+z31\.h,[ \t]{z0.s-z1.s}, #14
> + *[0-9a-f]+:[ \t]+45b213c0[ \t]+uqshrn[ \t]+z0\.h,[ \t]{z30.s-z31.s}, #14
> + *[0-9a-f]+:[ \t]+45b31000[ \t]+uqshrn[ \t]+z0\.h,[ \t]{z0.s-z1.s}, #13
> + *[0-9a-f]+:[ \t]+45b3101f[ \t]+uqshrn[ \t]+z31\.h,[ \t]{z0.s-z1.s}, #13
> + *[0-9a-f]+:[ \t]+45b313c0[ \t]+uqshrn[ \t]+z0\.h,[ \t]{z30.s-z31.s}, #13
> + *[0-9a-f]+:[ \t]+45b41000[ \t]+uqshrn[ \t]+z0\.h,[ \t]{z0.s-z1.s}, #12
> + *[0-9a-f]+:[ \t]+45b4101f[ \t]+uqshrn[ \t]+z31\.h,[ \t]{z0.s-z1.s}, #12
> + *[0-9a-f]+:[ \t]+45b413c0[ \t]+uqshrn[ \t]+z0\.h,[ \t]{z30.s-z31.s}, #12
> + *[0-9a-f]+:[ \t]+45b51000[ \t]+uqshrn[ \t]+z0\.h,[ \t]{z0.s-z1.s}, #11
> + *[0-9a-f]+:[ \t]+45b5101f[ \t]+uqshrn[ \t]+z31\.h,[ \t]{z0.s-z1.s}, #11
> + *[0-9a-f]+:[ \t]+45b513c0[ \t]+uqshrn[ \t]+z0\.h,[ \t]{z30.s-z31.s}, #11
> + *[0-9a-f]+:[ \t]+45b61000[ \t]+uqshrn[ \t]+z0\.h,[ \t]{z0.s-z1.s}, #10
> + *[0-9a-f]+:[ \t]+45b6101f[ \t]+uqshrn[ \t]+z31\.h,[ \t]{z0.s-z1.s}, #10
> + *[0-9a-f]+:[ \t]+45b613c0[ \t]+uqshrn[ \t]+z0\.h,[ \t]{z30.s-z31.s}, #10
> + *[0-9a-f]+:[ \t]+45b71000[ \t]+uqshrn[ \t]+z0\.h,[ \t]{z0.s-z1.s}, #9
> + *[0-9a-f]+:[ \t]+45b7101f[ \t]+uqshrn[ \t]+z31\.h,[ \t]{z0.s-z1.s}, #9
> + *[0-9a-f]+:[ \t]+45b713c0[ \t]+uqshrn[ \t]+z0\.h,[ \t]{z30.s-z31.s}, #9
> + *[0-9a-f]+:[ \t]+45b81000[ \t]+uqshrn[ \t]+z0\.h,[ \t]{z0.s-z1.s}, #8
> + *[0-9a-f]+:[ \t]+45b8101f[ \t]+uqshrn[ \t]+z31\.h,[ \t]{z0.s-z1.s}, #8
> + *[0-9a-f]+:[ \t]+45b813c0[ \t]+uqshrn[ \t]+z0\.h,[ \t]{z30.s-z31.s}, #8
> + *[0-9a-f]+:[ \t]+45b91000[ \t]+uqshrn[ \t]+z0\.h,[ \t]{z0.s-z1.s}, #7
> + *[0-9a-f]+:[ \t]+45b9101f[ \t]+uqshrn[ \t]+z31\.h,[ \t]{z0.s-z1.s}, #7
> + *[0-9a-f]+:[ \t]+45b913c0[ \t]+uqshrn[ \t]+z0\.h,[ \t]{z30.s-z31.s}, #7
> + *[0-9a-f]+:[ \t]+45ba1000[ \t]+uqshrn[ \t]+z0\.h,[ \t]{z0.s-z1.s}, #6
> + *[0-9a-f]+:[ \t]+45ba101f[ \t]+uqshrn[ \t]+z31\.h,[ \t]{z0.s-z1.s}, #6
> + *[0-9a-f]+:[ \t]+45ba13c0[ \t]+uqshrn[ \t]+z0\.h,[ \t]{z30.s-z31.s}, #6
> + *[0-9a-f]+:[ \t]+45bb1000[ \t]+uqshrn[ \t]+z0\.h,[ \t]{z0.s-z1.s}, #5
> + *[0-9a-f]+:[ \t]+45bb101f[ \t]+uqshrn[ \t]+z31\.h,[ \t]{z0.s-z1.s}, #5
> + *[0-9a-f]+:[ \t]+45bb13c0[ \t]+uqshrn[ \t]+z0\.h,[ \t]{z30.s-z31.s}, #5
> + *[0-9a-f]+:[ \t]+45bc1000[ \t]+uqshrn[ \t]+z0\.h,[ \t]{z0.s-z1.s}, #4
> + *[0-9a-f]+:[ \t]+45bc101f[ \t]+uqshrn[ \t]+z31\.h,[ \t]{z0.s-z1.s}, #4
> + *[0-9a-f]+:[ \t]+45bc13c0[ \t]+uqshrn[ \t]+z0\.h,[ \t]{z30.s-z31.s}, #4
> + *[0-9a-f]+:[ \t]+45bd1000[ \t]+uqshrn[ \t]+z0\.h,[ \t]{z0.s-z1.s}, #3
> + *[0-9a-f]+:[ \t]+45bd101f[ \t]+uqshrn[ \t]+z31\.h,[ \t]{z0.s-z1.s}, #3
> + *[0-9a-f]+:[ \t]+45bd13c0[ \t]+uqshrn[ \t]+z0\.h,[ \t]{z30.s-z31.s}, #3
> + *[0-9a-f]+:[ \t]+45be1000[ \t]+uqshrn[ \t]+z0\.h,[ \t]{z0.s-z1.s}, #2
> + *[0-9a-f]+:[ \t]+45be101f[ \t]+uqshrn[ \t]+z31\.h,[ \t]{z0.s-z1.s}, #2
> + *[0-9a-f]+:[ \t]+45be13c0[ \t]+uqshrn[ \t]+z0\.h,[ \t]{z30.s-z31.s}, #2
> + *[0-9a-f]+:[ \t]+45bf1000[ \t]+uqshrn[ \t]+z0\.h,[ \t]{z0.s-z1.s}, #1
> + *[0-9a-f]+:[ \t]+45bf101f[ \t]+uqshrn[ \t]+z31\.h,[ \t]{z0.s-z1.s}, #1
> + *[0-9a-f]+:[ \t]+45bf13c0[ \t]+uqshrn[ \t]+z0\.h,[ \t]{z30.s-z31.s}, #1
> diff --git a/gas/testsuite/gas/aarch64/uqshrn_imm.s b/gas/testsuite/gas/aarch64/uqshrn_imm.s
> new file mode 100644
> index 00000000000..6513d985bff
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/uqshrn_imm.s
> @@ -0,0 +1,73 @@
> +uqshrn z0.b, { z0.h-z1.h }, #8
> +uqshrn z31.b, { z0.h-z1.h }, #8
> +uqshrn z0.b, { z30.h-z31.h }, #8
> +uqshrn z0.b, { z0.h-z1.h }, #7
> +uqshrn z31.b, { z0.h-z1.h }, #7
> +uqshrn z0.b, { z30.h-z31.h }, #7
> +uqshrn z0.b, { z0.h-z1.h }, #6
> +uqshrn z31.b, { z0.h-z1.h }, #6
> +uqshrn z0.b, { z30.h-z31.h }, #6
> +uqshrn z0.b, { z0.h-z1.h }, #5
> +uqshrn z31.b, { z0.h-z1.h }, #5
> +uqshrn z0.b, { z30.h-z31.h }, #5
> +uqshrn z0.b, { z0.h-z1.h }, #4
> +uqshrn z31.b, { z0.h-z1.h }, #4
> +uqshrn z0.b, { z30.h-z31.h }, #4
> +uqshrn z0.b, { z0.h-z1.h }, #3
> +uqshrn z31.b, { z0.h-z1.h }, #3
> +uqshrn z0.b, { z30.h-z31.h }, #3
> +uqshrn z0.b, { z0.h-z1.h }, #2
> +uqshrn z31.b, { z0.h-z1.h }, #2
> +uqshrn z0.b, { z30.h-z31.h }, #2
> +uqshrn z0.b, { z0.h-z1.h }, #1
> +uqshrn z31.b, { z0.h-z1.h }, #1
> +uqshrn z0.b, { z30.h-z31.h }, #1
> +
> +uqshrn z0.h, { z0.s-z1.s }, #16
> +uqshrn z31.h, { z0.s-z1.s }, #16
> +uqshrn z0.h, { z30.s-z31.s }, #16
> +uqshrn z0.h, { z0.s-z1.s }, #15
> +uqshrn z31.h, { z0.s-z1.s }, #15
> +uqshrn z0.h, { z30.s-z31.s }, #15
> +uqshrn z0.h, { z0.s-z1.s }, #14
> +uqshrn z31.h, { z0.s-z1.s }, #14
> +uqshrn z0.h, { z30.s-z31.s }, #14
> +uqshrn z0.h, { z0.s-z1.s }, #13
> +uqshrn z31.h, { z0.s-z1.s }, #13
> +uqshrn z0.h, { z30.s-z31.s }, #13
> +uqshrn z0.h, { z0.s-z1.s }, #12
> +uqshrn z31.h, { z0.s-z1.s }, #12
> +uqshrn z0.h, { z30.s-z31.s }, #12
> +uqshrn z0.h, { z0.s-z1.s }, #11
> +uqshrn z31.h, { z0.s-z1.s }, #11
> +uqshrn z0.h, { z30.s-z31.s }, #11
> +uqshrn z0.h, { z0.s-z1.s }, #10
> +uqshrn z31.h, { z0.s-z1.s }, #10
> +uqshrn z0.h, { z30.s-z31.s }, #10
> +uqshrn z0.h, { z0.s-z1.s }, #9
> +uqshrn z31.h, { z0.s-z1.s }, #9
> +uqshrn z0.h, { z30.s-z31.s }, #9
> +uqshrn z0.h, { z0.s-z1.s }, #8
> +uqshrn z31.h, { z0.s-z1.s }, #8
> +uqshrn z0.h, { z30.s-z31.s }, #8
> +uqshrn z0.h, { z0.s-z1.s }, #7
> +uqshrn z31.h, { z0.s-z1.s }, #7
> +uqshrn z0.h, { z30.s-z31.s }, #7
> +uqshrn z0.h, { z0.s-z1.s }, #6
> +uqshrn z31.h, { z0.s-z1.s }, #6
> +uqshrn z0.h, { z30.s-z31.s }, #6
> +uqshrn z0.h, { z0.s-z1.s }, #5
> +uqshrn z31.h, { z0.s-z1.s }, #5
> +uqshrn z0.h, { z30.s-z31.s }, #5
> +uqshrn z0.h, { z0.s-z1.s }, #4
> +uqshrn z31.h, { z0.s-z1.s }, #4
> +uqshrn z0.h, { z30.s-z31.s }, #4
> +uqshrn z0.h, { z0.s-z1.s }, #3
> +uqshrn z31.h, { z0.s-z1.s }, #3
> +uqshrn z0.h, { z30.s-z31.s }, #3
> +uqshrn z0.h, { z0.s-z1.s }, #2
> +uqshrn z31.h, { z0.s-z1.s }, #2
> +uqshrn z0.h, { z30.s-z31.s }, #2
> +uqshrn z0.h, { z0.s-z1.s }, #1
> +uqshrn z31.h, { z0.s-z1.s }, #1
> +uqshrn z0.h, { z30.s-z31.s }, #1
> diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
> index e65b61c3f9c..08a78912301 100644
> --- a/include/opcode/aarch64.h
> +++ b/include/opcode/aarch64.h
> @@ -263,6 +263,10 @@ enum aarch64_feature_bit {
> AARCH64_FEATURE_SME_TMOP,
> /* SME MOP4 instructions. */
> AARCH64_FEATURE_SME_MOP4,
> + /* SVE2.3. */
> + AARCH64_FEATURE_SVE2p3,
> + /* SME2.3. */
> + AARCH64_FEATURE_SME2p3,
>
> /* Virtual features. These are used to gate instructions that are enabled
> by either of two (or more) sets of command line flags. */
> @@ -290,6 +294,8 @@ enum aarch64_feature_bit {
> AARCH64_FEATURE_SVE2p1_SME2p1,
> /* +sve2p2 or +sme2p2 */
> AARCH64_FEATURE_SVE2p2_SME2p2,
> + /* +sve2p3 or +sme2p3 */
> + AARCH64_FEATURE_SVE2p3_SME2p3,
> AARCH64_NUM_FEATURES
> };
>
> @@ -879,11 +885,13 @@ enum aarch64_opnd
> AARCH64_OPND_SME_Zm_17_3, /* SVE vector register in [19:17]*2+16. */
> AARCH64_OPND_SME_Znx2_6_3, /* SVE vector register list from [8:6]*2. */
> AARCH64_OPND_SME_Zmx2_17_3, /* SVE vector register list from [19:17]*2+16. */
> + AARCH64_OPND_SME_ZmxN_INDEX_22, /* SVE vector register list in [20:16].with index in 22 */
> AARCH64_OPND_SME_Zmx2, /* SVE vector register list from [20:17]*2. */
> AARCH64_OPND_SME_Zmx4, /* SVE vector register list from [20:18]*4. */
> AARCH64_OPND_SME_Znx2, /* SVE vector register list from [9:6]*2. */
> AARCH64_OPND_SME_Znx2_BIT_INDEX, /* SVE vector register list encoding a bit index from [9:6]*2. */
> AARCH64_OPND_SME_Znx4, /* SVE vector register list from [9:7]*4. */
> + AARCH64_OPND_SME_Zn3_UNTYPED, /* SVE vector register list from [9:7]. */
> AARCH64_OPND_SME_Ztx2_STRIDED, /* SVE vector register list in [4:0]&23. */
> AARCH64_OPND_SME_Ztx4_STRIDED, /* SVE vector register list in [4:0]&19. */
> AARCH64_OPND_SME_ZAda_1b, /* SME <ZAda>.H, 1-bits. */
> @@ -913,6 +921,7 @@ enum aarch64_opnd
> AARCH64_OPND_SME_ADDR_RI_U4xVL, /* SME [<Xn|SP>{, #<imm>, MUL VL}]. */
> AARCH64_OPND_SME_SM_ZA, /* SME {SM | ZA}. */
> AARCH64_OPND_SME_PnT_Wm_imm, /* SME <Pn>.<T>[<Wm>, #<imm>]. */
> + AARCH64_OPND_SME_SHRIMM3, /* 3-bit right shift, bits [18:16]. */
> AARCH64_OPND_SME_SHRIMM4, /* 4-bit right shift, bits [19:16]. */
> AARCH64_OPND_SME_SHRIMM5, /* size + 5-bit right shift, bits [23:22,20:16]. */
> AARCH64_OPND_SME_Zk_INDEX, /* Zk[index], bits [12:10,5:4]. */
> diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c
> index b0611654ead..04fc3793d96 100644
> --- a/opcodes/aarch64-asm-2.c
> +++ b/opcodes/aarch64-asm-2.c
> @@ -1153,6 +1153,10 @@ aarch64_insert_operand (const aarch64_operand *self,
> case AARCH64_OPND_SME_Znx4:
> case AARCH64_OPND_SME_Pdx2:
> return aarch64_ins_sve_aligned_reglist (self, info, code, inst, errors);
> + case AARCH64_OPND_SME_ZmxN_INDEX_22:
> + return aarch64_ins_sve_reglist_index (self, info, code, inst, errors);
> + case AARCH64_OPND_SME_Zn3_UNTYPED:
> + return aarch64_ins_sve_aligned_reglist_untyped (self, info, code, inst, errors);
> case AARCH64_OPND_SME_Ztx2_STRIDED:
> case AARCH64_OPND_SME_Ztx4_STRIDED:
> return aarch64_ins_sve_strided_reglist (self, info, code, inst, errors);
> @@ -1177,6 +1181,7 @@ aarch64_insert_operand (const aarch64_operand *self,
> return aarch64_ins_sme_sm_za (self, info, code, inst, errors);
> case AARCH64_OPND_SME_PnT_Wm_imm:
> return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
> + case AARCH64_OPND_SME_SHRIMM3:
> case AARCH64_OPND_SME_SHRIMM4:
> return aarch64_ins_plain_shrimm (self, info, code, inst, errors);
> case AARCH64_OPND_MOPS_ADDR_Rd:
> diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c
> index 0c8f4b36902..3851e587a0e 100644
> --- a/opcodes/aarch64-asm.c
> +++ b/opcodes/aarch64-asm.c
> @@ -1266,6 +1266,21 @@ aarch64_ins_sve_aligned_reglist (const aarch64_operand *self,
> return true;
> }
>
> +/* Encode a register list from the 3 upper bits where Z1:{0-7}
> + and Zn3 = Z1+2 */
> +bool
> +aarch64_ins_sve_aligned_reglist_untyped (const aarch64_operand *self,
> + const aarch64_opnd_info *info,
> + aarch64_insn *code,
> + const aarch64_inst *inst ATTRIBUTE_UNUSED,
> + aarch64_operand_error *errors ATTRIBUTE_UNUSED)
> +{
> + // unsigned int num_regs = get_operand_specific_data (self);
> + unsigned int val = info->reglist.first_regno;
> + insert_field (self->fields[0], code, val, 0);
> + return true;
> +}
> +
> /* Encode an SVE CPY/DUP immediate. */
> bool
> aarch64_ins_sve_asimm (const aarch64_operand *self,
> @@ -1351,6 +1366,21 @@ aarch64_ins_sve_strided_reglist (const aarch64_operand *self,
> return true;
> }
>
> +/* Encode {Zn - Zm}[index]. The fields array specifies which field
> + to use for Zn. */
> +bool
> +aarch64_ins_sve_reglist_index (const aarch64_operand *self ATTRIBUTE_UNUSED,
> + const aarch64_opnd_info *info ATTRIBUTE_UNUSED, aarch64_insn *code ATTRIBUTE_UNUSED,
> + const aarch64_inst *inst ATTRIBUTE_UNUSED,
> + aarch64_operand_error *errors ATTRIBUTE_UNUSED)
> +{
> + assert (info->reglist.has_index);
> + insert_field (self->fields[0], code, info->reglist.first_regno, 0);
> + insert_field (FLD_imm1_22, code, info->reglane.index, 0);
> +
> + return true;
> +}
> +
> /* Encode <pattern>{, MUL #<amount>}. The fields array specifies which
> fields to use for <pattern>. <amount> - 1 is encoded in the SVE_imm4
> field. */
> diff --git a/opcodes/aarch64-asm.h b/opcodes/aarch64-asm.h
> index 104c5e8d7a2..5e940f68d71 100644
> --- a/opcodes/aarch64-asm.h
> +++ b/opcodes/aarch64-asm.h
> @@ -98,6 +98,8 @@ AARCH64_DECL_OPD_INSERTER (ins_sve_index);
> AARCH64_DECL_OPD_INSERTER (ins_sve_limm_mov);
> AARCH64_DECL_OPD_INSERTER (ins_sve_quad_index);
> AARCH64_DECL_OPD_INSERTER (ins_sve_reglist);
> +AARCH64_DECL_OPD_INSERTER (ins_sve_reglist_index);
> +AARCH64_DECL_OPD_INSERTER (ins_sve_aligned_reglist_untyped);
> AARCH64_DECL_OPD_INSERTER (ins_sve_strided_reglist);
> AARCH64_DECL_OPD_INSERTER (ins_sve_scale);
> AARCH64_DECL_OPD_INSERTER (ins_sve_shlimm);
> diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
> index ecaea2d2fdb..1867908b525 100644
> --- a/opcodes/aarch64-dis-2.c
> +++ b/opcodes/aarch64-dis-2.c
> @@ -513,19 +513,29 @@ aarch64_opcode_lookup_1 (uint32_t word)
> }
> else
> {
> - if (((word >> 22) & 0x1) == 0)
> + if (((word >> 14) & 0x1) == 0)
> {
> - /* 33222222222211111111110000000000
> - 10987654321098765432109876543210
> - x1000000x00x100xxxxxxxxxxxxxxxxx. */
> - return A64_OPID_c0080000_zero_SME_list_of_64bit_tiles;
> + if (((word >> 22) & 0x1) == 0)
> + {
> + /* 33222222222211111111110000000000
> + 10987654321098765432109876543210
> + x1000000x00x100xx0xxxxxxxxxxxxxx. */
> + return A64_OPID_c0080000_zero_SME_list_of_64bit_tiles;
> + }
> + else
> + {
> + /* 33222222222211111111110000000000
> + 10987654321098765432109876543210
> + x1000000x10x100xx0xxxxxxxxxxxxxx. */
> + return A64_OPID_c0480001_zero_SME_ZT0_LIST;
> + }
> }
> else
> {
> /* 33222222222211111111110000000000
> 10987654321098765432109876543210
> - x1000000x10x100xxxxxxxxxxxxxxxxx. */
> - return A64_OPID_c0480001_zero_SME_ZT0_LIST;
> + x1000000xx0x100xx1xxxxxxxxxxxxxx. */
> + return A64_OPID_c0c84000_luti6_SVE_Zd_SME_ZT0_SVE_Zn;
> }
> }
> }
> @@ -598,10 +608,20 @@ aarch64_opcode_lookup_1 (uint32_t word)
> {
> if (((word >> 15) & 0x1) == 0)
> {
> - /* 33222222222211111111110000000000
> - 10987654321098765432109876543210
> - x1000000x000101x00xxxxxxxxxxxxxx. */
> - return A64_OPID_c08b0000_luti4_SME_Zdnx4_SME_ZT0_SME_Znx2_BIT_INDEX;
> + if (((word >> 16) & 0x1) == 0)
> + {
> + /* 33222222222211111111110000000000
> + 10987654321098765432109876543210
> + x1000000x000101000xxxxxxxxxxxxxx. */
> + return A64_OPID_c08a0000_luti6_SME_Zdnx4_SME_ZT0_SME_Zn3_UNTYPED;
> + }
> + else
> + {
> + /* 33222222222211111111110000000000
> + 10987654321098765432109876543210
> + x1000000x000101100xxxxxxxxxxxxxx. */
> + return A64_OPID_c08b0000_luti4_SME_Zdnx4_SME_ZT0_SME_Znx2_BIT_INDEX;
> + }
> }
> else
> {
> @@ -633,10 +653,20 @@ aarch64_opcode_lookup_1 (uint32_t word)
> {
> if (((word >> 15) & 0x1) == 0)
> {
> - /* 33222222222211111111110000000000
> - 10987654321098765432109876543210
> - x1000000xx01101x00xxxxxxxxxxxxxx. */
> - return A64_OPID_c09b0000_luti4_SME_Ztx4_STRIDED_SME_ZT0_SME_Znx2_BIT_INDEX;
> + if (((word >> 16) & 0x1) == 0)
> + {
> + /* 33222222222211111111110000000000
> + 10987654321098765432109876543210
> + x1000000xx01101000xxxxxxxxxxxxxx. */
> + return A64_OPID_c09a0000_luti6_SME_Ztx4_STRIDED_SME_ZT0_SME_Zn3_UNTYPED;
> + }
> + else
> + {
> + /* 33222222222211111111110000000000
> + 10987654321098765432109876543210
> + x1000000xx01101100xxxxxxxxxxxxxx. */
> + return A64_OPID_c09b0000_luti4_SME_Ztx4_STRIDED_SME_ZT0_SME_Znx2_BIT_INDEX;
> + }
> }
> else
> {
> @@ -7432,10 +7462,20 @@ aarch64_opcode_lookup_1 (uint32_t word)
> }
> else
> {
> - /* 33222222222211111111110000000000
> - 10987654321098765432109876543210
> - x1000001xx1xxxxx1x1101xxxxxxxxxx. */
> - return A64_OPID_c120b400_sqdmulh_SME_Zdnx2_SME_Zdnx2_SME_Zmx2;
> + if (((word >> 14) & 0x1) == 0)
> + {
> + /* 33222222222211111111110000000000
> + 10987654321098765432109876543210
> + x1000001xx1xxxxx101101xxxxxxxxxx. */
> + return A64_OPID_c120b400_sqdmulh_SME_Zdnx2_SME_Zdnx2_SME_Zmx2;
> + }
> + else
> + {
> + /* 33222222222211111111110000000000
> + 10987654321098765432109876543210
> + x1000001xx1xxxxx111101xxxxxxxxxx. */
> + return A64_OPID_c120f400_luti6_SME_Zdnx4_SVE_ZnxN_SME_ZmxN_INDEX_22;
> + }
> }
> }
> else
> @@ -7449,10 +7489,20 @@ aarch64_opcode_lookup_1 (uint32_t word)
> }
> else
> {
> - /* 33222222222211111111110000000000
> - 10987654321098765432109876543210
> - x1000001xx1xxxxx1x1111xxxxxxxxxx. */
> - return A64_OPID_c120bc00_sqdmulh_SME_Zdnx4_SME_Zdnx4_SME_Zmx4;
> + if (((word >> 14) & 0x1) == 0)
> + {
> + /* 33222222222211111111110000000000
> + 10987654321098765432109876543210
> + x1000001xx1xxxxx101111xxxxxxxxxx. */
> + return A64_OPID_c120bc00_sqdmulh_SME_Zdnx4_SME_Zdnx4_SME_Zmx4;
> + }
> + else
> + {
> + /* 33222222222211111111110000000000
> + 10987654321098765432109876543210
> + x1000001xx1xxxxx111111xxxxxxxxxx. */
> + return A64_OPID_c120fc00_luti6_SME_Ztx4_STRIDED_SVE_ZnxN_SME_ZmxN_INDEX_22;
> + }
> }
> }
> }
> @@ -13479,10 +13529,20 @@ aarch64_opcode_lookup_1 (uint32_t word)
> {
> if (((word >> 11) & 0x1) == 0)
> {
> - /* 33222222222211111111110000000000
> - 10987654321098765432109876543210
> - 010001x0xx0xxxxx000000xxxxxxxxxx. */
> - return A64_OPID_44800000_sdot_SVE_Zd_SVE_Zn_SVE_Zm_16;
> + if (((word >> 23) & 0x1) == 0)
> + {
> + /* 33222222222211111111110000000000
> + 10987654321098765432109876543210
> + 010001x00x0xxxxx000000xxxxxxxxxx. */
> + return A64_OPID_44400000_sdot_SVE_Zd_SVE_Zn_SVE_Zm_16;
> + }
> + else
> + {
> + /* 33222222222211111111110000000000
> + 10987654321098765432109876543210
> + 010001x01x0xxxxx000000xxxxxxxxxx. */
> + return A64_OPID_44800000_sdot_SVE_Zd_SVE_Zn_SVE_Zm_16;
> + }
> }
> else
> {
> @@ -13496,10 +13556,20 @@ aarch64_opcode_lookup_1 (uint32_t word)
> {
> if (((word >> 11) & 0x1) == 0)
> {
> - /* 33222222222211111111110000000000
> - 10987654321098765432109876543210
> - 010001x0xx0xxxxx000001xxxxxxxxxx. */
> - return A64_OPID_44800400_udot_SVE_Zd_SVE_Zn_SVE_Zm_16;
> + if (((word >> 23) & 0x1) == 0)
> + {
> + /* 33222222222211111111110000000000
> + 10987654321098765432109876543210
> + 010001x00x0xxxxx000001xxxxxxxxxx. */
> + return A64_OPID_44400400_udot_SVE_Zd_SVE_Zn_SVE_Zm_16;
> + }
> + else
> + {
> + /* 33222222222211111111110000000000
> + 10987654321098765432109876543210
> + 010001x01x0xxxxx000001xxxxxxxxxx. */
> + return A64_OPID_44800400_udot_SVE_Zd_SVE_Zn_SVE_Zm_16;
> + }
> }
> else
> {
> @@ -13646,10 +13716,20 @@ aarch64_opcode_lookup_1 (uint32_t word)
> {
> if (((word >> 11) & 0x1) == 0)
> {
> - /* 33222222222211111111110000000000
> - 10987654321098765432109876543210
> - 010001x00x1xxxxx000x00xxxxxxxxxx. */
> - return A64_OPID_44201000_sqrdmlah_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX;
> + if (((word >> 12) & 0x1) == 0)
> + {
> + /* 33222222222211111111110000000000
> + 10987654321098765432109876543210
> + 010001x00x1xxxxx000000xxxxxxxxxx. */
> + return A64_OPID_44200000_sdot_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX;
> + }
> + else
> + {
> + /* 33222222222211111111110000000000
> + 10987654321098765432109876543210
> + 010001x00x1xxxxx000100xxxxxxxxxx. */
> + return A64_OPID_44201000_sqrdmlah_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX;
> + }
> }
> else
> {
> @@ -13663,10 +13743,20 @@ aarch64_opcode_lookup_1 (uint32_t word)
> {
> if (((word >> 11) & 0x1) == 0)
> {
> - /* 33222222222211111111110000000000
> - 10987654321098765432109876543210
> - 010001x00x1xxxxx000x01xxxxxxxxxx. */
> - return A64_OPID_44201400_sqrdmlsh_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX;
> + if (((word >> 12) & 0x1) == 0)
> + {
> + /* 33222222222211111111110000000000
> + 10987654321098765432109876543210
> + 010001x00x1xxxxx000001xxxxxxxxxx. */
> + return A64_OPID_44200400_udot_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX;
> + }
> + else
> + {
> + /* 33222222222211111111110000000000
> + 10987654321098765432109876543210
> + 010001x00x1xxxxx000101xxxxxxxxxx. */
> + return A64_OPID_44201400_sqrdmlsh_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX;
> + }
> }
> else
> {
> @@ -15148,26 +15238,46 @@ aarch64_opcode_lookup_1 (uint32_t word)
> {
> if (((word >> 11) & 0x1) == 0)
> {
> - /* 33222222222211111111110000000000
> - 10987654321098765432109876543210
> - 010001x0xx0xxxxx110x01xxxxxxxxxx. */
> - return A64_OPID_4400c400_uclamp_SVE_Zd_SVE_Zn_SVE_Zm_16;
> + if (((word >> 12) & 0x1) == 0)
> + {
> + /* 33222222222211111111110000000000
> + 10987654321098765432109876543210
> + 010001x0xx0xxxxx110001xxxxxxxxxx. */
> + return A64_OPID_4400c400_uclamp_SVE_Zd_SVE_Zn_SVE_Zm_16;
> + }
> + else
> + {
> + /* 33222222222211111111110000000000
> + 10987654321098765432109876543210
> + 010001x0xx0xxxxx110101xxxxxxxxxx. */
> + return A64_OPID_4400d400_sabal_SVE_Zd_SVE_Zn_SVE_Zm_16;
> + }
> }
> else
> {
> - if (((word >> 23) & 0x1) == 0)
> + if (((word >> 12) & 0x1) == 0)
> {
> - /* 33222222222211111111110000000000
> - 10987654321098765432109876543210
> - 010001x00x0xxxxx110x11xxxxxxxxxx. */
> - return A64_OPID_4400cc00_udot_SVE_Zd_SVE_Zn_SVE_Zm_16;
> + if (((word >> 23) & 0x1) == 0)
> + {
> + /* 33222222222211111111110000000000
> + 10987654321098765432109876543210
> + 010001x00x0xxxxx110011xxxxxxxxxx. */
> + return A64_OPID_4400cc00_udot_SVE_Zd_SVE_Zn_SVE_Zm_16;
> + }
> + else
> + {
> + /* 33222222222211111111110000000000
> + 10987654321098765432109876543210
> + 010001x01x0xxxxx110011xxxxxxxxxx. */
> + return A64_OPID_4480cc00_udot_SVE_Zd_SVE_Zn_SVE_Zm3_19_INDEX;
> + }
> }
> else
> {
> /* 33222222222211111111110000000000
> 10987654321098765432109876543210
> - 010001x01x0xxxxx110x11xxxxxxxxxx. */
> - return A64_OPID_4480cc00_udot_SVE_Zd_SVE_Zn_SVE_Zm3_19_INDEX;
> + 010001x0xx0xxxxx110111xxxxxxxxxx. */
> + return A64_OPID_4400dc00_uabal_SVE_Zd_SVE_Zn_SVE_Zm_16;
> }
> }
> }
> @@ -16235,10 +16345,20 @@ aarch64_opcode_lookup_1 (uint32_t word)
> {
> if (((word >> 19) & 0x1) == 0)
> {
> - /* 33222222222211111111110000000000
> - 10987654321098765432109876543210
> - 010001x0xx0x0000101xxxxxxxxxxxxx. */
> - return A64_OPID_4480a000_urecpe_SVE_Zd_SVE_Pg3_SVE_Zn;
> + if (((word >> 20) & 0x1) == 0)
> + {
> + /* 33222222222211111111110000000000
> + 10987654321098765432109876543210
> + 010001x0xx000000101xxxxxxxxxxxxx. */
> + return A64_OPID_4480a000_urecpe_SVE_Zd_SVE_Pg3_SVE_Zn;
> + }
> + else
> + {
> + /* 33222222222211111111110000000000
> + 10987654321098765432109876543210
> + 010001x0xx010000101xxxxxxxxxxxxx. */
> + return A64_OPID_4410a000_subp_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5;
> + }
> }
> else
> {
> @@ -16668,10 +16788,20 @@ aarch64_opcode_lookup_1 (uint32_t word)
> }
> else
> {
> - /* 33222222222211111111110000000000
> - 10987654321098765432109876543210
> - 000001x0xx1xxxxx011x10xxxxxxxxxx. */
> - return A64_OPID_04206800_smulh_SVE_Zd_SVE_Zn_SVE_Zm_16;
> + if (((word >> 12) & 0x1) == 0)
> + {
> + /* 33222222222211111111110000000000
> + 10987654321098765432109876543210
> + 000001x0xx1xxxxx011010xxxxxxxxxx. */
> + return A64_OPID_04206800_smulh_SVE_Zd_SVE_Zn_SVE_Zm_16;
> + }
> + else
> + {
> + /* 33222222222211111111110000000000
> + 10987654321098765432109876543210
> + 000001x0xx1xxxxx011110xxxxxxxxxx. */
> + return A64_OPID_04207800_addqp_SVE_Zd_SVE_Zn_SVE_Zm_16;
> + }
> }
> }
> else
> @@ -16695,10 +16825,20 @@ aarch64_opcode_lookup_1 (uint32_t word)
> }
> else
> {
> - /* 33222222222211111111110000000000
> - 10987654321098765432109876543210
> - 000001x0xx1xxxxx011x11xxxxxxxxxx. */
> - return A64_OPID_04206c00_umulh_SVE_Zd_SVE_Zn_SVE_Zm_16;
> + if (((word >> 12) & 0x1) == 0)
> + {
> + /* 33222222222211111111110000000000
> + 10987654321098765432109876543210
> + 000001x0xx1xxxxx011011xxxxxxxxxx. */
> + return A64_OPID_04206c00_umulh_SVE_Zd_SVE_Zn_SVE_Zm_16;
> + }
> + else
> + {
> + /* 33222222222211111111110000000000
> + 10987654321098765432109876543210
> + 000001x0xx1xxxxx011111xxxxxxxxxx. */
> + return A64_OPID_04207c00_addsubp_SVE_Zd_SVE_Zn_SVE_Zm_16;
> + }
> }
> }
> }
> @@ -21414,10 +21554,40 @@ aarch64_opcode_lookup_1 (uint32_t word)
> }
> else
> {
> - /* 33222222222211111111110000000000
> - 10987654321098765432109876543210
> - x10001x11x1xxxxx000xxxxxxxxxxxxx. */
> - return A64_OPID_45b00800_sqrshrun_SVE_Zd_SME_Znx2_SME_SHRIMM4;
> + if (((word >> 11) & 0x1) == 0)
> + {
> + if (((word >> 12) & 0x1) == 0)
> + {
> + /* 33222222222211111111110000000000
> + 10987654321098765432109876543210
> + x10001x11x1xxxxx00000xxxxxxxxxxx. */
> + return A64_OPID_45a00000_sqshrn_SVE_Zd_SME_Znx2_SVE_SHRIMM_UNPRED_22;
> + }
> + else
> + {
> + /* 33222222222211111111110000000000
> + 10987654321098765432109876543210
> + x10001x11x1xxxxx00010xxxxxxxxxxx. */
> + return A64_OPID_45a01000_uqshrn_SVE_Zd_SME_Znx2_SVE_SHRIMM_UNPRED_22;
> + }
> + }
> + else
> + {
> + if (((word >> 20) & 0x1) == 0)
> + {
> + /* 33222222222211111111110000000000
> + 10987654321098765432109876543210
> + x10001x11x10xxxx000x1xxxxxxxxxxx. */
> + return A64_OPID_45a80800_sqrshrun_SVE_Zd_SME_Znx2_SME_SHRIMM3;
> + }
> + else
> + {
> + /* 33222222222211111111110000000000
> + 10987654321098765432109876543210
> + x10001x11x11xxxx000x1xxxxxxxxxxx. */
> + return A64_OPID_45b00800_sqrshrun_SVE_Zd_SME_Znx2_SME_SHRIMM4;
> + }
> + }
> }
> }
> }
> @@ -22101,19 +22271,49 @@ aarch64_opcode_lookup_1 (uint32_t word)
> }
> else
> {
> - if (((word >> 12) & 0x1) == 0)
> + if (((word >> 11) & 0x1) == 0)
> {
> /* 33222222222211111111110000000000
> 10987654321098765432109876543210
> - x10001x11x1xxxxx0010xxxxxxxxxxxx. */
> - return A64_OPID_45b02800_sqrshrn_SVE_Zd_SME_Znx2_SME_SHRIMM4;
> + x10001x11x1xxxxx001x0xxxxxxxxxxx. */
> + return A64_OPID_45a02000_sqshrun_SVE_Zd_SME_Znx2_SVE_SHRIMM_UNPRED_22;
> }
> else
> {
> - /* 33222222222211111111110000000000
> - 10987654321098765432109876543210
> - x10001x11x1xxxxx0011xxxxxxxxxxxx. */
> - return A64_OPID_45b03800_uqrshrn_SVE_Zd_SME_Znx2_SME_SHRIMM4;
> + if (((word >> 12) & 0x1) == 0)
> + {
> + if (((word >> 20) & 0x1) == 0)
> + {
> + /* 33222222222211111111110000000000
> + 10987654321098765432109876543210
> + x10001x11x10xxxx00101xxxxxxxxxxx. */
> + return A64_OPID_45a82800_sqrshrn_SVE_Zd_SME_Znx2_SME_SHRIMM3;
> + }
> + else
> + {
> + /* 33222222222211111111110000000000
> + 10987654321098765432109876543210
> + x10001x11x11xxxx00101xxxxxxxxxxx. */
> + return A64_OPID_45b02800_sqrshrn_SVE_Zd_SME_Znx2_SME_SHRIMM4;
> + }
> + }
> + else
> + {
> + if (((word >> 20) & 0x1) == 0)
> + {
> + /* 33222222222211111111110000000000
> + 10987654321098765432109876543210
> + x10001x11x10xxxx00111xxxxxxxxxxx. */
> + return A64_OPID_45a83800_uqrshrn_SVE_Zd_SME_Znx2_SME_SHRIMM3;
> + }
> + else
> + {
> + /* 33222222222211111111110000000000
> + 10987654321098765432109876543210
> + x10001x11x11xxxx00111xxxxxxxxxxx. */
> + return A64_OPID_45b03800_uqrshrn_SVE_Zd_SME_Znx2_SME_SHRIMM4;
> + }
> + }
> }
> }
> }
> @@ -22249,10 +22449,30 @@ aarch64_opcode_lookup_1 (uint32_t word)
> }
> else
> {
> - /* 33222222222211111111110000000000
> - 10987654321098765432109876543210
> - 010001x1xx1xxxxx101x11xxxxxxxxxx. */
> - return A64_OPID_4520bc00_luti4_SVE_Zd_SVE_ZnxN_SVE_Zm2_22_INDEX;
> + if (((word >> 12) & 0x1) == 0)
> + {
> + if (((word >> 22) & 0x1) == 0)
> + {
> + /* 33222222222211111111110000000000
> + 10987654321098765432109876543210
> + 010001x1x01xxxxx101011xxxxxxxxxx. */
> + return A64_OPID_4520ac00_luti6_SVE_Zd_SVE_ZnxN_SVE_Zm_16;
> + }
> + else
> + {
> + /* 33222222222211111111110000000000
> + 10987654321098765432109876543210
> + 010001x1x11xxxxx101011xxxxxxxxxx. */
> + return A64_OPID_4560ac00_luti6_SVE_Zd_SVE_ZnxN_SVE_Zm1_23_INDEX;
> + }
> + }
> + else
> + {
> + /* 33222222222211111111110000000000
> + 10987654321098765432109876543210
> + 010001x1xx1xxxxx101111xxxxxxxxxx. */
> + return A64_OPID_4520bc00_luti4_SVE_Zd_SVE_ZnxN_SVE_Zm2_22_INDEX;
> + }
> }
> }
> }
> @@ -23277,10 +23497,50 @@ aarch64_opcode_lookup_1 (uint32_t word)
> }
> else
> {
> - /* 33222222222211111111110000000000
> - 10987654321098765432109876543210
> - 011001x1xx0xx100001xxxxxxxxxxxxx. */
> - return A64_OPID_65042000_fmaxnmv_SVE_Vd_SVE_Pg3_SVE_Zn;
> + if (((word >> 19) & 0x1) == 0)
> + {
> + /* 33222222222211111111110000000000
> + 10987654321098765432109876543210
> + 011001x1xx0x0100001xxxxxxxxxxxxx. */
> + return A64_OPID_65042000_fmaxnmv_SVE_Vd_SVE_Pg3_SVE_Zn;
> + }
> + else
> + {
> + if (((word >> 10) & 0x1) == 0)
> + {
> + if (((word >> 11) & 0x1) == 0)
> + {
> + /* 33222222222211111111110000000000
> + 10987654321098765432109876543210
> + 011001x1xx0x1100001x00xxxxxxxxxx. */
> + return A64_OPID_650c3000_scvtf_SVE_Zd_SVE_Zn;
> + }
> + else
> + {
> + /* 33222222222211111111110000000000
> + 10987654321098765432109876543210
> + 011001x1xx0x1100001x10xxxxxxxxxx. */
> + return A64_OPID_650c3800_scvtflt_SVE_Zd_SVE_Zn;
> + }
> + }
> + else
> + {
> + if (((word >> 11) & 0x1) == 0)
> + {
> + /* 33222222222211111111110000000000
> + 10987654321098765432109876543210
> + 011001x1xx0x1100001x01xxxxxxxxxx. */
> + return A64_OPID_650c3400_ucvtf_SVE_Zd_SVE_Zn;
> + }
> + else
> + {
> + /* 33222222222211111111110000000000
> + 10987654321098765432109876543210
> + 011001x1xx0x1100001x11xxxxxxxxxx. */
> + return A64_OPID_650c3c00_ucvtflt_SVE_Zd_SVE_Zn;
> + }
> + }
> + }
> }
> }
> else
> @@ -23414,10 +23674,30 @@ aarch64_opcode_lookup_1 (uint32_t word)
> }
> else
> {
> - /* 33222222222211111111110000000000
> - 10987654321098765432109876543210
> - 011001x1xx0xx101001xxxxxxxxxxxxx. */
> - return A64_OPID_65052000_fminnmv_SVE_Vd_SVE_Pg3_SVE_Zn;
> + if (((word >> 19) & 0x1) == 0)
> + {
> + /* 33222222222211111111110000000000
> + 10987654321098765432109876543210
> + 011001x1xx0x0101001xxxxxxxxxxxxx. */
> + return A64_OPID_65052000_fminnmv_SVE_Vd_SVE_Pg3_SVE_Zn;
> + }
> + else
> + {
> + if (((word >> 10) & 0x1) == 0)
> + {
> + /* 33222222222211111111110000000000
> + 10987654321098765432109876543210
> + 011001x1xx0x1101001xx0xxxxxxxxxx. */
> + return A64_OPID_650d3000_fcvtzsn_SVE_Zd_SME_Znx2;
> + }
> + else
> + {
> + /* 33222222222211111111110000000000
> + 10987654321098765432109876543210
> + 011001x1xx0x1101001xx1xxxxxxxxxx. */
> + return A64_OPID_650d3400_fcvtzun_SVE_Zd_SME_Znx2;
> + }
> + }
> }
> }
> else
> @@ -37583,6 +37863,10 @@ aarch64_extract_operand (const aarch64_operand *self,
> case AARCH64_OPND_SME_Znx4:
> case AARCH64_OPND_SME_Pdx2:
> return aarch64_ext_sve_aligned_reglist (self, info, code, inst, errors);
> + case AARCH64_OPND_SME_ZmxN_INDEX_22:
> + return aarch64_ext_sve_reglist_index (self, info, code, inst, errors);
> + case AARCH64_OPND_SME_Zn3_UNTYPED:
> + return aarch64_ext_sve_aligned_reglist_untyped (self, info, code, inst, errors);
> case AARCH64_OPND_SME_Ztx2_STRIDED:
> case AARCH64_OPND_SME_Ztx4_STRIDED:
> return aarch64_ext_sve_strided_reglist (self, info, code, inst, errors);
> @@ -37607,6 +37891,7 @@ aarch64_extract_operand (const aarch64_operand *self,
> return aarch64_ext_sme_sm_za (self, info, code, inst, errors);
> case AARCH64_OPND_SME_PnT_Wm_imm:
> return aarch64_ext_sme_pred_reg_with_index (self, info, code, inst, errors);
> + case AARCH64_OPND_SME_SHRIMM3:
> case AARCH64_OPND_SME_SHRIMM4:
> return aarch64_ext_plain_shrimm (self, info, code, inst, errors);
> case AARCH64_OPND_MOPS_ADDR_Rd:
> diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
> index c9e60a97152..9a6b56b088d 100644
> --- a/opcodes/aarch64-dis.c
> +++ b/opcodes/aarch64-dis.c
> @@ -1897,6 +1897,23 @@ aarch64_ext_sve_aligned_reglist (const aarch64_operand *self,
> return true;
> }
>
> +/* Decode a register list from the 3 upper bits where Reg1:{0-7}
> + and Reg3 = Z1+2 */
> +bool
> +aarch64_ext_sve_aligned_reglist_untyped (const aarch64_operand *self,
> + aarch64_opnd_info *info, aarch64_insn code,
> + const aarch64_inst *inst ATTRIBUTE_UNUSED,
> + aarch64_operand_error *errors
> + ATTRIBUTE_UNUSED)
> +{
> + unsigned int num_regs = get_operand_specific_data (self);
> + unsigned int val = extract_field (self->fields[0], code, 0);
> + info->reglist.first_regno = val;
> + info->reglist.num_regs = num_regs;
> + info->reglist.stride = 1;
> + return true;
> +}
> +
> /* Decode an SVE CPY/DUP immediate. */
> bool
> aarch64_ext_sve_asimm (const aarch64_operand *self,
> @@ -2353,6 +2370,23 @@ aarch64_ext_sve_reglist_zt (const aarch64_operand *self,
> return true;
> }
>
> +/* Decode { <Zm1>-<Zm2> }[<index>]. The fields array specifies which field
> + to use for Zm. The opcode-dependent value specifies the number
> + of registers in the list. */
> +bool
> +aarch64_ext_sve_reglist_index (const aarch64_operand *self,
> + aarch64_opnd_info *info, aarch64_insn code,
> + const aarch64_inst *inst ATTRIBUTE_UNUSED,
> + aarch64_operand_error *errors ATTRIBUTE_UNUSED)
> +{
> + info->reglist.first_regno = extract_field (self->fields[0], code, 0);
> + info->reglist.num_regs = get_opcode_dependent_value (inst->opcode);
> + info->reglist.stride = 1;
> + info->reglist.has_index = true;
> + info->reglist.index = extract_field (FLD_imm1_22, code, 0);
> + return true;
> +}
> +
> /* Decode a strided register list. The first field holds the top bit
> (0 or 16) and the second field holds the lower bits. The stride is
> 16 divided by the list length. */
> @@ -2368,6 +2402,7 @@ aarch64_ext_sve_strided_reglist (const aarch64_operand *self,
> info->reglist.first_regno = upper * 16 + lower;
> info->reglist.num_regs = get_operand_specific_data (self);
> info->reglist.stride = 16 / info->reglist.num_regs;
> +
Unrelated change?
> return true;
> }
>
> diff --git a/opcodes/aarch64-dis.h b/opcodes/aarch64-dis.h
> index 9021113e2ab..45f425b08fa 100644
> --- a/opcodes/aarch64-dis.h
> +++ b/opcodes/aarch64-dis.h
> @@ -122,6 +122,8 @@ AARCH64_DECL_OPD_EXTRACTOR (ext_sve_index);
> AARCH64_DECL_OPD_EXTRACTOR (ext_sve_limm_mov);
> AARCH64_DECL_OPD_EXTRACTOR (ext_sve_quad_index);
> AARCH64_DECL_OPD_EXTRACTOR (ext_sve_reglist);
> +AARCH64_DECL_OPD_EXTRACTOR (ext_sve_reglist_index);
> +AARCH64_DECL_OPD_EXTRACTOR (ext_sve_aligned_reglist_untyped);
> AARCH64_DECL_OPD_EXTRACTOR (ext_sve_strided_reglist);
> AARCH64_DECL_OPD_EXTRACTOR (ext_sve_scale);
> AARCH64_DECL_OPD_EXTRACTOR (ext_sve_shlimm);
> diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c
> index 7f3b25eae38..2bb4c36e058 100644
> --- a/opcodes/aarch64-opc-2.c
> +++ b/opcodes/aarch64-opc-2.c
> @@ -288,11 +288,13 @@ const struct aarch64_operand aarch64_operands[] =
> {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_17_3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CONST_1, FLD_SME_Zm17_3, FLD_CONST_0}, "an SVE vector register"},
> {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Znx2_6_3", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CONST_0, FLD_SME_Zn6_3, FLD_CONST_0}, "a list of SVE vector registers"},
> {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zmx2_17_3", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CONST_1, FLD_SME_Zm17_3, FLD_CONST_0}, "a list of SVE vector registers"},
> + {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_ZmxN_INDEX_22", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16, FLD_imm1_22}, "a list of SVE vector registers with index"},
> {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zmx2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm2, FLD_CONST_0}, "a list of SVE vector registers"},
> {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zmx4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm4, FLD_CONST_00}, "a list of SVE vector registers"},
> {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Znx2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zn2, FLD_CONST_0}, "a list of SVE vector registers"},
> {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Znx2_BIT_INDEX", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zn2, FLD_CONST_0}, "a list of SVE vector registers"},
> {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Znx4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zn4, FLD_CONST_00}, "a list of SVE vector registers"},
> + {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zn3_UNTYPED", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zn4}, "a list of untyped SVE vector registers"},
> {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Ztx2_STRIDED", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_ZtT, FLD_SME_Zt3}, "a list of SVE vector registers"},
> {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Ztx4_STRIDED", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_ZtT, FLD_SME_Zt2}, "a list of SVE vector registers"},
> {AARCH64_OPND_CLASS_SVE_REG, "SME_ZAda_1b", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_ZAda_1b}, "an SME ZA tile ZA0-ZA1"},
> @@ -322,6 +324,7 @@ const struct aarch64_operand aarch64_operands[] =
> {AARCH64_OPND_CLASS_ADDRESS, "SME_ADDR_RI_U4xVL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_imm4_0}, "memory offset"},
> {AARCH64_OPND_CLASS_ADDRESS, "SME_SM_ZA", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm}, "streaming mode"},
> {AARCH64_OPND_CLASS_SVE_REG, "SME_PnT_Wm_imm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rm,FLD_SVE_Pn,FLD_SME_i1,FLD_SME_tszh,FLD_SME_tszl}, "Source scalable predicate register with index "},
> + {AARCH64_OPND_CLASS_IMMEDIATE, "SME_SHRIMM3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm3}, "a shift-right immediate operand"},
> {AARCH64_OPND_CLASS_IMMEDIATE, "SME_SHRIMM4", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm4}, "a shift-right immediate operand"},
> {AARCH64_OPND_CLASS_IMMEDIATE, "SME_SHRIMM5", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_tszh,FLD_SVE_imm5b}, "a shift-right immediate operand"},
> {AARCH64_OPND_CLASS_SVE_REG, "SME_Zk_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm2_4, FLD_CONST_1, FLD_SVE_i3l2, FLD_CONST_1, FLD_imm2_10}, "an indexed SVE vector register"},
> diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
> index b074765920e..dbbe05b7f38 100644
> --- a/opcodes/aarch64-opc.c
> +++ b/opcodes/aarch64-opc.c
> @@ -361,6 +361,7 @@ const aarch64_field aarch64_fields[] =
> AARCH64_FIELD (14, 1), /* imm1_14: general immediate in bits [14]. */
> AARCH64_FIELD (15, 1), /* imm1_15: general immediate in bits [15]. */
> AARCH64_FIELD (16, 1), /* imm1_16: general immediate in bits [16]. */
> + AARCH64_FIELD (22, 1), /* imm1_22: general immediate in bits [22]. */
Is the indentation here wrong?
> AARCH64_FIELD ( 0, 2), /* imm2_0: general immediate in bits [1:0]. */
> AARCH64_FIELD ( 1, 2), /* imm2_1: general immediate in bits [2:1]. */
> AARCH64_FIELD ( 2, 2), /* imm2_2: general immediate in bits [3:2]. */
> @@ -2072,6 +2073,10 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
> return false;
> break;
>
> + case AARCH64_OPND_SME_ZmxN_INDEX_22:
> + case AARCH64_OPND_SME_Zn3_UNTYPED:
> + break;
> +
This is missing checks - look at the existing reglist and reglane operands to
see what sort of checks are required. Since you're adding new operand types,
it's a good idea to write tests for various edge cases that shouldn't be
allowed (e.g. index out of range, register number out of range, wrong length of
reglist) to check that they are rejected with sensible error messages (although
some issues with error messages might constitute existing technical debt).
> default:
> abort ();
> }
> @@ -3257,6 +3262,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
> }
> break;
>
> + case AARCH64_OPND_SME_SHRIMM3:
> case AARCH64_OPND_SME_SHRIMM4:
> size = 1 << get_operand_fields_width (get_operand_from_code (type));
> if (!value_in_range_p (opnd->imm.value, 1, size))
> @@ -4410,9 +4416,11 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
> case AARCH64_OPND_SME_Zmx2_17_3:
> case AARCH64_OPND_SME_Zmx2:
> case AARCH64_OPND_SME_Zmx4:
> + case AARCH64_OPND_SME_ZmxN_INDEX_22:
> case AARCH64_OPND_SME_Znx2:
> case AARCH64_OPND_SME_Znx2_BIT_INDEX:
> case AARCH64_OPND_SME_Znx4:
> + case AARCH64_OPND_SME_Zn3_UNTYPED:
> case AARCH64_OPND_SME_Ztx2_STRIDED:
> case AARCH64_OPND_SME_Ztx4_STRIDED:
> print_register_list (buf, size, opnd, "z", styler);
> @@ -4617,6 +4625,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
> case AARCH64_OPND_FBITS:
> case AARCH64_OPND_TME_UIMM16:
> case AARCH64_OPND_SIMM5:
> + case AARCH64_OPND_SME_SHRIMM3:
> case AARCH64_OPND_SME_SHRIMM4:
> case AARCH64_OPND_SME_SHRIMM5:
> case AARCH64_OPND_SVE_SHLIMM_PRED:
> diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h
> index 5d544d53baf..6d67190ff60 100644
> --- a/opcodes/aarch64-opc.h
> +++ b/opcodes/aarch64-opc.h
> @@ -165,6 +165,7 @@ enum aarch64_field_kind
> FLD_imm1_14,
> FLD_imm1_15,
> FLD_imm1_16,
> + FLD_imm1_22,
> FLD_imm2_0,
> FLD_imm2_1,
> FLD_imm2_2,
> diff --git a/opcodes/aarch64-tbl-2.h b/opcodes/aarch64-tbl-2.h
> index 1263f1f9bd8..92ca8ff995a 100644
> --- a/opcodes/aarch64-tbl-2.h
> +++ b/opcodes/aarch64-tbl-2.h
> @@ -3995,5 +3995,33 @@ enum aarch64_opcode_idx
> A64_OPID_a1c00018_usmop4s_SME_ZAda_3b_SME_Zn_6_3_SME_Zm_17_3,
> A64_OPID_a1c00218_usmop4s_SME_ZAda_3b_SME_Znx2_6_3_SME_Zm_17_3,
> A64_OPID_a1d00218_usmop4s_SME_ZAda_3b_SME_Znx2_6_3_SME_Zmx2_17_3,
> + A64_OPID_4520ac00_luti6_SVE_Zd_SVE_ZnxN_SVE_Zm_16,
> + A64_OPID_c120f400_luti6_SME_Zdnx4_SVE_ZnxN_SME_ZmxN_INDEX_22,
> + A64_OPID_c120fc00_luti6_SME_Ztx4_STRIDED_SVE_ZnxN_SME_ZmxN_INDEX_22,
> + A64_OPID_c08a0000_luti6_SME_Zdnx4_SME_ZT0_SME_Zn3_UNTYPED,
> + A64_OPID_c09a0000_luti6_SME_Ztx4_STRIDED_SME_ZT0_SME_Zn3_UNTYPED,
> + A64_OPID_c0c84000_luti6_SVE_Zd_SME_ZT0_SVE_Zn,
> + A64_OPID_04207800_addqp_SVE_Zd_SVE_Zn_SVE_Zm_16,
> + A64_OPID_04207c00_addsubp_SVE_Zd_SVE_Zn_SVE_Zm_16,
> + A64_OPID_4400d400_sabal_SVE_Zd_SVE_Zn_SVE_Zm_16,
> + A64_OPID_650c3000_scvtf_SVE_Zd_SVE_Zn,
> + A64_OPID_650c3800_scvtflt_SVE_Zd_SVE_Zn,
> + A64_OPID_44400000_sdot_SVE_Zd_SVE_Zn_SVE_Zm_16,
> + A64_OPID_44200000_sdot_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX,
> + A64_OPID_4410a000_subp_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5,
> + A64_OPID_4400dc00_uabal_SVE_Zd_SVE_Zn_SVE_Zm_16,
> + A64_OPID_650c3400_ucvtf_SVE_Zd_SVE_Zn,
> + A64_OPID_650c3c00_ucvtflt_SVE_Zd_SVE_Zn,
> + A64_OPID_44400400_udot_SVE_Zd_SVE_Zn_SVE_Zm_16,
> + A64_OPID_44200400_udot_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX,
> + A64_OPID_650d3000_fcvtzsn_SVE_Zd_SME_Znx2,
> + A64_OPID_650d3400_fcvtzun_SVE_Zd_SME_Znx2,
> + A64_OPID_4560ac00_luti6_SVE_Zd_SVE_ZnxN_SVE_Zm1_23_INDEX,
> + A64_OPID_45a82800_sqrshrn_SVE_Zd_SME_Znx2_SME_SHRIMM3,
> + A64_OPID_45a80800_sqrshrun_SVE_Zd_SME_Znx2_SME_SHRIMM3,
> + A64_OPID_45a00000_sqshrn_SVE_Zd_SME_Znx2_SVE_SHRIMM_UNPRED_22,
> + A64_OPID_45a02000_sqshrun_SVE_Zd_SME_Znx2_SVE_SHRIMM_UNPRED_22,
> + A64_OPID_45a83800_uqrshrn_SVE_Zd_SME_Znx2_SME_SHRIMM3,
> + A64_OPID_45a01000_uqshrn_SVE_Zd_SME_Znx2_SVE_SHRIMM_UNPRED_22,
> A64_OPID_MAX,
> };
> diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
> index 2fc69c27791..7f6fbbb977e 100644
> --- a/opcodes/aarch64-tbl.h
> +++ b/opcodes/aarch64-tbl.h
> @@ -1812,6 +1812,10 @@
> { \
> QLF3(S_H,S_S,NIL), \
> }
> +#define OP_SVE_BHU \
> +{ \
> + QLF3(S_B,S_H,NIL), \
> +}
> #define OP_SVE_HU \
> { \
> QLF2(S_H,NIL), \
> @@ -2119,6 +2123,11 @@
> QLF3(S_B,S_S,NIL), \
> QLF3(S_H,S_D,NIL), \
> }
> +#define OP_SVE_VVU_BH_HS \
> +{ \
> + QLF3(S_B,S_H,NIL), \
> + QLF3(S_H,S_S,NIL), \
> +}
> #define OP_SVE_VVU_HSD_BHS \
> { \
> QLF3(S_H,S_B,NIL), \
> @@ -3057,6 +3066,12 @@ static const aarch64_feature_set aarch64_feature_sme_mop4_f8f32 =
> AARCH64_FEATURES (2, SME_MOP4, SME_F8F32);
> static const aarch64_feature_set aarch64_feature_sme_mop4_i16i64 =
> AARCH64_FEATURES (2, SME_MOP4, SME_I16I64);
> +static const aarch64_feature_set aarch64_feature_sve2p3 =
> + AARCH64_FEATURE (SVE2p3);
> +static const aarch64_feature_set aarch64_feature_sme2p3 =
> + AARCH64_FEATURE (SME2p3);
> +static const aarch64_feature_set aarch64_feature_sve2p3_sme2p3 =
> + AARCH64_FEATURE (SVE2p3_SME2p3);
>
> #define CORE &aarch64_feature_v8
> #define FP &aarch64_feature_fp
> @@ -3181,6 +3196,9 @@ static const aarch64_feature_set aarch64_feature_sme_mop4_i16i64 =
> #define SME_MOP4_F8F16 &aarch64_feature_sme_mop4_f8f16
> #define SME_MOP4_F8F32 &aarch64_feature_sme_mop4_f8f32
> #define SME_MOP4_I16I64 &aarch64_feature_sme_mop4_i16i64
> +#define SVE2p3 &aarch64_feature_sve2p3
> +#define SME2p3 &aarch64_feature_sme2p3
> +#define SVE2p3_SME2p3 &aarch64_feature_sve2p3_sme2p3
>
> #define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
> { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL }
> @@ -3510,6 +3528,16 @@ static const aarch64_feature_set aarch64_feature_sme_mop4_i16i64 =
> #define SME_MOP4_I16I64_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,TIED) \
> { NAME, OPCODE, MASK, CLASS, 0, SME_MOP4_I16I64, OPS, QUALS, \
> FLAGS | F_STRICT, 0, TIED, NULL }
> +#define SVE2p3_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS, TIED) \
> + { NAME, OPCODE, MASK, CLASS, OP, SVE2p3, OPS, QUALS, \
> + F_STRICT | FLAGS, CONSTRAINTS, TIED, NULL }
> +#define SME2p3_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS, TIED) \
> + { NAME, OPCODE, MASK, CLASS, OP, SME2p3, OPS, QUALS, \
> + FLAGS, CONSTRAINTS, TIED, NULL }
> +#define SVE2p3_SME2p3_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS, TIED) \
> + { NAME, OPCODE, MASK, CLASS, OP, SVE2p3_SME2p3, OPS, QUALS, \
> + F_STRICT | FLAGS, CONSTRAINTS, TIED, NULL }
I think it might be better to include the F_INVALID_IMM_SYMS_3 in the macro
here, since that would be consistent with the placement for existing
instructions, but I don't mind much either way.
> +
>
> #define MOPS_CPY_OP1_OP2_PME_INSN(NAME, OPCODE, MASK, FLAGS, CONSTRAINTS) \
> MOPS_INSN (NAME, OPCODE, MASK, 0, \
> @@ -7737,6 +7765,39 @@ const struct aarch64_opcode aarch64_opcode_table[] =
> SME_MOP4_I16I64_INSN ("usmop4s", 0xa1c00018, 0xfff1fe38, sme_misc, OP3 (SME_ZAda_3b, SME_Zn_6_3, SME_Zm_17_3), OP_SVE_DHH, 0, 0),
> SME_MOP4_I16I64_INSN ("usmop4s", 0xa1c00218, 0xfff1fe38, sme_misc, OP3 (SME_ZAda_3b, SME_Znx2_6_3, SME_Zm_17_3), OP_SVE_DHH, 0, 0),
> SME_MOP4_I16I64_INSN ("usmop4s", 0xa1d00218, 0xfff1fe38, sme_misc, OP3 (SME_ZAda_3b, SME_Znx2_6_3, SME_Zmx2_17_3), OP_SVE_DHH, 0, 0),
Add a blank line here for consistency.
> + /* SVE2p3 instructions. */
> + SVE2p3_INSN ("luti6", 0x4520ac00, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_ZnxN, SVE_Zm_16), OP_SVE_BB, F_OD(2), 0, 0),
This should use OP_SVE_BBU.
> +
> + /* SME2p3 instructions. */
All of these five luti6 variants should use OP_SVE_HUU or OP_SVE_BUU:
> + SME2p3_INSN ("luti6", 0xc120f400, 0xffa0fc03, sve_misc, 0, OP3 (SME_Zdnx4, SVE_ZnxN, SME_ZmxN_INDEX_22), OP_SVE_HH, F_OD(2), 0, 0),
> + SME2p3_INSN ("luti6", 0xc120fc00, 0xffa0fc00, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SVE_ZnxN, SME_ZmxN_INDEX_22), OP_SVE_HH, F_OD(2), 0, 0),
This mask should be 0xffa0fc0c.
These two luti6 variants don't need the "F_OD(4)":
> + SME2p3_INSN ("luti6", 0xc08a0000, 0xfffffc63, sve_misc, 0, OP3 (SME_Zdnx4, SME_ZT0, SME_Zn3_UNTYPED), OP_SVE_BB, F_OD(4), 0, 0),
> + SME2p3_INSN ("luti6", 0xc09a0000, 0xfffffc60, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_ZT0, SME_Zn3_UNTYPED), OP_SVE_BB, F_OD(4), 0, 0),
This mask should be 0xfffffc6c.
> + SME2p3_INSN ("luti6", 0xc0c84000, 0xfffffc00, sve_misc, 0, OP3 (SVE_Zd, SME_ZT0, SVE_Zn), OP_SVE_B, 0, 0, 0),
> +
> + /* SME2p3 / SME2p3 instructions. */
> + SVE2p3_SME2p3_INSN ("addqp", 0x04207800, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0, 0),
> + SVE2p3_SME2p3_INSN ("addsubp", 0x04207c00, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0, 0),
> + SVE2p3_SME2p3_INSN ("sabal", 0x4400d400, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, C_SCAN_MOVPRFX, 0),
> + SVE2p3_SME2p3_INSN ("scvtf", 0x650c3000, 0xff3ffc00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_HSD_BHS, 0, 0, 0),
> + SVE2p3_SME2p3_INSN ("scvtflt", 0x650c3800, 0xff3ffc00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_HSD_BHS, 0, 0, 0),
> + SVE2p3_SME2p3_INSN ("sdot", 0x44400000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_H_B, 0, C_SCAN_MOVPRFX, 0),
> + SVE2p3_SME2p3_INSN ("sdot", 0x44200000, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_22_INDEX), OP_SVE_VVV_H_B, 0, C_SCAN_MOVPRFX, 0),
> + SVE2p3_SME2p3_INSN ("subp", 0x4410a000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2),
The spec permits only an unpredicated movprfx before this instruction, which
breaks our existing assumption that all instructions with merging predication
that permit a movprfx will also permit a predicated movprfx. However, we
already have this issue with existing instructions like ADDP and FMAXP, so it's
fine to keep it this way in this patch.
> + SVE2p3_SME2p3_INSN ("uabal", 0x4400dc00, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, C_SCAN_MOVPRFX, 0),
> + SVE2p3_SME2p3_INSN ("ucvtf", 0x650c3400, 0xff3ffc00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_HSD_BHS, 0, 0, 0),
> + SVE2p3_SME2p3_INSN ("ucvtflt", 0x650c3c00, 0xff3ffc00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_HSD_BHS, 0, 0, 0),
> + SVE2p3_SME2p3_INSN ("udot", 0x44400400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_H_B, 0, C_SCAN_MOVPRFX, 0),
> + SVE2p3_SME2p3_INSN ("udot", 0x44200400, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_22_INDEX), OP_SVE_VVV_H_B, 0, C_SCAN_MOVPRFX, 0),
> + SVE2p3_SME2p3_INSN ("fcvtzsn", 0x650d3000, 0xff3ffc20, sve_size_hsd, 0, OP2 (SVE_Zd, SME_Znx2), OP_SVE_VV_BHS_HSD, 0, 0, 0),
> + SVE2p3_SME2p3_INSN ("fcvtzun", 0x650d3400, 0xff3ffc20, sve_size_hsd, 0, OP2 (SVE_Zd, SME_Znx2), OP_SVE_VV_BHS_HSD, 0, 0, 0),
> + SVE2p3_SME2p3_INSN ("luti6", 0x4560ac00, 0xff60fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_ZnxN, SVE_Zm1_23_INDEX), OP_SVE_HH, F_OD(2), 0, 0),
This should use OP_SVE_HHU.
> + SVE2p3_SME2p3_INSN ("sqrshrn", 0x45a82800, 0xfff8fc20, sve_misc, 0, OP3 (SVE_Zd, SME_Znx2, SME_SHRIMM3), OP_SVE_BHU, F_INVALID_IMM_SYMS_3, 0, 0),
> + SVE2p3_SME2p3_INSN ("sqrshrun", 0x45a80800, 0xfff8fc20, sve_misc, 0, OP3 (SVE_Zd, SME_Znx2, SME_SHRIMM3), OP_SVE_BHU, F_INVALID_IMM_SYMS_3, 0, 0),
> + SVE2p3_SME2p3_INSN ("sqshrn", 0x45a00000, 0xffe0fc20, sve_shift_tsz_hsd, 0, OP3 (SVE_Zd, SME_Znx2, SVE_SHRIMM_UNPRED_22), OP_SVE_VVU_BH_HS, F_INVALID_IMM_SYMS_3, 0, 0),
> + SVE2p3_SME2p3_INSN ("sqshrun", 0x45a02000, 0xffe0fc20, sve_shift_tsz_hsd, 0, OP3 (SVE_Zd, SME_Znx2, SVE_SHRIMM_UNPRED_22), OP_SVE_VVU_BH_HS, F_INVALID_IMM_SYMS_3, 0, 0),
> + SVE2p3_SME2p3_INSN ("uqrshrn", 0x45a83800, 0xfff8fc20, sve_misc, 0, OP3 (SVE_Zd, SME_Znx2, SME_SHRIMM3), OP_SVE_BHU, F_INVALID_IMM_SYMS_3, 0, 0),
> + SVE2p3_SME2p3_INSN ("uqshrn", 0x45a01000, 0xffe0fc20, sve_shift_tsz_hsd, 0, OP3 (SVE_Zd, SME_Znx2, SVE_SHRIMM_UNPRED_22), OP_SVE_VVU_BH_HS, F_INVALID_IMM_SYMS_3, 0, 0),
This perhaps ought to use an sve_shift_tsz_hs class, but I think this slight
misuse of the existing insn class name is fine, to avoid code duplication (and
I'd like to deduplicate this further in future).
To make this a bit clearer, could you add a comment in the relevant case in
aarch64_decode_variant_using_iclass, perhaps saying:
case sve_shift_tsz_hsd
+ /* This is also used for some instructions with hs variants only, in
+ which case FLD_SVE_sz will always be zero. */
>
> {0, 0, 0, 0, 0, 0, {}, {}, 0, 0, 0, NULL},
> };
> @@ -8305,6 +8366,8 @@ const struct aarch64_opcode aarch64_opcode_table[] =
> Y(SVE_REGLIST, sve_aligned_reglist, "SME_Zmx2_17_3", \
> 2 << OPD_F_OD_LSB, F(FLD_CONST_1, FLD_SME_Zm17_3, FLD_CONST_0), \
> "a list of SVE vector registers") \
> + Y(SVE_REGLIST, sve_reglist_index, "SME_ZmxN_INDEX_22", 0, \
> + F(FLD_SVE_Zm_16, FLD_imm1_22), "a list of SVE vector registers with index") \
> Y(SVE_REGLIST, sve_aligned_reglist, "SME_Zmx2", 2 << OPD_F_OD_LSB, \
> F(FLD_SME_Zm2, FLD_CONST_0), "a list of SVE vector registers") \
> Y(SVE_REGLIST, sve_aligned_reglist, "SME_Zmx4", 4 << OPD_F_OD_LSB, \
> @@ -8316,6 +8379,8 @@ const struct aarch64_opcode aarch64_opcode_table[] =
> "a list of SVE vector registers") \
> Y(SVE_REGLIST, sve_aligned_reglist, "SME_Znx4", 4 << OPD_F_OD_LSB, \
> F(FLD_SME_Zn4, FLD_CONST_00), "a list of SVE vector registers") \
> + Y(SVE_REGLIST, sve_aligned_reglist_untyped, "SME_Zn3_UNTYPED", 3 << OPD_F_OD_LSB, \
> + F(FLD_SME_Zn4), "a list of untyped SVE vector registers") \
How about calling this SME_Zn7x3_UNTYPED?
For the inserter/extractor - firstly, "aligned" is wrong, because that is used
to mean that the start register number is a multiple of 2 or 4 (according to
the number of registers).
However, I don't think we actually need a new inserter/extractor (although that
only changed recently). Instead we can tweak sve_reglist to accept multiple
fields and then use that (with the fixed bits represented by FLD_CONST_00).
See 6c8bca7bc224fcce for a similar change (this one should be much simpler than
that).
> Y(SVE_REGLIST, sve_strided_reglist, "SME_Ztx2_STRIDED", \
> 2 << OPD_F_OD_LSB, F(FLD_SME_ZtT, FLD_SME_Zt3), \
> "a list of SVE vector registers") \
> @@ -8384,6 +8449,8 @@ const struct aarch64_opcode aarch64_opcode_table[] =
> Y(SVE_REG, sme_pred_reg_with_index, "SME_PnT_Wm_imm", 0, \
> F(FLD_SME_Rm,FLD_SVE_Pn,FLD_SME_i1,FLD_SME_tszh,FLD_SME_tszl), \
> "Source scalable predicate register with index ") \
> + Y(IMMEDIATE, plain_shrimm, "SME_SHRIMM3", 0, F(FLD_SVE_imm3), \
> + "a shift-right immediate operand") \
> Y(IMMEDIATE, plain_shrimm, "SME_SHRIMM4", 0, F(FLD_SVE_imm4), \
> "a shift-right immediate operand") \
> Y(IMMEDIATE, sve_shrimm, "SME_SHRIMM5", 1 << OPD_F_OD_LSB, \
> --
> 2.43.0
>
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