[PATCH] aarch64: Add system registers for Virtual Tagging Extension

[Yury Khrustalev]

 - HCRXMASK_EL2 Extended Hypervisor Configuration Masking Register
 - SCR2_EL3     Secure Configuration Register

---

Passes regression on AArch64. OK for trunk?
Base commit: 42a76e2e3cc

---
 gas/config/tc-aarch64.c                                     | 2 ++
 .../gas/aarch64/sysreg/sysregs_with_no_restrictions.d       | 4 ++++
 .../gas/aarch64/sysreg/sysregs_with_no_restrictions.s       | 6 ++++++
 .../gas/aarch64/sysreg/sysregs_with_restrictions.d          | 4 ++++
 .../gas/aarch64/sysreg/sysregs_with_restrictions.s          | 6 ++++++
 include/opcode/aarch64.h                                    | 4 ++++
 opcodes/aarch64-sys-regs.def                                | 2 ++
 7 files changed, 28 insertions(+)

diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 0ca54c3bd40..df6c9b7147c 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -10905,6 +10905,8 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
   {"ssve-fexpa",	AARCH64_FEATURE (SSVE_FEXPA), AARCH64_FEATURE (SME2)},
   {"sme-tmop",		AARCH64_FEATURE (SME_TMOP), AARCH64_FEATURE (SME2)},
   {"sme-mop4",		AARCH64_FEATURE (SME_MOP4), AARCH64_FEATURE (SME2)},
+  {"srmask2",		AARCH64_FEATURE (SRMASK2), AARCH64_NO_FEATURES},
+  {"scr2",		AARCH64_FEATURE (SCR2), AARCH64_NO_FEATURES},
   {NULL,		AARCH64_NO_FEATURES, AARCH64_NO_FEATURES},
 };
 
diff --git a/gas/testsuite/gas/aarch64/sysreg/sysregs_with_no_restrictions.d b/gas/testsuite/gas/aarch64/sysreg/sysregs_with_no_restrictions.d
index 68ff860aa73..800865094c0 100644
--- a/gas/testsuite/gas/aarch64/sysreg/sysregs_with_no_restrictions.d
+++ b/gas/testsuite/gas/aarch64/sysreg/sysregs_with_no_restrictions.d
@@ -94,3 +94,7 @@
 .*:	d57c2002 	mrrs	x2, x3, ttbr0_el2
 .*:	d55c2022 	msrr	ttbr1_el2, x2, x3
 .*:	d57c2022 	mrrs	x2, x3, ttbr1_el2
+.*:	d51c15e0 	msr	hcrxmask_el2, x0
+.*:	d53c15e0 	mrs	x0, hcrxmask_el2
+.*:	d51e1240 	msr	scr2_el3, x0
+.*:	d53e1240 	mrs	x0, scr2_el3
diff --git a/gas/testsuite/gas/aarch64/sysreg/sysregs_with_no_restrictions.s b/gas/testsuite/gas/aarch64/sysreg/sysregs_with_no_restrictions.s
index 3619951fb3c..821720c2710 100644
--- a/gas/testsuite/gas/aarch64/sysreg/sysregs_with_no_restrictions.s
+++ b/gas/testsuite/gas/aarch64/sysreg/sysregs_with_no_restrictions.s
@@ -55,3 +55,9 @@
 	rw_sys_reg_128 rcwmask_el1 xreg1=x2 xreg2=x3  // THE
 	rw_sys_reg_128 ttbr0_el2 xreg1=x2 xreg2=x3  // V8A
 	rw_sys_reg_128 ttbr1_el2 xreg1=x2 xreg2=x3  // V8A && V8_1A
+
+	.arch_extension srmask2 // For the srmask2 instructions.
+	rw_sys_reg hcrxmask_el2 // HCRXMASK_EL2
+
+	.arch_extension scr2 // For the scr2 instructions.
+	rw_sys_reg scr2_el3 // SCR2_EL3
diff --git a/gas/testsuite/gas/aarch64/sysreg/sysregs_with_restrictions.d b/gas/testsuite/gas/aarch64/sysreg/sysregs_with_restrictions.d
index dd7c7a5dbf6..9eb830ee80e 100644
--- a/gas/testsuite/gas/aarch64/sysreg/sysregs_with_restrictions.d
+++ b/gas/testsuite/gas/aarch64/sysreg/sysregs_with_restrictions.d
@@ -94,3 +94,7 @@
 .*:	d57c2002 	mrrs	x2, x3, ttbr0_el2
 .*:	d55c2022 	msrr	ttbr1_el2, x2, x3
 .*:	d57c2022 	mrrs	x2, x3, ttbr1_el2
+.*:	d51c15e0 	msr	hcrxmask_el2, x0
+.*:	d53c15e0 	mrs	x0, hcrxmask_el2
+.*:	d51e1240 	msr	scr2_el3, x0
+.*:	d53e1240 	mrs	x0, scr2_el3
diff --git a/gas/testsuite/gas/aarch64/sysreg/sysregs_with_restrictions.s b/gas/testsuite/gas/aarch64/sysreg/sysregs_with_restrictions.s
index 2102ea8bdcc..d91a7567e09 100644
--- a/gas/testsuite/gas/aarch64/sysreg/sysregs_with_restrictions.s
+++ b/gas/testsuite/gas/aarch64/sysreg/sysregs_with_restrictions.s
@@ -93,3 +93,9 @@
 	rw_sys_reg_128 ttbr0_el2 xreg1=x2 xreg2=x3  // V8A
 	.arch armv8.1-a+d128
 	rw_sys_reg_128 ttbr1_el2 xreg1=x2 xreg2=x3  // V8A && V8_1A
+
+	.arch_extension srmask2 // For the srmask2 instructions.
+	rw_sys_reg hcrxmask_el2 // HCRXMASK_EL2
+
+	.arch_extension scr2 // For the scr2 instructions.
+	rw_sys_reg scr2_el3 // SCR2_EL3
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index e65b61c3f9c..f2b76378e6c 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -263,6 +263,10 @@ enum aarch64_feature_bit {
   AARCH64_FEATURE_SME_TMOP,
   /* SME MOP4 instructions.  */
   AARCH64_FEATURE_SME_MOP4,
+  /* Bitwise Write Masks for Hypervisor Configuration Registers.  */
+  AARCH64_FEATURE_SRMASK2,
+  /* Extension to SCR_EL3.  */
+  AARCH64_FEATURE_SCR2,
 
   /* Virtual features.  These are used to gate instructions that are enabled
      by either of two (or more) sets of command line flags.  */
diff --git a/opcodes/aarch64-sys-regs.def b/opcodes/aarch64-sys-regs.def
index 17c1c9d0c01..2665ad5a4bd 100644
--- a/opcodes/aarch64-sys-regs.def
+++ b/opcodes/aarch64-sys-regs.def
@@ -444,6 +444,7 @@
   SYSREG ("hafgrtr_el2",	CPENC (3,4,3,1,6),	0,		AARCH64_FEATURE (V8_5A)) /* AMUv1 && FGT */
   SYSREG ("hcr_el2",		CPENC (3,4,1,1,0),	0,		AARCH64_NO_FEATURES)
   SYSREG ("hcrx_el2",		CPENC (3,4,1,2,2),	0,		AARCH64_FEATURE (V8_6A)) /* HCX */
+  SYSREG ("hcrxmask_el2",	CPENC (3,4,1,5,7),	0,		AARCH64_FEATURE (SRMASK2))
   SYSREG ("hdbssbr_el2",	CPENC (3,4,2,3,2),	0,		AARCH64_FEATURE (V9_4A)) /* HDBSS */
   SYSREG ("hdbssprod_el2",	CPENC (3,4,2,3,3),	0,		AARCH64_FEATURE (V9_4A)) /* HDBSS */
   SYSREG ("hdfgrtr_el2",	CPENC (3,4,3,1,4),	0,		AARCH64_FEATURE (V8_5A)) /* FGT */
@@ -942,6 +943,7 @@
   SYSREG ("s2pir_el2",		CPENC (3,4,10,2,5),	0,		AARCH64_FEATURE (V8_8A)) /* S2PIE */
   SYSREG ("s2por_el1",		CPENC (3,0,10,2,5),	0,		AARCH64_FEATURE (V8_8A)) /* S2POE */
   SYSREG ("scr_el3",		CPENC (3,6,1,1,0),	0,		AARCH64_NO_FEATURES)
+  SYSREG ("scr2_el3",		CPENC (3,6,1,2,2),	0,		AARCH64_FEATURE (SCR2))
   SYSREG ("sctlr_el1",		CPENC (3,0,1,0,0),	0,		AARCH64_NO_FEATURES)
   SYSREG ("sctlr_el12",		CPENC (3,5,1,0,0),	0,		AARCH64_NO_FEATURES)
   SYSREG ("sctlr_el2",		CPENC (3,4,1,0,0),	0,		AARCH64_NO_FEATURES)
-- 
2.47.3