[PATCH v2] PowerPC: Support for eTCE (RFC02662)

Surya Kumari Jangala jskumari@linux.ibm.com
Wed Nov 19 12:40:49 GMT 2025


Hi Abhay,

On 14/11/25 2:42 pm, Abhay Kandpal wrote:
> opcodes/
>     * ppc-opc.c (X_TLBP_MASK, X_TLBIO_MASK): New macros.
>     (powerpc_opcodes): Add tlbiep, tlbieio, tlbsyncio,
>     ptesyncio.
> 
> gas/
>     * testsuite/gas/ppc/future.s: New test.
>     * testsuite/gas/ppc/future.d: Likewise.
> ---
> This patch is reg tested.
> Changes from v1->v2:
> <Incorporated comments in latest trunc>
> <Removed tlbiep extended mnemonic entry>
> 
>  gas/testsuite/gas/ppc/future.d |  5 +++++
>  gas/testsuite/gas/ppc/future.s |  5 +++++
>  opcodes/ppc-opc.c              | 13 +++++++++++++
>  3 files changed, 23 insertions(+)
> 
> diff --git a/gas/testsuite/gas/ppc/future.d b/gas/testsuite/gas/ppc/future.d
> index efb3ee8428d..629cae637f1 100644
> --- a/gas/testsuite/gas/ppc/future.d
> +++ b/gas/testsuite/gas/ppc/future.d
> @@ -109,4 +109,9 @@ Disassembly of section \.text:
>  .*:	(4c 06 00 7c|7c 00 06 4c) 	ccmclean
>  .*:	(cc 06 00 7c|7c 00 06 cc) 	ccmrl
>  .*:	(26 22 40 7c|7c 40 22 26) 	mtlpl   r4,r2
> +.*:	(64 10 8f 7c|7c 8f 10 64) 	tlbiep  r2,r4,3,1,1
> +.*:	(64 10 60 7c|7c 60 10 64) 	tlbiep  r2,r3
> +.*:	(24 38 c8 7c|7c c8 38 24) 	tlbieio r7,r6,2
> +.*:	(68 04 20 7d|7d 20 04 68) 	tlbsyncio r9
> +.*:	(a8 04 a0 7c|7c a0 04 a8) 	ptesyncio r5
>  #pass
> diff --git a/gas/testsuite/gas/ppc/future.s b/gas/testsuite/gas/ppc/future.s
> index e66465a7418..c7b42688a40 100644
> --- a/gas/testsuite/gas/ppc/future.s
> +++ b/gas/testsuite/gas/ppc/future.s
> @@ -83,4 +83,9 @@ _start:
>  	ccmclean
>  	ccmrl
>  	mtlpl 4, 2
> +	tlbiep 2, 4, 3, 1, 1
> +	tlbiep 2, 3
> +	tlbieio 7, 6, 2
> +	tlbsyncio 9
> +	ptesyncio 5
>  
> diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
> index 867801a83d2..85b2cb5a8de 100644
> --- a/opcodes/ppc-opc.c
> +++ b/opcodes/ppc-opc.c
> @@ -4628,6 +4628,12 @@ const unsigned int num_powerpc_operands = ARRAY_SIZE (powerpc_operands);
>     field.  */
>  #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
>  
> +/* The mask of TLB invalidate Entry for Processor */
> +#define X_TLBP_MASK (X_MASK | (1<<20))

The name X_TLBP_MASK does not follow the general naming conventions
for masks. Take a look at other masks such as XX2UIM_MASK, XWC_MASK etc.
Can you try coming up with a different name?

> +
> +/* The mask of TLB invalidate Entry for I/O device */> +#define X_TLBIO_MASK (X_TLBP_MASK | (3<<16))
> +
>  /* An X form wait instruction with everything filled in except the WC
>     and PL fields.  */
>  #define XWCPL_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | (3 << 18) | RB_MASK)
> @@ -7238,6 +7244,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
>  {"iseleq",	XISEL(31,15,2),	X_MASK,	     PPCISEL,	EXT,		{RT, RA0, RB}},
>  {"isel",	XISEL(31,15,0), XISEL_MASK, PPCISEL|TITAN, 0,		{RT, RA0, RB, BC}},
>  
> +{"tlbieio",	X(31,18), 	X_TLBIO_MASK, FUTURE,	0,		{RB, RS, RIC}},

Have the above entry on a separate line.


-Surya

>  {"tlbilxlpid",	XTO(31,18,0),	XTO_MASK, E500MC|PPCA2,	0,		{0}},
>  {"tlbilxpid",	XTO(31,18,1),	XTO_MASK, E500MC|PPCA2,	0,		{0}},
>  {"tlbilxva",	XTO(31,18,3),	XTO_MASK, E500MC|PPCA2,	0,		{RA0, RB}},
> @@ -7297,6 +7304,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
>  
>  {"mviwsplt",	X(31,46),	X_MASK,	     E6500,	0,		{VD, RA, RB}},
>  
> +{"tlbiep",	X(31,50),	X_TLBP_MASK, FUTURE,	TITAN,		{RB, RS, RIC, PRS, X_R}},
> +
>  {"lvewx",	X(31,71),	X_MASK,	     PPCVEC,	0,		{VD, RA0, RB}},
>  
>  {"addg6s",	XO(31,74,0,0),	XO_MASK,     POWER6,	0,		{RT, RA, RB}},
> @@ -8605,6 +8614,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
>  
>  {"lxvrll",	X(31,557),	XX1_MASK,    PPCVSXF,	0,		{XT6, RA0, RB}},
>  
> +{"tlbsyncio",	X(31,564),	XRARB_MASK,  FUTURE,	0,		{RS}},
> +
>  {"tlbsync",	X(31,566),	0xffffffff,  PPC,	0,		{0}},
>  
>  {"lfsux",	X(31,567),	X_MASK,	     COM,	PPCEFS,		{FRT, RAS, RB}},
> @@ -8630,6 +8641,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
>  
>  {"mfsr",	X(31,595), XRB_MASK|(1<<20), COM,	NON32,		{RT, SR}},
>  
> +{"ptesyncio",	X(31,596),	XRARB_MASK,  FUTURE,	0,		{RS}},
> +
>  {"lswi",	X(31,597),	X_MASK,	     PPCCOM,	E500|E500MC,	{RT, RAX, NBI}},
>  {"lsi",		X(31,597),	X_MASK,	     PWRCOM,	0,		{RT, RA0, NB}},
>  



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