RISC-V GNU Toolchain - assembler assembles `clz` instruction incorrectly

[Averill, Charles Charles]

Upon re-implementing "vTaskSwitchContext" from FreeRTOS in RISC-V (implementation attached), the "clz a5, a5" instruction is incorrectly assembled as 0x60079793, when the RISC-V Zbb extension specification (https://five-embeddev.com/riscv-bitmanip/1.0.0/bitmanip.html#insns-clz) specifies that it should be 0x600a9a93.

Version:

GNU assembler (xPack GNU RISC-V Embedded GCC x86_64) 2.43.1
Copyright (C) 2024 Free Software Foundation, Inc.
This program is free software; you may redistribute it under the terms of
the GNU General Public License version 3 or later.
This program has absolutely no warranty.
This assembler was configured for a target of `riscv-none-elf'.

I didn't compile these tools, I downloaded them here: https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack

I've also attached the two makefiles used to compile this project.

Thank you,

Charles Averill
UTD Software Languages Security Lab
Dartmouth Trust Lab
UTD Computer Security Group
https://www.charles.systems/
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