[PATCH] Add AMD znver6 processor support

[Jan Beulich]

On 11.11.2025 11:07, Jan Beulich wrote:
> On 11.11.2025 11:00, Jan Beulich wrote:
>> On 07.11.2025 10:34, Umesh Kalvakuntla wrote:
>>> AVX512 Bit Manipulation Instructions
>>> ==============================
>>
>> Btw, is this really the canonical expansion of AVX512-BMM? Not e.g. "AVX512
>> Bitmap Manipulation Instructions", thus explaining the 2nd M in the acronym?
>> While at the same time distinguishing from AVX512-VBMI{,2}?
>>> @@ -208,6 +210,8 @@ static const dependency isa_dependencies[] =
>>>      "AVX512BW" },
>>>    { "AVX512_VP2INTERSECT",
>>>      "AVX512F" },
>>> +  { "AVX512_BMM",
>>> +    "AVX512F" },
>>
>> I'm not convinced of this, btw. Like e.g. ...
>>
>>>    { "AVX512_BF16",
>>>      "AVX512BW" },
>> ... this, making AVX512BW the prereq would seem more logical to me. AVX512F
>> does not offer any "regular" insns handling operands with 8- or 16-bit element
>> size ("regular" meaning: leaving aside the to/from PH conversion insns as well
>> as the size-/zero-extending and narrowing moves, i.e. ones where one of source
>> or destination still have 32- or 64-bit element size, which isn't the case for
>> AVX512-BMM).
> 
> Oh, and requiring wider than 16-bit mask registers (I assume masking is byte-
> granular for VBITREV).

And AVX512VL likely is a prereq, too?

Jan