[PATCH] Add AMD znver6 processor support

[Jiang, Haochen]

> From: Jan Beulich <jbeulich@suse.com>
> Sent: Friday, November 7, 2025 9:20 PM
> 
> On 07.11.2025 10:34, Umesh Kalvakuntla wrote:
> >
> > diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
> > index 1cf3d5d4688..f9e4044a3db 100644
> > --- a/opcodes/i386-opc.tbl
> > +++ b/opcodes/i386-opc.tbl
> > @@ -3144,6 +3144,14 @@ vcvtneps2bf16<Vxy>, 0xf372, AVX_NE_CONVERT, Modrm|<Vxy:vex>|Space0F38|VexW0|NoSu
> > 
> > // AVX-NE-CONVERT instructions end.
> > 
> > +// AVX512_BMM instructions.
> > +
> > +vbmacor16x16x16, 0x80, AVX512_BMM, Modrm|EVexDYN|VexW0|Src1VVVV|Map6|NoSuf, { RegYMM|RegZMM|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM }
> > +vbmacxor16x16x16, 0x80, AVX512_BMM, Modrm|EVexDYN|VexW1|Src1VVVV|Map6|NoSuf, { RegYMM|RegZMM|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM }
> > +vbitrev, 0x81, AVX512_BMM, Modrm|EVexDYN|VexW0|Masking|Map6|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }

Other than Jan's review, I have one more comment here.

We may need CheckOperandSize and Disp8Memshift (probably
VL is correct here but we need doc to confirm) attribute to be
added here.

BTW, I don't know why I could not find the original patch email
in my mailbox. It might be blocked due to too large size.

Thx,
Haochen