[PATCH v3] gdb/record: Support fense.tso, zicond, bitmanip, sinval and zihintntl in RISC-V

Fri Nov 7 10:49:05 GMT 2025

Hi!
I tried to avoid adding new MATCH and MASK macros and now patch looks
like this (in total 25 new lines):

> +#define MATCH_BCLRI_RV32 0x48001013
> +#define MASK_BCLRI_RV32 0xfe00707f
> +#define MATCH_BEXTI_RV32 0x48005013
> +#define MASK_BEXTI_RV32 0xfe00707f
> +#define MATCH_BINVI_RV32 0x68001013
> +#define MASK_BINVI_RV32 0xfe00707f
> +#define MATCH_BSETI_RV32 0x28001013
> +#define MASK_BSETI_RV32 0xfe00707f
> +#define MATCH_RORI_RV32 0x60005013
> +#define MASK_RORI_RV32 0xfe00707f
> DECLARE_INSN(rorw, MATCH_RORW, MASK_RORW)
> DECLARE_INSN(roriw, MATCH_RORIW, MASK_RORIW)
> +DECLARE_INSN(fence_tso, MATCH_FENCE_TSO, MASK_FENCE_TSO)q
> +DECLARE_INSN(rev8, MATCH_GREVI|MATCH_SHAMT_REV8_64, MASK_GREVI|MASK_SHAMT)
> +DECLARE_INSN(zext_h, MATCH_PACKW, MASK_PACKW|MASK_RS2)
> +DECLARE_INSN(zip, MATCH_SHFLI|MATCH_SHAMT_ZIP_32, MASK_SHFLI|MASK_SHAMT)
> +DECLARE_INSN(unzip, MATCH_UNSHFLI|MATCH_SHAMT_ZIP_32, MASK_UNSHFLI|MASK_SHAMT)
> +DECLARE_INSN(orc_b, MATCH_GORCI|MATCH_SHAMT_ORC_B, MASK_GORCI | MASK_SHAMT)
> +DECLARE_INSN(brev8, MATCH_GREVI|MATCH_SHAMT_BREV8, MASK_GREVI|MASK_SHAMT)
> +DECLARE_INSN(rev8_rv32, MATCH_GREVI|MATCH_SHAMT_REV8_32, MASK_GREVI|MASK_SHAMT)
> +DECLARE_INSN(rori_rv32, MATCH_RORI_RV32, MASK_RORI_RV32)
> +DECLARE_INSN(zext_h_rv32, MATCH_PACK, MASK_PACK|MASK_RS2)
> +DECLARE_INSN(bclri_rv32, MATCH_BCLRI_RV32, MASK_BCLRI_RV32)
> +DECLARE_INSN(bexti_rv32, MATCH_BEXTI_RV32, MASK_BEXTI_RV32)
> +DECLARE_INSN(binvi_rv32, MATCH_BINVI_RV32, MASK_BINVI_RV32)
> +DECLARE_INSN(bseti_rv32, MATCH_BSETI_RV32, MASK_BSETI_RV32)
> +DECLARE_INSN(c_sext_w, MATCH_C_ADDIW, MASK_C_ADDIW|MASK_RVC_IMM)

but unfortunately I came across a mistake that now it doesn't compile,
because such macroses:

#define MASK_RS1 (OP_MASK_RS1 << OP_SH_RS1)
#define MASK_RS2 (OP_MASK_RS2 << OP_SH_RS2)
#define MASK_RD (OP_MASK_RD << OP_SH_RD)
#define MASK_CRS2 (OP_MASK_CRS2 << OP_SH_CRS2)
#define MASK_CRS2S (OP_MASK_CRS2S << OP_SH_CRS2S)
#define MASK_IMM ENCODE_ITYPE_IMM (-1U)
#define MASK_RVC_IMM ENCODE_CITYPE_IMM (-1U)
#define MASK_UIMM ENCODE_UTYPE_IMM (-1U)
#define MASK_RM (OP_MASK_RM << OP_SH_RM)
#define MASK_PRED (OP_MASK_PRED << OP_SH_PRED)
#define MASK_SUCC (OP_MASK_SUCC << OP_SH_SUCC)
#define MASK_AQ (OP_MASK_AQ << OP_SH_AQ)
#define MASK_RL (OP_MASK_RL << OP_SH_RL)
#define MASK_AQRL (MASK_AQ | MASK_RL)
#define MASK_SHAMT (OP_MASK_SHAMT << OP_SH_SHAMT)
#define MATCH_SHAMT_REV8_32 (0b11000 << OP_SH_SHAMT)
#define MATCH_SHAMT_REV8_64 (0b111000 << OP_SH_SHAMT)
#define MATCH_SHAMT_BREV8 (0b00111 << OP_SH_SHAMT)
#define MATCH_SHAMT_ZIP_32 (0b1111 << OP_SH_SHAMT)
#define MATCH_SHAMT_ORC_B (0b00111 << OP_SH_SHAMT)
#define MASK_VD (OP_MASK_VD << OP_SH_VD)
#define MASK_VS1 (OP_MASK_VS1 << OP_SH_VS1)
#define MASK_VS2 (OP_MASK_VS2 << OP_SH_VS2)
#define MASK_VMASK (OP_MASK_VMASK << OP_SH_VMASK)
/* Vendor-specific (CORE-V) masks. */
#define MASK_CV_IS3_UIMM5 ENCODE_CV_IS3_UIMM5 (-1U)

are defined only in riscv-opc.c. So probably the simplest variant for
now is either just add these new instructions and macroses as I
proposed in the beginning either put these macroses in riscv-opc.h.
What do you think?

On Fri, Nov 7, 2025 at 4:01 AM Nelson Chu <nelson@rivosinc.com> wrote:
>
> We haven't used riscv-opcodes to generate these macros for a long time in binutils, probably because of the license issue which I forgot...  However, if I remember correctly, these codes in opcodes/riscv-opc.c are used to simplify the number of macros defined, so I would like to keep the existing code.  If you are adding new instructions with new defined macros, then it's all Okay.
>
> Thanks
> Nelson
>
> On Thu, Nov 6, 2025 at 1:36 AM Timur Golubovich <timurgol007@gmail.com> wrote:
>>
>> > so is it possible to apply these defined stuffs into the missing DECLARE_INSN macros, rather than define a bunch of extra new ones?
>>
>> Well, I can do this, but won't it be better to change
>> MATCH_UNSHFLI|MATCH_SHAMT_ZIP_32 to MATCH_UNZIP in
>> opcodes/riscv-opc.c? Because the changes that I made in this patch
>> were generated by riscv-opcodes, and I absolutely don't understand why
>> it was necessary to build this MATCH using |.
>>
>> On Tue, Nov 4, 2025 at 6:14 AM Nelson Chu <nelson@rivosinc.com> wrote:
>> >
>> >
>> >
>> > On Tue, Nov 4, 2025 at 5:37 AM Timur Golubovich <timurgol007@gmail.com> wrote:
>> >>
>> >> ---------- Forwarded message ---------
>> >> From: timurgol007 <timurgol007@gmail.com>
>> >> Date: Sat, Nov 1, 2025 at 2:28 PM
>> >> Subject: [PATCH v3] gdb/record: Support fense.tso, zicond, bitmanip,
>> >> sinval and zihintntl in RISC-V
>> >> To: <tom@tromey.com>, <guinevere@redhat.com>, <aburgess@redhat.com>,
>> >> <gdb-patches@sourceware.org>
>> >> Cc: timurgol007 <timurgol007@gmail.com>
>> >>
>> >>
>> >> Added record-full support for these extensions. As some opcodes were
>> >> missed in riscv-opc.h, added them there using riscv-opcodes repo.
>> >
>> >
>> > I think I can just review the riscv-opc.h parts.
>> >
>> >>
>> >> ---
>> >>  gdb/riscv-tdep.c           | 83 ++++++++++++++++++++++++++++++++++++--
>> >>  include/opcode/riscv-opc.h | 43 ++++++++++++++++++++
>> >>  2 files changed, 123 insertions(+), 3 deletions(-)
>> >>
>> >> diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
>> >> index 1c649628390..6a5d54b1615 100644
>> >> --- a/include/opcode/riscv-opc.h
>> >> +++ b/include/opcode/riscv-opc.h
>> >> @@ -579,6 +579,32 @@
>> >>  #define MASK_RORW  0xfe00707f
>> >>  #define MATCH_RORIW 0x6000501b
>> >>  #define MASK_RORIW  0xfe00707f
>> >> +#define MATCH_BCLRI_RV32 0x48001013
>> >> +#define MASK_BCLRI_RV32 0xfe00707f
>> >> +#define MATCH_BEXTI_RV32 0x48005013
>> >> +#define MASK_BEXTI_RV32 0xfe00707f
>> >> +#define MATCH_BINVI_RV32 0x68001013
>> >> +#define MASK_BINVI_RV32 0xfe00707f
>> >> +#define MATCH_BREV8 0x68705013
>> >> +#define MASK_BREV8 0xfff0707f
>> >> +#define MATCH_BSETI_RV32 0x28001013
>> >> +#define MASK_BSETI_RV32 0xfe00707f
>> >> +#define MATCH_ORC_B 0x28705013
>> >> +#define MASK_ORC_B 0xfff0707f
>> >> +#define MATCH_REV8 0x6b805013
>> >> +#define MASK_REV8 0xfff0707f
>> >> +#define MATCH_REV8_RV32 0x69805013
>> >> +#define MASK_REV8_RV32 0xfff0707f
>> >> +#define MATCH_RORI_RV32 0x60005013
>> >> +#define MASK_RORI_RV32 0xfe00707f
>> >> +#define MATCH_UNZIP 0x8f05013
>> >> +#define MASK_UNZIP 0xfff0707f
>> >> +#define MATCH_ZEXT_H 0x800403b
>> >> +#define MASK_ZEXT_H 0xfff0707f
>> >> +#define MATCH_ZEXT_H_RV32 0x8004033
>> >> +#define MASK_ZEXT_H_RV32 0xfff0707f
>> >> +#define MATCH_ZIP 0x8f01013
>> >> +#define MASK_ZIP 0xfff0707f
>> >>  #define MATCH_SH1ADD 0x20002033
>> >>  #define MASK_SH1ADD  0xfe00707f
>> >>  #define MATCH_SH2ADD 0x20004033
>> >> @@ -2269,6 +2295,8 @@
>> >>  #define MASK_C_SEXT_H 0xfc7f
>> >>  #define MATCH_C_ZEXT_W 0x9c71
>> >>  #define MASK_C_ZEXT_W 0xfc7f
>> >> +#define MATCH_C_SEXT_W 0x2001
>> >> +#define MASK_C_SEXT_W 0xf07f
>> >>  #define MATCH_C_NOT 0x9c75
>> >>  #define MASK_C_NOT 0xfc7f
>> >>  #define MATCH_C_MUL 0x9c41
>> >> @@ -4370,6 +4398,7 @@ DECLARE_INSN(sd, MATCH_SD, MASK_SD)
>> >>  DECLARE_INSN(pause, MATCH_PAUSE, MASK_PAUSE)
>> >>  DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE)
>> >>  DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I)
>> >> +DECLARE_INSN(fence_tso, MATCH_FENCE_TSO, MASK_FENCE_TSO)
>> >>  DECLARE_INSN(mul, MATCH_MUL, MASK_MUL)
>> >>  DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH)
>> >>  DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU)
>> >> @@ -4570,6 +4599,19 @@ DECLARE_INSN(cpopw, MATCH_CPOPW, MASK_CPOPW)
>> >>  DECLARE_INSN(rolw, MATCH_ROLW, MASK_ROLW)
>> >>  DECLARE_INSN(rorw, MATCH_RORW, MASK_RORW)
>> >>  DECLARE_INSN(roriw, MATCH_RORIW, MASK_RORIW)
>> >> +DECLARE_INSN(bclri_rv32, MATCH_BCLRI_RV32, MASK_BCLRI_RV32)
>> >> +DECLARE_INSN(bexti_rv32, MATCH_BEXTI_RV32, MASK_BEXTI_RV32)
>> >> +DECLARE_INSN(binvi_rv32, MATCH_BINVI_RV32, MASK_BINVI_RV32)
>> >> +DECLARE_INSN(brev8, MATCH_BREV8, MASK_BREV8)
>> >> +DECLARE_INSN(bseti_rv32, MATCH_BSETI_RV32, MASK_BSETI_RV32)
>> >> +DECLARE_INSN(orc_b, MATCH_ORC_B, MASK_ORC_B)
>> >> +DECLARE_INSN(rev8, MATCH_REV8, MASK_REV8)
>> >> +DECLARE_INSN(rev8_rv32, MATCH_REV8_RV32, MASK_REV8_RV32)
>> >> +DECLARE_INSN(rori_rv32, MATCH_RORI_RV32, MASK_RORI_RV32)
>> >> +DECLARE_INSN(unzip, MATCH_UNZIP, MASK_UNZIP)
>> >> +DECLARE_INSN(zext_h, MATCH_ZEXT_H, MASK_ZEXT_H)
>> >> +DECLARE_INSN(zext_h_rv32, MATCH_ZEXT_H_RV32, MASK_ZEXT_H_RV32)
>> >> +DECLARE_INSN(zip, MATCH_ZIP, MASK_ZIP)
>> >>  DECLARE_INSN(sh1add, MATCH_SH1ADD, MASK_SH1ADD)
>> >>  DECLARE_INSN(sh2add, MATCH_SH2ADD, MASK_SH2ADD)
>> >>  DECLARE_INSN(sh3add, MATCH_SH3ADD, MASK_SH3ADD)
>> >> @@ -4803,6 +4845,7 @@ DECLARE_INSN(vsm3me_vv, MATCH_VSM3ME_VV, MASK_VSM3ME_VV)
>> >>  /* Zcb instructions.  */
>> >>  DECLARE_INSN(c_sext_b, MATCH_C_SEXT_B, MASK_C_SEXT_B)
>> >>  DECLARE_INSN(c_sext_h, MATCH_C_SEXT_H, MASK_C_SEXT_H)
>> >> +DECLARE_INSN(c_sext_w, MATCH_C_SEXT_W, MASK_C_SEXT_W)
>> >>  DECLARE_INSN(c_zext_b, MATCH_C_ZEXT_B, MASK_C_ZEXT_B)
>> >>  DECLARE_INSN(c_zext_h, MATCH_C_ZEXT_H, MASK_C_ZEXT_H)
>> >>  DECLARE_INSN(c_zext_w, MATCH_C_ZEXT_W, MASK_C_ZEXT_W)
>> >
>> >
>> > I haven't check the whole instruction, but at least for something like unzip, according to the opcode table, it's match and mask functions are,
>> > MATCH_UNSHFLI|MATCH_SHAMT_ZIP_32 and MASK_UNSHFLI|MASK_SHAMT, so is it possible to apply these defined stuffs into the missing DECLARE_INSN macros, rather than define a bunch of extra new ones?
>> >
>> > Thanks
>> > Nelson