[PATCH v1] PowerPC: Support for eTCE (RFC02662)

[Abhay Kandpal]

opcodes/
    * ppc-opc.c (X_TLBP_MASK, X_TLBIO_MASK): New macros.
    (powerpc_opcodes): Add tlbiep, tlbiep(extended),
    tlbieio, tlbsyncio, ptesyncio.

gas/
    * testsuite/gas/ppc/future.s: New test.
    * testsuite/gas/ppc/future.d: Likewise.
---
This patch is reg tested.

 gas/testsuite/gas/ppc/future.d |  5 +++++
 gas/testsuite/gas/ppc/future.s |  5 +++++
 opcodes/ppc-opc.c              | 14 ++++++++++++++
 3 files changed, 24 insertions(+)

diff --git a/gas/testsuite/gas/ppc/future.d b/gas/testsuite/gas/ppc/future.d
index 19e96fac345..f3b742ad850 100644
--- a/gas/testsuite/gas/ppc/future.d
+++ b/gas/testsuite/gas/ppc/future.d
@@ -106,4 +106,9 @@ Disassembly of section \.text:
 .*:	(83 b9 2f 12|12 2f b9 83) 	vupkint8tofp32 v17,v23,3
 .*:	(da 9e 72 7c|7c 72 9e da) 	lxvpb32x vs34,r18,r19
 .*:	(da af 74 7c|7c 74 af da) 	stxvpb32x vs34,r20,r21
+.*:	(64 10 8f 7c|7c 8f 10 64) 	tlbiep  r2,r4,3,1,1
+.*:	(64 10 60 7c|7c 60 10 64) 	tlbiep  r2,r3
+.*:	(24 38 c8 7c|7c c8 38 24) 	tlbieio r7,r6,2
+.*:	(68 04 20 7d|7d 20 04 68) 	tlbsyncio r9
+.*:	(a8 04 a0 7c|7c a0 04 a8) 	ptesyncio r5
 #pass
diff --git a/gas/testsuite/gas/ppc/future.s b/gas/testsuite/gas/ppc/future.s
index 492b963c96c..27e475c54fd 100644
--- a/gas/testsuite/gas/ppc/future.s
+++ b/gas/testsuite/gas/ppc/future.s
@@ -80,4 +80,9 @@ _start:
 	vupkint8tofp32 17, 23, 3
 	lxvpb32x 34, 18, 19
 	stxvpb32x 34, 20, 21
+	tlbiep 2, 4, 3, 1, 1
+	tlbiep 2, 3
+	tlbieio 7, 6, 2
+	tlbsyncio 9
+	ptesyncio 5
 
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 08d6a38d22f..28644e6385e 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -4628,6 +4628,12 @@ const unsigned int num_powerpc_operands = ARRAY_SIZE (powerpc_operands);
    field.  */
 #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
 
+/* The mask of TLB invalidate Entry for Processor */
+#define X_TLBP_MASK (X_MASK | (1<<20))
+
+/* The mask of TLB invalidate Entry for I/O device */
+#define X_TLBIO_MASK (X_TLBP_MASK | (3<<16))
+
 /* An X form wait instruction with everything filled in except the WC
    and PL fields.  */
 #define XWCPL_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | (3 << 18) | RB_MASK)
@@ -7242,6 +7248,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"tlbilxpid",	XTO(31,18,1),	XTO_MASK, E500MC|PPCA2,	0,		{0}},
 {"tlbilxva",	XTO(31,18,3),	XTO_MASK, E500MC|PPCA2,	0,		{RA0, RB}},
 {"tlbilx",	X(31,18),	X_MASK,	  E500MC|PPCA2,	0,		{T, RA0, RB}},
+{"tlbieio",	X(31,18), 	X_TLBIO_MASK, FUTURE,	0,		{RB, RS, RIC}},
 
 {"mfcr",	XFXM(31,19,0,0), XFXFXM_MASK, COM,	0,		{RT, FXM4}},
 {"mfocrf",	XFXM(31,19,0,1), XFXFXM_MASK, COM,	0,		{RT, FXM}},
@@ -7310,6 +7317,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"subf.",	XO(31,40,0,1),	XO_MASK,     PPC,	0,		{RT, RA, RB}},
 {"sub.",	XO(31,40,0,1),	XO_MASK,     PPC,	EXT,		{RT, RB, RA}},
 
+{"tlbiep",	X(31,50),	XRA_MASK,    FUTURE,	POWER9|EXT,	{RB, RS}},
+{"tlbiep",	X(31,50),	X_TLBP_MASK, FUTURE,	TITAN,		{RB, RS, RIC, PRS, X_R}},
+
 {"mffprd",	X(31,51),	XX1RB_MASK|1, PPCVSX2,	EXT,		{RA, FRS}},
 {"mfvrd",	X(31,51)|1,	XX1RB_MASK|1, PPCVSX2,	EXT,		{RA, VS}},
 {"mfvsrd",	X(31,51),	XX1RB_MASK,   PPCVSX2,	0,		{RA, XS6}},
@@ -8604,6 +8614,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"lxvrll",	X(31,557),	XX1_MASK,    PPCVSXF,	0,		{XT6, RA0, RB}},
 
+{"tlbsyncio",	X(31,564),	XRARB_MASK,  FUTURE,	0,		{RS}},
+
 {"tlbsync",	X(31,566),	0xffffffff,  PPC,	0,		{0}},
 
 {"lfsux",	X(31,567),	X_MASK,	     COM,	PPCEFS,		{FRT, RAS, RB}},
@@ -8629,6 +8641,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"mfsr",	X(31,595), XRB_MASK|(1<<20), COM,	NON32,		{RT, SR}},
 
+{"ptesyncio",	X(31,596),	XRARB_MASK,  FUTURE,	0,		{RS}},
+
 {"lswi",	X(31,597),	X_MASK,	     PPCCOM,	E500|E500MC,	{RT, RAX, NBI}},
 {"lsi",		X(31,597),	X_MASK,	     PWRCOM,	0,		{RT, RA0, NB}},
 
-- 
2.47.3