[PATCH 1/1] RISC-V: Support ".option [no]exact" assembler directives

[Jan Beulich]

On 16.05.2025 11:00, Tsukasa OI wrote:
> On 2025/05/16 15:38, Jan Beulich wrote:
>> Looks quite okay to me. I'm not entirely certain we need the new insn flag, but
>> perhaps it's good to do it this way to also cover the doc aspect (i.e. making
>> explicit which aliases are which).
> 
> Thanks.
> 
> The intent of the new instruction flag is, we don't want to disable all
> aliases but only aliases which will have unintended side effects in the
> context of the exact mode (currently, this flag is applied to RVC
> aliases which will change the instruction length from the non-RVC _main_
> encoding).
> 
> For instance, we want to disable aliases of "addi" / "add" (that turn
> into compressed instructions like "c.addi") in the exact mode but we
> _don't_ want to disable "sgt" (set if greater than) aliases because
> "sgt" only turns into "sle" (set if less than or equal; with two source
> operands flipped) and unintended side effects in the context of the
> exact mode will not occur.
> 
> For documentation, let me consider.  I think the best place to
> improve/describe is at the definition of INSN_NON_EXACT, right?

I'm sorry if I caused confusion - I didn't mean to ask for anything to be
added.

>> The only other (more general) comment I'd
>> have is: For boolean fields in struct riscv_set_options, can't we start using
>> bool?
> 
> I completely agree that and I think even regular bool is wasteful.
> So after the improved version of this patch set is applied, I have a
> plan to submit a patch to change GAS RISC-V option struct members from
> "int OPTION;" to "bool OPTION : 1;" (using bit fields).

Yes please.

Jan