[PATCH] aarch64: Support for FEAT_OCCMO

[Ezra.Sitorus@arm.com]

From: Ezra Sitorus <ezra.sitorus@arm.com>

FEAT_OCCMO - Outer Cacheable Cache Maintenance Operation - introduces system
instructions that provides software with a mechanism to publish writes to the
Outer cache level.
---

This has been regression tested on aarch64-none-linux-gnu. I don't have commit
access yet, so could somebody commit this if it looks ok?

Ezra

 gas/testsuite/gas/aarch64/occmo.d | 18 ++++++++++++++++++
 gas/testsuite/gas/aarch64/occmo.s |  8 ++++++++
 opcodes/aarch64-opc.c             |  4 ++++
 3 files changed, 30 insertions(+)
 create mode 100644 gas/testsuite/gas/aarch64/occmo.d
 create mode 100644 gas/testsuite/gas/aarch64/occmo.s

diff --git a/gas/testsuite/gas/aarch64/occmo.d b/gas/testsuite/gas/aarch64/occmo.d
new file mode 100644
index 00000000000..388d8f4ca0a
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/occmo.d
@@ -0,0 +1,18 @@
+#name: FEAT_OCCMO Test
+#as: -march=armv9.5-a+memtag
+#objdump: -dr
+
+.*:     file format .*
+
+Disassembly of section .text:
+
+0+ <.*>:
+
+[^:]*:	d50b7b00 	dc	cvaoc, x0
+[^:]*:	d50b7b1e 	dc	cvaoc, x30
+[^:]*:	d50b7be0 	dc	cgdvaoc, x0
+[^:]*:	d50b7bfe 	dc	cgdvaoc, x30
+[^:]*:	d50b7f00 	dc	civaoc, x0
+[^:]*:	d50b7f1e 	dc	civaoc, x30
+[^:]*:	d50b7fe0 	dc	cigdvaoc, x0
+[^:]*:	d50b7ffe 	dc	cigdvaoc, x30
diff --git a/gas/testsuite/gas/aarch64/occmo.s b/gas/testsuite/gas/aarch64/occmo.s
new file mode 100644
index 00000000000..92cfaf006fc
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/occmo.s
@@ -0,0 +1,8 @@
+	dc	cvaoc, x0
+	dc	cvaoc, x30
+	dc	cgdvaoc, x0
+	dc	cgdvaoc, x30
+	dc	civaoc, x0
+	dc	civaoc, x30
+	dc	cigdvaoc, x0
+	dc	cigdvaoc, x30
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 4f0c71696fa..8bd99a131e7 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -5206,6 +5206,8 @@ const aarch64_sys_ins_reg aarch64_sys_regs_dc[] =
     { "cvac",       CPENS (3, C7, C10, 1), F_HASXT, AARCH64_NO_FEATURES },
     { "cgvac",      CPENS (3, C7, C10, 3), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (MEMTAG) },
     { "cgdvac",     CPENS (3, C7, C10, 5), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (MEMTAG) },
+    { "cvaoc",      CPENS (3, C7, C11, 0), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (V9_5A) },
+    { "cgdvaoc",    CPENS (3, C7, C11, 7), F_HASXT | F_ARCHEXT, AARCH64_FEATURES (2, V9_5A, MEMTAG) },
     { "csw",	    CPENS (0, C7, C10, 2), F_HASXT, AARCH64_NO_FEATURES },
     { "cgsw",       CPENS (0, C7, C10, 4), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (MEMTAG) },
     { "cgdsw",	    CPENS (0, C7, C10, 6), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (MEMTAG) },
@@ -5222,6 +5224,8 @@ const aarch64_sys_ins_reg aarch64_sys_regs_dc[] =
     { "cisw",       CPENS (0, C7, C14, 2), F_HASXT, AARCH64_NO_FEATURES },
     { "cigsw",      CPENS (0, C7, C14, 4), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (MEMTAG) },
     { "cigdsw",     CPENS (0, C7, C14, 6), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (MEMTAG) },
+    { "civaoc",     CPENS (3, C7, C15, 0), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (V9_5A) },
+    { "cigdvaoc",   CPENS (3, C7, C15, 7), F_HASXT | F_ARCHEXT, AARCH64_FEATURES (2, V9_5A, MEMTAG) },
     { "cipae",      CPENS (4, C7, C14, 0), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (V8_7A) },
     { "cigdpae",    CPENS (4, C7, C14, 7), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (V8_7A) },
     { "cipapa",     CPENS (6, C7, C14, 1), F_HASXT, AARCH64_NO_FEATURES },
-- 
2.45.2