[PATCH 2/2] LoongArch: Fix the mnemonics of ll.acq.[wd] and sc.rel.[wd]
Lulu Cai
cailulu@loongson.cn
Wed Mar 26 07:44:46 GMT 2025
On 3/23/25 5:30 PM, WANG Xuerui wrote:
> From: WANG Xuerui <git@xen0n.name>
>
> Previously the instructions are named llacq.[wd] and screl.[wd]
> respectively, but according to LoongArch ISA manual v1.10, a dot is
> missing before the acq/rel prefix.
The instructions are llacq.[wd] and screl.[wd] instead of ll.acq.[wd]
and sc.rel.[wd]. This is a mistake in the main text of the LoongArch ISA
manual V1.10; the correct names can be found in Appendix B.
> Because there may already exist software using the older mnemonics,
> make them aliases to the correct ones to preserve compatibility.
>
> Signed-off-by: WANG Xuerui <git@xen0n.name>
> ---
> gas/testsuite/gas/loongarch/insn_int64.d | 16 ++--
> gas/testsuite/gas/loongarch/insn_int64.s | 16 ++--
> gas/testsuite/gas/loongarch/load_store_op.d | 88 +++++++++++----------
> gas/testsuite/gas/loongarch/load_store_op.s | 8 ++
> opcodes/loongarch-opc.c | 24 ++++--
> 5 files changed, 88 insertions(+), 64 deletions(-)
>
> diff --git a/gas/testsuite/gas/loongarch/insn_int64.d b/gas/testsuite/gas/loongarch/insn_int64.d
> index 360b840d415..a7333cab274 100644
> --- a/gas/testsuite/gas/loongarch/insn_int64.d
> +++ b/gas/testsuite/gas/loongarch/insn_int64.d
> @@ -370,14 +370,14 @@ Disassembly of section .text:
> 59c: 387f98a4 stle.d \$a0, \$a1, \$a2
> 5a0: 385714c4 sc.q \$a0, \$a1, \$a2
> 5a4: 385714c4 sc.q \$a0, \$a1, \$a2
> - 5a8: 385780a4 llacq.w \$a0, \$a1
> - 5ac: 385780a4 llacq.w \$a0, \$a1
> - 5b0: 385784a4 screl.w \$a0, \$a1
> - 5b4: 385784a4 screl.w \$a0, \$a1
> - 5b8: 385788a4 llacq.d \$a0, \$a1
> - 5bc: 385788a4 llacq.d \$a0, \$a1
> - 5c0: 38578ca4 screl.d \$a0, \$a1
> - 5c4: 38578ca4 screl.d \$a0, \$a1
> + 5a8: 385780a4 ll.acq.w \$a0, \$a1
> + 5ac: 385780a4 ll.acq.w \$a0, \$a1
> + 5b0: 385784a4 sc.rel.w \$a0, \$a1
> + 5b4: 385784a4 sc.rel.w \$a0, \$a1
> + 5b8: 385788a4 ll.acq.d \$a0, \$a1
> + 5bc: 385788a4 ll.acq.d \$a0, \$a1
> + 5c0: 38578ca4 sc.rel.d \$a0, \$a1
> + 5c4: 38578ca4 sc.rel.d \$a0, \$a1
> 5c8: 385814c4 amcas.b \$a0, \$a1, \$a2
> 5cc: 385818a4 amcas.b \$a0, \$a2, \$a1
> 5d0: 385894c4 amcas.h \$a0, \$a1, \$a2
> diff --git a/gas/testsuite/gas/loongarch/insn_int64.s b/gas/testsuite/gas/loongarch/insn_int64.s
> index f80895178d4..fdd0486d90f 100644
> --- a/gas/testsuite/gas/loongarch/insn_int64.s
> +++ b/gas/testsuite/gas/loongarch/insn_int64.s
> @@ -379,14 +379,14 @@ stle.w $r4,$r5,$r6
> stle.d $r4,$r5,$r6
> sc.q $r4,$r5,$r6,0
> sc.q $r4,$r5,$r6
> -llacq.w $r4,$r5,0
> -llacq.w $r4,$r5
> -screl.w $r4,$r5,0
> -screl.w $r4,$r5
> -llacq.d $r4,$r5,0
> -llacq.d $r4,$r5
> -screl.d $r4,$r5,0
> -screl.d $r4,$r5
> +ll.acq.w $r4,$r5,0
> +ll.acq.w $r4,$r5
> +sc.rel.w $r4,$r5,0
> +sc.rel.w $r4,$r5
> +ll.acq.d $r4,$r5,0
> +ll.acq.d $r4,$r5
> +sc.rel.d $r4,$r5,0
> +sc.rel.d $r4,$r5
> amcas.b $r4,$r5,$r6,0
> amcas.b $r4,$r6,$r5
> amcas.h $r4,$r5,$r6,0
> diff --git a/gas/testsuite/gas/loongarch/load_store_op.d b/gas/testsuite/gas/loongarch/load_store_op.d
> index 0ad83167bbc..6ad755760ca 100644
> --- a/gas/testsuite/gas/loongarch/load_store_op.d
> +++ b/gas/testsuite/gas/loongarch/load_store_op.d
> @@ -178,43 +178,51 @@ Disassembly of section .text:
> 2a0:[ ]+387f98a4 [ ]+stle.d[ ]+[ ]+\$a0, \$a1, \$a2
> 2a4:[ ]+385714c4 [ ]+sc.q[ ]+[ ]+\$a0, \$a1, \$a2
> 2a8:[ ]+385714c4 [ ]+sc.q[ ]+[ ]+\$a0, \$a1, \$a2
> - 2ac:[ ]+385780a4 [ ]+llacq.w[ ]+[ ]+\$a0, \$a1
> - 2b0:[ ]+385780a4 [ ]+llacq.w[ ]+[ ]+\$a0, \$a1
> - 2b4:[ ]+385784a4 [ ]+screl.w[ ]+[ ]+\$a0, \$a1
> - 2b8:[ ]+385784a4 [ ]+screl.w[ ]+[ ]+\$a0, \$a1
> - 2bc:[ ]+385788a4 [ ]+llacq.d[ ]+[ ]+\$a0, \$a1
> - 2c0:[ ]+385788a4 [ ]+llacq.d[ ]+[ ]+\$a0, \$a1
> - 2c4:[ ]+38578ca4 [ ]+screl.d[ ]+[ ]+\$a0, \$a1
> - 2c8:[ ]+38578ca4 [ ]+screl.d[ ]+[ ]+\$a0, \$a1
> - 2cc:[ ]+385814c4 [ ]+amcas.b[ ]+[ ]+\$a0, \$a1, \$a2
> - 2d0:[ ]+385818a4 [ ]+amcas.b[ ]+[ ]+\$a0, \$a2, \$a1
> - 2d4:[ ]+385894c4 [ ]+amcas.h[ ]+[ ]+\$a0, \$a1, \$a2
> - 2d8:[ ]+385898a4 [ ]+amcas.h[ ]+[ ]+\$a0, \$a2, \$a1
> - 2dc:[ ]+385914c4 [ ]+amcas.w[ ]+[ ]+\$a0, \$a1, \$a2
> - 2e0:[ ]+385918a4 [ ]+amcas.w[ ]+[ ]+\$a0, \$a2, \$a1
> - 2e4:[ ]+385994c4 [ ]+amcas.d[ ]+[ ]+\$a0, \$a1, \$a2
> - 2e8:[ ]+385998a4 [ ]+amcas.d[ ]+[ ]+\$a0, \$a2, \$a1
> - 2ec:[ ]+385a14c4 [ ]+amcas_db.b[ ]+[ ]+\$a0, \$a1, \$a2
> - 2f0:[ ]+385a18a4 [ ]+amcas_db.b[ ]+[ ]+\$a0, \$a2, \$a1
> - 2f4:[ ]+385a94c4 [ ]+amcas_db.h[ ]+[ ]+\$a0, \$a1, \$a2
> - 2f8:[ ]+385a98a4 [ ]+amcas_db.h[ ]+[ ]+\$a0, \$a2, \$a1
> - 2fc:[ ]+385b14c4 [ ]+amcas_db.w[ ]+[ ]+\$a0, \$a1, \$a2
> - 300:[ ]+385b18a4 [ ]+amcas_db.w[ ]+[ ]+\$a0, \$a2, \$a1
> - 304:[ ]+385b94c4 [ ]+amcas_db.d[ ]+[ ]+\$a0, \$a1, \$a2
> - 308:[ ]+385b98a4 [ ]+amcas_db.d[ ]+[ ]+\$a0, \$a2, \$a1
> - 30c:[ ]+385c14c4 [ ]+amswap.b[ ]+[ ]+\$a0, \$a1, \$a2
> - 310:[ ]+385c18a4 [ ]+amswap.b[ ]+[ ]+\$a0, \$a2, \$a1
> - 314:[ ]+385c94c4 [ ]+amswap.h[ ]+[ ]+\$a0, \$a1, \$a2
> - 318:[ ]+385c98a4 [ ]+amswap.h[ ]+[ ]+\$a0, \$a2, \$a1
> - 31c:[ ]+385d14c4 [ ]+amadd.b[ ]+[ ]+\$a0, \$a1, \$a2
> - 320:[ ]+385d18a4 [ ]+amadd.b[ ]+[ ]+\$a0, \$a2, \$a1
> - 324:[ ]+385d94c4 [ ]+amadd.h[ ]+[ ]+\$a0, \$a1, \$a2
> - 328:[ ]+385d98a4 [ ]+amadd.h[ ]+[ ]+\$a0, \$a2, \$a1
> - 32c:[ ]+385e14c4 [ ]+amswap_db.b[ ]+[ ]+\$a0, \$a1, \$a2
> - 330:[ ]+385e18a4 [ ]+amswap_db.b[ ]+[ ]+\$a0, \$a2, \$a1
> - 334:[ ]+385e94c4 [ ]+amswap_db.h[ ]+[ ]+\$a0, \$a1, \$a2
> - 338:[ ]+385e98a4 [ ]+amswap_db.h[ ]+[ ]+\$a0, \$a2, \$a1
> - 33c:[ ]+385f14c4 [ ]+amadd_db.b[ ]+[ ]+\$a0, \$a1, \$a2
> - 340:[ ]+385f18a4 [ ]+amadd_db.b[ ]+[ ]+\$a0, \$a2, \$a1
> - 344:[ ]+385f94c4 [ ]+amadd_db.h[ ]+[ ]+\$a0, \$a1, \$a2
> - 348:[ ]+385f98a4 [ ]+amadd_db.h[ ]+[ ]+\$a0, \$a2, \$a1
> + 2ac:[ ]+385780a4 [ ]+ll.acq.w[ ]+[ ]+\$a0, \$a1
> + 2b0:[ ]+385780a4 [ ]+ll.acq.w[ ]+[ ]+\$a0, \$a1
> + 2b4:[ ]+385780a4 [ ]+ll.acq.w[ ]+[ ]+\$a0, \$a1
> + 2b8:[ ]+385780a4 [ ]+ll.acq.w[ ]+[ ]+\$a0, \$a1
> + 2bc:[ ]+385784a4 [ ]+sc.rel.w[ ]+[ ]+\$a0, \$a1
> + 2c0:[ ]+385784a4 [ ]+sc.rel.w[ ]+[ ]+\$a0, \$a1
> + 2c4:[ ]+385784a4 [ ]+sc.rel.w[ ]+[ ]+\$a0, \$a1
> + 2c8:[ ]+385784a4 [ ]+sc.rel.w[ ]+[ ]+\$a0, \$a1
> + 2cc:[ ]+385788a4 [ ]+ll.acq.d[ ]+[ ]+\$a0, \$a1
> + 2d0:[ ]+385788a4 [ ]+ll.acq.d[ ]+[ ]+\$a0, \$a1
> + 2d4:[ ]+385788a4 [ ]+ll.acq.d[ ]+[ ]+\$a0, \$a1
> + 2d8:[ ]+385788a4 [ ]+ll.acq.d[ ]+[ ]+\$a0, \$a1
> + 2dc:[ ]+38578ca4 [ ]+sc.rel.d[ ]+[ ]+\$a0, \$a1
> + 2e0:[ ]+38578ca4 [ ]+sc.rel.d[ ]+[ ]+\$a0, \$a1
> + 2e4:[ ]+38578ca4 [ ]+sc.rel.d[ ]+[ ]+\$a0, \$a1
> + 2e8:[ ]+38578ca4 [ ]+sc.rel.d[ ]+[ ]+\$a0, \$a1
> + 2ec:[ ]+385814c4 [ ]+amcas.b[ ]+[ ]+\$a0, \$a1, \$a2
> + 2f0:[ ]+385818a4 [ ]+amcas.b[ ]+[ ]+\$a0, \$a2, \$a1
> + 2f4:[ ]+385894c4 [ ]+amcas.h[ ]+[ ]+\$a0, \$a1, \$a2
> + 2f8:[ ]+385898a4 [ ]+amcas.h[ ]+[ ]+\$a0, \$a2, \$a1
> + 2fc:[ ]+385914c4 [ ]+amcas.w[ ]+[ ]+\$a0, \$a1, \$a2
> + 300:[ ]+385918a4 [ ]+amcas.w[ ]+[ ]+\$a0, \$a2, \$a1
> + 304:[ ]+385994c4 [ ]+amcas.d[ ]+[ ]+\$a0, \$a1, \$a2
> + 308:[ ]+385998a4 [ ]+amcas.d[ ]+[ ]+\$a0, \$a2, \$a1
> + 30c:[ ]+385a14c4 [ ]+amcas_db.b[ ]+[ ]+\$a0, \$a1, \$a2
> + 310:[ ]+385a18a4 [ ]+amcas_db.b[ ]+[ ]+\$a0, \$a2, \$a1
> + 314:[ ]+385a94c4 [ ]+amcas_db.h[ ]+[ ]+\$a0, \$a1, \$a2
> + 318:[ ]+385a98a4 [ ]+amcas_db.h[ ]+[ ]+\$a0, \$a2, \$a1
> + 31c:[ ]+385b14c4 [ ]+amcas_db.w[ ]+[ ]+\$a0, \$a1, \$a2
> + 320:[ ]+385b18a4 [ ]+amcas_db.w[ ]+[ ]+\$a0, \$a2, \$a1
> + 324:[ ]+385b94c4 [ ]+amcas_db.d[ ]+[ ]+\$a0, \$a1, \$a2
> + 328:[ ]+385b98a4 [ ]+amcas_db.d[ ]+[ ]+\$a0, \$a2, \$a1
> + 32c:[ ]+385c14c4 [ ]+amswap.b[ ]+[ ]+\$a0, \$a1, \$a2
> + 330:[ ]+385c18a4 [ ]+amswap.b[ ]+[ ]+\$a0, \$a2, \$a1
> + 334:[ ]+385c94c4 [ ]+amswap.h[ ]+[ ]+\$a0, \$a1, \$a2
> + 338:[ ]+385c98a4 [ ]+amswap.h[ ]+[ ]+\$a0, \$a2, \$a1
> + 33c:[ ]+385d14c4 [ ]+amadd.b[ ]+[ ]+\$a0, \$a1, \$a2
> + 340:[ ]+385d18a4 [ ]+amadd.b[ ]+[ ]+\$a0, \$a2, \$a1
> + 344:[ ]+385d94c4 [ ]+amadd.h[ ]+[ ]+\$a0, \$a1, \$a2
> + 348:[ ]+385d98a4 [ ]+amadd.h[ ]+[ ]+\$a0, \$a2, \$a1
> + 34c:[ ]+385e14c4 [ ]+amswap_db.b[ ]+[ ]+\$a0, \$a1, \$a2
> + 350:[ ]+385e18a4 [ ]+amswap_db.b[ ]+[ ]+\$a0, \$a2, \$a1
> + 354:[ ]+385e94c4 [ ]+amswap_db.h[ ]+[ ]+\$a0, \$a1, \$a2
> + 358:[ ]+385e98a4 [ ]+amswap_db.h[ ]+[ ]+\$a0, \$a2, \$a1
> + 35c:[ ]+385f14c4 [ ]+amadd_db.b[ ]+[ ]+\$a0, \$a1, \$a2
> + 360:[ ]+385f18a4 [ ]+amadd_db.b[ ]+[ ]+\$a0, \$a2, \$a1
> + 364:[ ]+385f94c4 [ ]+amadd_db.h[ ]+[ ]+\$a0, \$a1, \$a2
> + 368:[ ]+385f98a4 [ ]+amadd_db.h[ ]+[ ]+\$a0, \$a2, \$a1
> diff --git a/gas/testsuite/gas/loongarch/load_store_op.s b/gas/testsuite/gas/loongarch/load_store_op.s
> index 7912adb1090..972a51d125e 100644
> --- a/gas/testsuite/gas/loongarch/load_store_op.s
> +++ b/gas/testsuite/gas/loongarch/load_store_op.s
> @@ -171,12 +171,20 @@ sc.q $r4,$r5,$r6,0
> sc.q $r4,$r5,$r6
> llacq.w $r4,$r5,0
> llacq.w $r4,$r5
> +ll.acq.w $r4,$r5,0
> +ll.acq.w $r4,$r5
> screl.w $r4,$r5,0
> screl.w $r4,$r5
> +sc.rel.w $r4,$r5,0
> +sc.rel.w $r4,$r5
> llacq.d $r4,$r5,0
> llacq.d $r4,$r5
> +ll.acq.d $r4,$r5,0
> +ll.acq.d $r4,$r5
> screl.d $r4,$r5,0
> screl.d $r4,$r5
> +sc.rel.d $r4,$r5,0
> +sc.rel.d $r4,$r5
> amcas.b $r4,$r5,$r6,0
> amcas.b $r4,$r6,$r5
> amcas.h $r4,$r5,$r6,0
> diff --git a/opcodes/loongarch-opc.c b/opcodes/loongarch-opc.c
> index fa53021cfae..c2fc9afe9f3 100644
> --- a/opcodes/loongarch-opc.c
> +++ b/opcodes/loongarch-opc.c
> @@ -936,14 +936,22 @@ static struct loongarch_opcode loongarch_load_store_opcodes[] =
> { 0x382c0000, 0xffff8000, "preldx", "u0:5,r5:5,r10:5", 0, 0, 0, 0 },
> { 0x0, 0x0, "sc.q", "r,r,r,u0:0", "sc.q %1,%2,%3", 0, 0, 0 },
> { 0x38570000, 0xffff8000, "sc.q", "r0:5,r10:5,r5:5", 0, 0, 0, 0 },
> - { 0x0, 0x0, "llacq.w", "r,r,u0:0", "llacq.w %1,%2", 0, 0, 0 },
> - { 0x38578000, 0xfffffc00, "llacq.w", "r0:5,r5:5", 0, 0, 0, 0 },
> - { 0x0, 0x0, "screl.w", "r,r,u0:0", "screl.w %1,%2", 0, 0, 0 },
> - { 0x38578400, 0xfffffc00, "screl.w", "r0:5,r5:5", 0, 0, 0, 0 },
> - { 0x0, 0x0, "llacq.d", "r,r,u0:0", "llacq.d %1,%2", 0, 0, 0 },
> - { 0x38578800, 0xfffffc00, "llacq.d", "r0:5,r5:5", 0, 0, 0, 0 },
> - { 0x0, 0x0, "screl.d", "r,r,u0:0", "screl.d %1,%2", 0, 0, 0 },
> - { 0x38578c00, 0xfffffc00, "screl.d", "r0:5,r5:5", 0, 0, 0, 0 },
> + { 0x0, 0x0, "llacq.w", "r,r,u0:0", "ll.acq.w %1,%2", 0, 0, 0 },
> + { 0x0, 0x0, "llacq.w", "r0:5,r5:5", "ll.acq.w %1,%2", 0, 0, 0 },
> + { 0x0, 0x0, "ll.acq.w", "r,r,u0:0", "ll.acq.w %1,%2", 0, 0, 0 },
> + { 0x38578000, 0xfffffc00, "ll.acq.w", "r0:5,r5:5", 0, 0, 0, 0 },
> + { 0x0, 0x0, "screl.w", "r,r,u0:0", "sc.rel.w %1,%2", 0, 0, 0 },
> + { 0x0, 0x0, "screl.w", "r0:5,r5:5", "sc.rel.w %1,%2", 0, 0, 0 },
> + { 0x0, 0x0, "sc.rel.w", "r,r,u0:0", "sc.rel.w %1,%2", 0, 0, 0 },
> + { 0x38578400, 0xfffffc00, "sc.rel.w", "r0:5,r5:5", 0, 0, 0, 0 },
> + { 0x0, 0x0, "llacq.d", "r,r,u0:0", "ll.acq.d %1,%2", 0, 0, 0 },
> + { 0x0, 0x0, "llacq.d", "r0:5,r5:5", "ll.acq.d %1,%2", 0, 0, 0 },
> + { 0x0, 0x0, "ll.acq.d", "r,r,u0:0", "ll.acq.d %1,%2", 0, 0, 0 },
> + { 0x38578800, 0xfffffc00, "ll.acq.d", "r0:5,r5:5", 0, 0, 0, 0 },
> + { 0x0, 0x0, "screl.d", "r,r,u0:0", "sc.rel.d %1,%2", 0, 0, 0 },
> + { 0x0, 0x0, "screl.d", "r0:5,r5:5", "sc.rel.d %1,%2", 0, 0, 0 },
> + { 0x0, 0x0, "sc.rel.d", "r,r,u0:0", "sc.rel.d %1,%2", 0, 0, 0 },
> + { 0x38578c00, 0xfffffc00, "sc.rel.d", "r0:5,r5:5", 0, 0, 0, 0 },
> { 0x0, 0x0, "amcas.b", "r,r,r,u0:0", "amcas.b %1,%2,%3", 0, 0, 0 },
> { 0x38580000, 0xffff8000, "amcas.b", "r0:5,r10:5,r5:5", 0, 0, 0, 0 },
> { 0x0, 0x0, "amcas.h", "r,r,r,u0:0", "amcas.h %1,%2,%3", 0, 0, 0 },
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