[PATCH] RISC-V: Support Zalasr extension
Nelson Chu
nelson@rivosinc.com
Thu Mar 20 08:19:43 GMT 2025
From: Brendan Sweeney <turtwig@utexas.edu>
====
There was a patch sent by Tsukasa OI before for this with draft v0.1. Even
the encodings and mnemonic don't changed for current draft v0.3.5, we cannot
promise that won't happen since it's still draft. The one of the spec main
contributors, Brendan Sweeney, will continue to maintain the implementation
in our internal branch, and make sure it will be the same as the later spec.
So, I keep Brendan as the main author of this series of patch, and list Tsukasa
as an important co-author. Brendan is willing to use his utexas email for this
patch, so I will follow his wishes.
Thanks
Nelson
=====
Spec v0.3.5,
https://github.com/riscv/riscv-zalasr/blob/main/chapter2.adoc
Encodings,
https://github.com/search?q=repo%3Ariscv%2Friscv-opcodes%20zalasr&type=code
Signed-off-by: Brendan Sweeney <turtwig@utexas.edu>
Co-Authored-By: Tsukasa OI <research_trasio@irq.a4lg.com>
---
bfd/elfxx-riscv.c | 5 +++++
gas/testsuite/gas/riscv/march-help.l | 1 +
gas/testsuite/gas/riscv/zalasr.d | 26 ++++++++++++++++++++++++++
gas/testsuite/gas/riscv/zalasr.s | 18 ++++++++++++++++++
include/opcode/riscv-opc.h | 26 ++++++++++++++++++++++++++
include/opcode/riscv.h | 1 +
opcodes/riscv-opc.c | 18 ++++++++++++++++++
7 files changed, 95 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/zalasr.d
create mode 100644 gas/testsuite/gas/riscv/zalasr.s
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 481bac91d73..69fcdcbb6ef 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1366,6 +1366,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{"zaamo", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zabha", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zacas", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zalasr", ISA_SPEC_CLASS_DRAFT, 0, 3, 0 },
{"zalrsc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zawrs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zfbfmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
@@ -2650,6 +2651,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
case INSN_CLASS_ZABHA_AND_ZACAS:
return (riscv_subset_supports (rps, "zabha")
&& riscv_subset_supports (rps, "zacas"));
+ case INSN_CLASS_ZALASR:
+ return riscv_subset_supports (rps, "zalasr");
case INSN_CLASS_ZALRSC:
return riscv_subset_supports (rps, "zalrsc");
case INSN_CLASS_ZAWRS:
@@ -2928,6 +2931,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
return "zabha";
case INSN_CLASS_ZACAS:
return "zacas";
+ case INSN_CLASS_ZALASR:
+ return "zalasr";
case INSN_CLASS_ZALRSC:
return "zalrsc";
case INSN_CLASS_ZAWRS:
diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l
index d77472fda9c..db24596603e 100644
--- a/gas/testsuite/gas/riscv/march-help.l
+++ b/gas/testsuite/gas/riscv/march-help.l
@@ -34,6 +34,7 @@ All available -march extensions for RISC-V:
zaamo 1.0
zabha 1.0
zacas 1.0
+ zalasr 0.3
zalrsc 1.0
zawrs 1.0
zfbfmin 1.0
diff --git a/gas/testsuite/gas/riscv/zalasr.d b/gas/testsuite/gas/riscv/zalasr.d
new file mode 100644
index 00000000000..7e4c3e9d011
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zalasr.d
@@ -0,0 +1,26 @@
+#as:
+#source: zalasr.s
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <.text>:
+[ ]+[0-9a-f]+:[ ]+3405052f[ ]+lb.aq[ ]+a0,\(a0\)
+[ ]+[0-9a-f]+:[ ]+3405152f[ ]+lh.aq[ ]+a0,\(a0\)
+[ ]+[0-9a-f]+:[ ]+3405252f[ ]+lw.aq[ ]+a0,\(a0\)
+[ ]+[0-9a-f]+:[ ]+3605052f[ ]+lb.aqrl[ ]+a0,\(a0\)
+[ ]+[0-9a-f]+:[ ]+3605152f[ ]+lh.aqrl[ ]+a0,\(a0\)
+[ ]+[0-9a-f]+:[ ]+3605252f[ ]+lw.aqrl[ ]+a0,\(a0\)
+[ ]+[0-9a-f]+:[ ]+3aa5002f[ ]+sb.rl[ ]+a0,\(a0\)
+[ ]+[0-9a-f]+:[ ]+3aa5102f[ ]+sh.rl[ ]+a0,\(a0\)
+[ ]+[0-9a-f]+:[ ]+3aa5202f[ ]+sw.rl[ ]+a0,\(a0\)
+[ ]+[0-9a-f]+:[ ]+3ea5002f[ ]+sb.aqrl[ ]+a0,\(a0\)
+[ ]+[0-9a-f]+:[ ]+3ea5102f[ ]+sh.aqrl[ ]+a0,\(a0\)
+[ ]+[0-9a-f]+:[ ]+3ea5202f[ ]+sw.aqrl[ ]+a0,\(a0\)
+[ ]+[0-9a-f]+:[ ]+3405352f[ ]+ld.aq[ ]+a0,\(a0\)
+[ ]+[0-9a-f]+:[ ]+3605352f[ ]+ld.aqrl[ ]+a0,\(a0\)
+[ ]+[0-9a-f]+:[ ]+3aa5302f[ ]+sd.rl[ ]+a0,\(a0\)
+[ ]+[0-9a-f]+:[ ]+3ea5302f[ ]+sd.aqrl[ ]+a0,\(a0\)
diff --git a/gas/testsuite/gas/riscv/zalasr.s b/gas/testsuite/gas/riscv/zalasr.s
new file mode 100644
index 00000000000..f255dd8f9d3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zalasr.s
@@ -0,0 +1,18 @@
+.option arch, rv32i_zalasr
+lb.aq a0, 0(a0)
+lh.aq a0, 0(a0)
+lw.aq a0, 0(a0)
+lb.aqrl a0, 0(a0)
+lh.aqrl a0, 0(a0)
+lw.aqrl a0, 0(a0)
+sb.rl a0, 0(a0)
+sh.rl a0, 0(a0)
+sw.rl a0, 0(a0)
+sb.aqrl a0, 0(a0)
+sh.aqrl a0, 0(a0)
+sw.aqrl a0, 0(a0)
+.option arch, rv64i_zalasr
+ld.aq a0, 0(a0)
+ld.aqrl a0, 0(a0)
+sd.rl a0, 0(a0)
+sd.aqrl a0, 0(a0)
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 1f56317e255..47377c7eb70 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2497,6 +2497,23 @@
#define MASK_AMOCAS_D 0xf800707f
#define MATCH_AMOCAS_Q 0x2800402f
#define MASK_AMOCAS_Q 0xf800707f
+/* Zalasr instructions. */
+#define MATCH_LB_AQ 0x3400002f
+#define MASK_LB_AQ 0xfdf0707f
+#define MATCH_LH_AQ 0x3400102f
+#define MASK_LH_AQ 0xfdf0707f
+#define MATCH_LW_AQ 0x3400202f
+#define MASK_LW_AQ 0xfdf0707f
+#define MATCH_LD_AQ 0x3400302f
+#define MASK_LD_AQ 0xfdf0707f
+#define MATCH_SB_RL 0x3a00002f
+#define MASK_SB_RL 0xfa007fff
+#define MATCH_SH_RL 0x3a00102f
+#define MASK_SH_RL 0xfa007fff
+#define MATCH_SW_RL 0x3a00202f
+#define MASK_SW_RL 0xfa007fff
+#define MATCH_SD_RL 0x3a00302f
+#define MASK_SD_RL 0xfa007fff
/* Zawrs instructions. */
#define MATCH_WRS_NTO 0x00d00073
#define MASK_WRS_NTO 0xffffffff
@@ -4714,6 +4731,15 @@ DECLARE_INSN(MOP_RR_7, MATCH_MOP_RR_7, MASK_MOP_RR_7)
DECLARE_INSN(amocas_w, MATCH_AMOCAS_W, MASK_AMOCAS_W)
DECLARE_INSN(amocas_d, MATCH_AMOCAS_D, MASK_AMOCAS_D)
DECLARE_INSN(amocas_q, MATCH_AMOCAS_Q, MASK_AMOCAS_Q)
+/* Zalasr instructions. */
+DECLARE_INSN(lb_aq, MATCH_LB_AQ, MASK_LB_AQ)
+DECLARE_INSN(lh_aq, MATCH_LH_AQ, MASK_LH_AQ)
+DECLARE_INSN(lw_aq, MATCH_LW_AQ, MASK_LW_AQ)
+DECLARE_INSN(ld_aq, MATCH_LD_AQ, MASK_LD_AQ)
+DECLARE_INSN(sb_rl, MATCH_SB_RL, MASK_SB_RL)
+DECLARE_INSN(sh_rl, MATCH_SH_RL, MASK_SH_RL)
+DECLARE_INSN(sw_rl, MATCH_SW_RL, MASK_SW_RL)
+DECLARE_INSN(sd_rl, MATCH_SD_RL, MASK_SD_RL)
/* Zawrs instructions. */
DECLARE_INSN(wrs_nto, MATCH_WRS_NTO, MASK_WRS_NTO)
DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO)
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 1f4bede428e..7ee4b50ad6a 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -472,6 +472,7 @@ enum riscv_insn_class
INSN_CLASS_ZIMOP,
INSN_CLASS_ZMMUL,
INSN_CLASS_ZAAMO,
+ INSN_CLASS_ZALASR,
INSN_CLASS_ZALRSC,
INSN_CLASS_ZAWRS,
INSN_CLASS_F_INX,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index b83dcabf7fc..2b9e0999bf1 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -1238,6 +1238,24 @@ const struct riscv_opcode riscv_opcodes[] =
{"mop.rr.6", 0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_6, MASK_MOP_RR_6, match_opcode, 0 },
{"mop.rr.7", 0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_7, MASK_MOP_RR_7, match_opcode, 0 },
+/* Zalasr instructions. */
+{"lb.aq", 0, INSN_CLASS_ZALASR, "d,0(s)", MATCH_LB_AQ, MASK_LB_AQ|MASK_RL, match_opcode, INSN_DREF|INSN_1_BYTE },
+{"lb.aqrl", 0, INSN_CLASS_ZALASR, "d,0(s)", MATCH_LB_AQ|MASK_RL, MASK_LB_AQ|MASK_RL, match_opcode, INSN_DREF|INSN_1_BYTE },
+{"lh.aq", 0, INSN_CLASS_ZALASR, "d,0(s)", MATCH_LH_AQ, MASK_LH_AQ|MASK_RL, match_opcode, INSN_DREF|INSN_2_BYTE },
+{"lh.aqrl", 0, INSN_CLASS_ZALASR, "d,0(s)", MATCH_LH_AQ|MASK_RL, MASK_LH_AQ|MASK_RL, match_opcode, INSN_DREF|INSN_2_BYTE },
+{"lw.aq", 0, INSN_CLASS_ZALASR, "d,0(s)", MATCH_LW_AQ, MASK_LW_AQ|MASK_RL, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"lw.aqrl", 0, INSN_CLASS_ZALASR, "d,0(s)", MATCH_LW_AQ|MASK_RL, MASK_LW_AQ|MASK_RL, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"ld.aq", 64, INSN_CLASS_ZALASR, "d,0(s)", MATCH_LD_AQ, MASK_LD_AQ|MASK_RL, match_opcode, INSN_DREF|INSN_8_BYTE },
+{"ld.aqrl", 64, INSN_CLASS_ZALASR, "d,0(s)", MATCH_LD_AQ|MASK_RL, MASK_LD_AQ|MASK_RL, match_opcode, INSN_DREF|INSN_8_BYTE },
+{"sb.rl", 0, INSN_CLASS_ZALASR, "t,0(s)", MATCH_SB_RL, MASK_SB_RL|MASK_AQ, match_opcode, INSN_DREF|INSN_1_BYTE },
+{"sb.aqrl", 0, INSN_CLASS_ZALASR, "t,0(s)", MATCH_SB_RL|MASK_AQ, MASK_SB_RL|MASK_AQ, match_opcode, INSN_DREF|INSN_1_BYTE },
+{"sh.rl", 0, INSN_CLASS_ZALASR, "t,0(s)", MATCH_SH_RL, MASK_SH_RL|MASK_AQ, match_opcode, INSN_DREF|INSN_1_BYTE },
+{"sh.aqrl", 0, INSN_CLASS_ZALASR, "t,0(s)", MATCH_SH_RL|MASK_AQ, MASK_SH_RL|MASK_AQ, match_opcode, INSN_DREF|INSN_1_BYTE },
+{"sw.rl", 0, INSN_CLASS_ZALASR, "t,0(s)", MATCH_SW_RL, MASK_SW_RL|MASK_AQ, match_opcode, INSN_DREF|INSN_1_BYTE },
+{"sw.aqrl", 0, INSN_CLASS_ZALASR, "t,0(s)", MATCH_SW_RL|MASK_AQ, MASK_SW_RL|MASK_AQ, match_opcode, INSN_DREF|INSN_1_BYTE },
+{"sd.rl", 64, INSN_CLASS_ZALASR, "t,0(s)", MATCH_SD_RL, MASK_SD_RL|MASK_AQ, match_opcode, INSN_DREF|INSN_1_BYTE },
+{"sd.aqrl", 64, INSN_CLASS_ZALASR, "t,0(s)", MATCH_SD_RL|MASK_AQ, MASK_SD_RL|MASK_AQ, match_opcode, INSN_DREF|INSN_1_BYTE },
+
/* Zawrs instructions. */
{"wrs.nto", 0, INSN_CLASS_ZAWRS, "", MATCH_WRS_NTO, MASK_WRS_NTO, match_opcode, 0 },
{"wrs.sto", 0, INSN_CLASS_ZAWRS, "", MATCH_WRS_STO, MASK_WRS_STO, match_opcode, 0 },
--
2.39.3 (Apple Git-146)
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