[PATCH] RISC-V: Add support for ssnpm, smnpm and smmpm extensions.

[Nelson Chu]

There is no instruction support and no new csrs, so why do we need the
INSN_CLASS and imply zicsr for these extensions?

Nelson

On Wed, Mar 19, 2025 at 6:43 PM chendongyan <chendongyan@isrc.iscas.ac.cn>
wrote:

> Hi Nelson,
>
> The patch from Jerry Zhang Jian lacks some macro definition and zicsr
> dependent code, which I think is useful for the instructions support, and I
> have written it in my patch, and can complete the remaining sspm and supm
> extensions. Can I become a co-author for this patch?
>
> Thanks
>
> Dongyan Chen
> 在 2025/3/18 14:39, Nelson Chu 写道:
>
> Thanks for helping with this :-)  I found another patch,
> https://sourceware.org/pipermail/binutils/2025-March/140026.html, which
> seems the same, but do more about the conflict checking, and also has sspm
> and supm supports, so I based on that patch to add testcase and then
> commit.
>
> Thanks
> Nelson
>
> On Mon, Mar 17, 2025 at 7:32 PM Dongyan Chen <chendongyan@isrc.iscas.ac.cn>
> wrote:
>
>> This implements the ssnpm, smnpm and smmpm extensons, version 1.0[1].
>>
>> [1]
>> https://github.com/riscv/riscv-j-extension/blob/master/zjpm/instructions.adoc
>>
>> bfd/ChangeLog:
>>
>>         * elfxx-riscv.c (riscv_multi_subset_supports): Handle ssnpm,
>> smnpm and smmpm.
>>         (riscv_multi_subset_supports_ext): Ditto.
>>
>> gas/ChangeLog:
>>
>>         * NEWS: Updated.
>>         * testsuite/gas/riscv/march-help.l: Updated.
>>
>> include/ChangeLog:
>>
>>         * opcode/riscv.h (enum riscv_insn_class): New operand.
>>
>> ---
>>  bfd/elfxx-riscv.c                    | 19 +++++++++++++++++++
>>  gas/NEWS                             |  2 ++
>>  gas/testsuite/gas/riscv/march-help.l |  3 +++
>>  include/opcode/riscv.h               |  3 +++
>>  4 files changed, 27 insertions(+)
>>
>> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
>> index fd2cb74df80..c6aaed54fa1 100644
>> --- a/bfd/elfxx-riscv.c
>> +++ b/bfd/elfxx-riscv.c
>> @@ -1279,6 +1279,10 @@ static struct riscv_implicit_subset
>> riscv_implicit_subsets[] =
>>    {"ssu64xl", "+zicsr", check_implicit_always},
>>    {"ssdbltrp", "+zicsr", check_implicit_always},
>>
>> +  {"ssnpm", "+zicsr", check_implicit_always},
>> +  {"smnpm", "+zicsr", check_implicit_always},
>> +  {"smmpm", "+zicsr", check_implicit_always},
>> +
>>    {"svade", "+zicsr", check_implicit_always},
>>    {"svadu", "+zicsr", check_implicit_always},
>>    {"svbare", "+zicsr", check_implicit_always},
>> @@ -1477,6 +1481,9 @@ static struct riscv_supported_ext
>> riscv_supported_std_s_ext[] =
>>    {"svnapot",          ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
>>    {"svpbmt",           ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
>>    {"ssqosid",          ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
>> +  {"ssnpm",            ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
>> +  {"smnpm",            ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
>> +  {"smmpm",            ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
>>    {NULL, 0, 0, 0, 0}
>>  };
>>
>> @@ -2757,6 +2764,12 @@ riscv_multi_subset_supports (riscv_parse_subset_t
>> *rps,
>>               || riscv_subset_supports (rps, "ssctr"));
>>      case INSN_CLASS_SVINVAL:
>>        return riscv_subset_supports (rps, "svinval");
>> +    case INSN_CLASS_SSNPM:
>> +      return riscv_subset_supports (rps, "ssnpm");
>> +    case INSN_CLASS_SMNPM:
>> +      return riscv_subset_supports (rps, "smnpm");
>> +    case INSN_CLASS_SMMPM:
>> +      return riscv_subset_supports (rps, "smmpm");
>>      case INSN_CLASS_H:
>>        return riscv_subset_supports (rps, "h");
>>      case INSN_CLASS_XCVALU:
>> @@ -3062,6 +3075,12 @@ riscv_multi_subset_supports_ext
>> (riscv_parse_subset_t *rps,
>>        return _("smctr' or `ssctr");
>>      case INSN_CLASS_SVINVAL:
>>        return "svinval";
>> +    case INSN_CLASS_SSNPM:
>> +      return "ssnpm";
>> +    case INSN_CLASS_SMNPM:
>> +      return "smnpm";
>> +    case INSN_CLASS_SMMPM:
>> +      return "smmpm";
>>      case INSN_CLASS_H:
>>        return _("h");
>>      case INSN_CLASS_XCVALU:
>> diff --git a/gas/NEWS b/gas/NEWS
>> index 6c5af12178f..58459b871e0 100644
>> --- a/gas/NEWS
>> +++ b/gas/NEWS
>> @@ -2,6 +2,8 @@
>>
>>  * Add support for the x86 Zhaoxin PadLock XMODX instructions.
>>
>> +* Add support for the RISC-V s[sm]npm and smmpm extensions, version 1.0.
>> +
>>  Changes in 2.44:
>>
>>  * Add support for the x86 Intel Diamond Rapids AMX instructions,
>> including
>> diff --git a/gas/testsuite/gas/riscv/march-help.l
>> b/gas/testsuite/gas/riscv/march-help.l
>> index b7975ff9ade..80c1da13e68 100644
>> --- a/gas/testsuite/gas/riscv/march-help.l
>> +++ b/gas/testsuite/gas/riscv/march-help.l
>> @@ -133,6 +133,9 @@ All available -march extensions for RISC-V:
>>         sstvecd                                 1.0
>>         ssu64xl                                 1.0
>>         ssdbltrp                                1.0
>> +       ssnpm                                   1.0
>> +       smnpm                                   1.0
>> +       smmpm                                   1.0
>>         svade                                   1.0
>>         svadu                                   1.0
>>         svbare                                  1.0
>> diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
>> index 6bcea638025..93b20138546 100644
>> --- a/include/opcode/riscv.h
>> +++ b/include/opcode/riscv.h
>> @@ -527,6 +527,9 @@ enum riscv_insn_class
>>    INSN_CLASS_ZCMT,
>>    INSN_CLASS_SMCTR_OR_SSCTR,
>>    INSN_CLASS_SVINVAL,
>> +  INSN_CLASS_SSNPM,
>> +  INSN_CLASS_SMNPM,
>> +  INSN_CLASS_SMMPM,
>>    INSN_CLASS_ZICBOM,
>>    INSN_CLASS_ZICBOP,
>>    INSN_CLASS_ZICBOZ,
>> --
>> 2.43.0
>>
>>
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