[PATCH] aarch64: simplify RCPC3 unpredictable logic

[Jan Beulich]

On 27.02.2025 16:16, Andrew Carlotti wrote:
> On Tue, Feb 25, 2025 at 12:03:41PM +0100, Jan Beulich wrote:
>> The original observation was that STILP is warned about when everything
>> is fine. Documentation, not just for STILP, says explicitly that
>> behavior is identical to respective pre-existing insns (for STILP in
>> particular that's STP). With that it's unclear why distinct logic was
>> added: Other code can be re-used, simply distinguishing by the number of
>> operands. This was diagnostics also end up more consistent.
> 
> Thanks - I agree that the reuse is better.  I wonder whether it would have been
> possible to reuse existing instruction classes, but the simpler change you've
> made seems good for now.
> 
>> Along with adjusting some of the STILP uses in the (positive) testcase,
>> also adjust a few STLR to similarly demonstrate that the register
>> overlap goes without warning when there's no write-back.
> 
> Can you add these as new entries (within the existing file), rather than
> changing existing entries?  That would ensure we retain all the existing
> checks, and would make it clear that the original tests here are still valid.

I would have done so if I saw any value in retaining those. My take is that
these were added in their original shape only to avoid the warnings.

Jan