[PATCH v8 (+PING) 1/1] RISC-V: Support ".option [no]exact" assembler directives

[Nelson Chu]

Oops, I missed this one...  Okay, looks good, please commit, thanks.

Nelson

On Thu, May 29, 2025 at 2:47 PM Tsukasa OI <research_trasio@irq.a4lg.com>
wrote:

> From: Tsukasa OI <research_trasio@irq.a4lg.com>
>
> This commit adds two assembler directives: ".option exact" and
> ".option noexact" (enable/disable the exact mode) as discussed in
> <https://github.com/riscv-non-isa/riscv-asm-manual/pull/122> and
> already implemented in LLVM.
>
> When the exact mode is enabled,
>
> 1.  Linker relaxations are turned off,
> 2.  Instruction aliases that will change the encoding from the
>     (likely non-alias) instruction with the same name are disabled
>     (e.g. "addi" will never turn into "c.addi" even if optimizable) and
> 3.  Assembler relaxation of branch instructions are disabled
>     (e.g. "blt" with a long offset will not turn into "bge + j").
>
> Macros like "li" (known to be expanded into possibly complex sequences)
> may still expand to complex instruction sequences but at least each
> instruction emitted by macros is still subject to the behavior above.
>
> Currently, interactions between ".option relax/norelax" and
> ".option exact/noexact" are designed to be LLVM-compatible (i.e.
> ".option exact/noexact" imply ".option norelax/relax", respectively)
> but considered flaky and strongly discouraged from using both.
>
> cf. <https://github.com/llvm/llvm-project/pull/122483>
>
> gas/ChangeLog:
>
>         * config/tc-riscv.c (struct riscv_set_options): Add exact option.
>         (RELAX_BRANCH_ENCODE): Encode exact option.
>         (RELAX_BRANCH_EXACT): New predicate macro.
>         (relaxed_branch_length): Handle exact mode cases.
>         (append_insn): Pass exact option to RELAX_BRANCH_ENCODE.
>         (riscv_ip): Skip instructions that would change the encoding
>         when the exact mode is enabled.
>         (s_riscv_option): Parse ".option exact" and ".option noexact"
>         assembler directives.
>         * doc/c-riscv.texi: Document new assembler directives.
>         * testsuite/gas/riscv/exact.s: Test exact mode basics.
>         * testsuite/gas/riscv/exact.d: Ditto.
>         * testsuite/gas/riscv/exact-branch-local.s: Test conditional
>         branches and unconditional jumps relative to a local symbol.
>         * testsuite/gas/riscv/exact-branch-local-noexact.d: Ditto.
>         * testsuite/gas/riscv/exact-branch-local-exact-ok.d: Ditto.
>         * testsuite/gas/riscv/exact-branch-local-exact-fail.d: Ditto.
>         * testsuite/gas/riscv/exact-branch-local-exact-fail.l: Ditto.
>         * testsuite/gas/riscv/exact-branch-extern.s: Test conditional
>         branches and unconditional jumps relative to an external symbol.
>         * testsuite/gas/riscv/exact-branch-extern-noexact.d: Ditto.
>         * testsuite/gas/riscv/exact-branch-extern-exact.d: Ditto.
>         * testsuite/gas/riscv/li32.s: Enable exact mode by external option.
>         * testsuite/gas/riscv/li64.s: Likewise.
>         * testsuite/gas/riscv/exact-li32.d: li32.d but enable exact mode
>     to make sure that no automatic instruction compression occurs.
>         * testsuite/gas/riscv/exact-li64.d: Likewise.
>         * testsuite/gas/riscv/no-relax-branch-offset-fail.s: Use exact
>         mode to test various configurations and instructions.
>         * testsuite/gas/riscv/no-relax-branch-offset-fail.d: Ditto.
>         * testsuite/gas/riscv/no-relax-branch-offset-fail.l: Ditto.
>
> include/ChangeLog:
>
>         * opcode/riscv.h (INSN_NON_EXACT): New flag to represent aliases
>         to reject on the exact mode.
>
> opcodes/ChangeLog:
>
>         * riscv-opc.c (riscv_opcodes): Add INSN_NON_EXACT flag to all
>         instructions that should be rejected on the exact mode.
> ---
>  gas/config/tc-riscv.c                         |  40 +++-
>  gas/doc/c-riscv.texi                          |  13 ++
>  .../gas/riscv/exact-branch-extern-exact.d     |  32 ++++
>  .../gas/riscv/exact-branch-extern-noexact.d   |  50 +++++
>  gas/testsuite/gas/riscv/exact-branch-extern.s |  40 ++++
>  .../gas/riscv/exact-branch-local-exact-fail.d |   3 +
>  .../gas/riscv/exact-branch-local-exact-fail.l |  43 +++++
>  .../gas/riscv/exact-branch-local-exact-ok.d   |  75 ++++++++
>  .../gas/riscv/exact-branch-local-noexact.d    | 149 +++++++++++++++
>  gas/testsuite/gas/riscv/exact-branch-local.s  | 138 ++++++++++++++
>  gas/testsuite/gas/riscv/exact-li32.d          |  18 ++
>  gas/testsuite/gas/riscv/exact-li64.d          |  45 +++++
>  gas/testsuite/gas/riscv/exact.d               |  15 ++
>  gas/testsuite/gas/riscv/exact.s               |  11 ++
>  gas/testsuite/gas/riscv/li32.s                |   3 +
>  gas/testsuite/gas/riscv/li64.s                |   3 +
>  .../gas/riscv/no-relax-branch-offset-fail.l   |   5 +-
>  .../gas/riscv/no-relax-branch-offset-fail.s   |  11 +-
>  include/opcode/riscv.h                        |  14 ++
>  opcodes/riscv-opc.c                           | 180 +++++++++---------
>  20 files changed, 784 insertions(+), 104 deletions(-)
>  create mode 100644 gas/testsuite/gas/riscv/exact-branch-extern-exact.d
>  create mode 100644 gas/testsuite/gas/riscv/exact-branch-extern-noexact.d
>  create mode 100644 gas/testsuite/gas/riscv/exact-branch-extern.s
>  create mode 100644 gas/testsuite/gas/riscv/exact-branch-local-exact-fail.d
>  create mode 100644 gas/testsuite/gas/riscv/exact-branch-local-exact-fail.l
>  create mode 100644 gas/testsuite/gas/riscv/exact-branch-local-exact-ok.d
>  create mode 100644 gas/testsuite/gas/riscv/exact-branch-local-noexact.d
>  create mode 100644 gas/testsuite/gas/riscv/exact-branch-local.s
>  create mode 100644 gas/testsuite/gas/riscv/exact-li32.d
>  create mode 100644 gas/testsuite/gas/riscv/exact-li64.d
>  create mode 100644 gas/testsuite/gas/riscv/exact.d
>  create mode 100644 gas/testsuite/gas/riscv/exact.s
>
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