[PATCH v2 1/3] aarch64: Fix typos in opcode headers

[Alice Carlotti]

On Fri, Jun 06, 2025 at 11:14:14AM +0100, Yury Khrustalev wrote:
> ---
>  include/opcode/aarch64.h | 8 ++++----
>  opcodes/aarch64-opc.h    | 4 ++--
>  2 files changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
> index df90bb76e56..8a19bec8dcc 100644
> --- a/include/opcode/aarch64.h
> +++ b/include/opcode/aarch64.h
> @@ -210,7 +210,7 @@ enum aarch64_feature_bit {
>    /* Instrumentation Extension.  */
>    AARCH64_FEATURE_ITE,
>    /* 128-bit page table descriptor, system registers
> -     and isntructions.  */
> +     and instructions.  */
>    AARCH64_FEATURE_D128,
>    /* Armv8.9-A/Armv9.4-A architecture Debug extension.  */
>    AARCH64_FEATURE_DEBUGv8p9,
> @@ -1395,7 +1395,7 @@ extern const aarch64_opcode aarch64_opcode_table[];
>  #define F_OPD_PAIR_OPT (1ULL << 32)
>  /* This instruction does not allow the full range of values that the
>     width of fields in the assembler instruction would theoretically
> -   allow.  This impacts the constraintts on assembly but yelds no
> +   allow.  This impacts the constraints on assembly but yields no
>     impact on disassembly.  */
>  #define F_OPD_NARROW (1ULL << 33)
>  /* For the instruction with size[22:23] field.  */
> @@ -1761,7 +1761,7 @@ struct aarch64_inst
>    /* Corresponding opcode entry.  */
>    const aarch64_opcode *opcode;
>  
> -  /* Condition for a truly conditional-executed instrutions, e.g. b.cond.  */
> +  /* Condition for a truly conditional-executed instructions, e.g. b.cond.  */

I think this should be "instruction" (singular).

Looks good otherwise.

>    const aarch64_cond *cond;
>  
>    /* Operands information.  */
> @@ -1861,7 +1861,7 @@ struct aarch64_inst
>       yet still accept a wider range of registers.
>  
>     AARCH64_OPDE_RECOVERABLE, AARCH64_OPDE_SYNTAX_ERROR and
> -   AARCH64_OPDE_FATAL_SYNTAX_ERROR are only deteced by GAS while the
> +   AARCH64_OPDE_FATAL_SYNTAX_ERROR are only detected by GAS while the
>     AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
>     only libopcodes has the information about the valid variants of each
>     instruction.
> diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h
> index 9ab9bdf5123..d2b556fdba6 100644
> --- a/opcodes/aarch64-opc.h
> +++ b/opcodes/aarch64-opc.h
> @@ -326,7 +326,7 @@ verify_constraints (const struct aarch64_inst *, const aarch64_insn, bfd_vma,
>  #define F_REG_ALIAS	(1 << 6)  /* Register name aliases another.  */
>  
>  #undef F_REG_128
> -#define F_REG_128	(1 << 7) /* System regsister implementable as 128-bit wide.  */
> +#define F_REG_128	(1 << 7) /* System register implementable as 128-bit wide.  */
>  
>  
>  /* PSTATE field name for the MSR instruction this is encoded in "op1:op2:CRm".
> @@ -602,7 +602,7 @@ select_operand_for_scalar_size_field_coding (const aarch64_opcode *opcode)
>      src_size = aarch64_get_qualifier_esize (opcode->qualifiers_list[0][1]);
>    if (src_size == dst_size && src_size == 0)
>      { assert (0); abort (); }
> -  /* When the result is not a sisd register or it is a long operantion.  */
> +  /* When the result is not a sisd register or it is a long operation.  */
>    if (dst_size == 0 || dst_size == src_size << 1)
>      return 1;
>    else
> -- 
> 2.39.5
>