[PATCH v3] aarch64: Support for FEAT_LSFE
Ezra.Sitorus@arm.com
Ezra.Sitorus@arm.com
Wed Jun 4 19:36:34 GMT 2025
From: Ezra Sitorus <ezra.sitorus@arm.com>
FEAT_LSFE - Large System Float Extension - implements A64 base atomic
floating-point in-memory instructions.
---
This version addresses Alice's comments from v2 by adding F_LSFE_SZ to
handle the size field. By doing this, I could use Fm/Fd for all the
instructions, and there's no more need for the aarch64_ins_fs,
aarch64_ext_fs functions, and the respective ft versions could go back
to normal.
Regression tested on aarch64-none-linux-gnu.
Ezra
gas/config/tc-aarch64.c | 1 +
gas/doc/c-aarch64.texi | 2 +
gas/testsuite/gas/aarch64/lsfe-bad.d | 4 +
gas/testsuite/gas/aarch64/lsfe-bad.l | 17 +
gas/testsuite/gas/aarch64/lsfe-bad.s | 6 +
gas/testsuite/gas/aarch64/lsfe.d | 815 +++++++++++++++++++++++++++
gas/testsuite/gas/aarch64/lsfe.s | 71 +++
include/opcode/aarch64.h | 6 +-
opcodes/aarch64-asm.c | 7 +
opcodes/aarch64-dis.c | 17 +
opcodes/aarch64-tbl.h | 108 ++++
11 files changed, 1053 insertions(+), 1 deletion(-)
create mode 100644 gas/testsuite/gas/aarch64/lsfe-bad.d
create mode 100644 gas/testsuite/gas/aarch64/lsfe-bad.l
create mode 100644 gas/testsuite/gas/aarch64/lsfe-bad.s
create mode 100644 gas/testsuite/gas/aarch64/lsfe.d
create mode 100644 gas/testsuite/gas/aarch64/lsfe.s
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index acb56044fb5..e577b39900e 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -10641,6 +10641,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
AARCH64_FEATURE (SIMD)},
{"fp", AARCH64_FEATURE (FP), AARCH64_NO_FEATURES},
{"lse", AARCH64_FEATURE (LSE), AARCH64_NO_FEATURES},
+ {"lsfe", AARCH64_FEATURE (LSFE), AARCH64_FEATURE (FP)},
{"lse128", AARCH64_FEATURE (LSE128), AARCH64_FEATURE (LSE)},
{"simd", AARCH64_FEATURE (SIMD), AARCH64_FEATURE (FP)},
{"pan", AARCH64_FEATURE (PAN), AARCH64_NO_FEATURES},
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index 10888d1e78f..13992cd6268 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -225,6 +225,8 @@ automatically cause those extensions to be disabled.
@tab Enable Large System extensions.
@item @code{lse128} @tab @code{lse}
@tab Enable the 128-bit Atomic Instructions extension.
+@item @code{lsfe} @tab @code{fp}
+ @tab Enable Large System Float Extension.
@item @code{lut} @tab
@tab Enable the Lookup Table (LUT) extension.
@item @code{memtag} @tab
diff --git a/gas/testsuite/gas/aarch64/lsfe-bad.d b/gas/testsuite/gas/aarch64/lsfe-bad.d
new file mode 100644
index 00000000000..d2bf4a8d746
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/lsfe-bad.d
@@ -0,0 +1,4 @@
+#name: Bad FEAT_LSFE instructions
+#source: lsfe-bad.s
+#as: -march=armv8-a+lsfe
+#error_output: lsfe-bad.l
diff --git a/gas/testsuite/gas/aarch64/lsfe-bad.l b/gas/testsuite/gas/aarch64/lsfe-bad.l
new file mode 100644
index 00000000000..b6937be5390
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/lsfe-bad.l
@@ -0,0 +1,17 @@
+
+.*: Assembler messages:
+.*: Error: operand mismatch -- `ldfadd h0,s1,\[x2\]'
+.*: Info: did you mean this\?
+.*: Info: ldfadd h0, h1, \[x2\]
+.*: Info: other valid variant\(s\):
+.*: Info: ldfadd s0, s1, \[x2\]
+.*: Info: ldfadd d0, d1, \[x2\]
+.*: Error: operand mismatch -- `ldbfadd s0,s1,\[x2\]'
+.*: Info: did you mean this\?
+.*: Info: ldbfadd h0, h1, \[x2\]
+.*: Error: expected a scalar SIMD or floating-point register at operand 1 -- `stfmax w0,w1,\[x2\]'
+.*: Error: unknown mnemonic `stfmaxa' -- `stfmaxa s0,s1,\[x2\]'
+.*: Error: unknown mnemonic `stfmaxal' -- `stfmaxal s0,s1,\[x2\]'
+.*: Error: operand mismatch -- `stbfmin s0,\[x2\]'
+.*: Info: did you mean this\?
+.*: Info: stbfmin h0, \[x2\]
diff --git a/gas/testsuite/gas/aarch64/lsfe-bad.s b/gas/testsuite/gas/aarch64/lsfe-bad.s
new file mode 100644
index 00000000000..2b4b1112819
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/lsfe-bad.s
@@ -0,0 +1,6 @@
+ ldfadd h0, s1, [x2]
+ ldbfadd s0, s1, [x2]
+ stfmax w0, w1, [x2]
+ stfmaxa s0, s1, [x2]
+ stfmaxal s0, s1, [x2]
+ stbfmin s0, [x2]
diff --git a/gas/testsuite/gas/aarch64/lsfe.d b/gas/testsuite/gas/aarch64/lsfe.d
new file mode 100644
index 00000000000..4a3ba97fc76
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/lsfe.d
@@ -0,0 +1,815 @@
+#name: FEAT_LSFE instructions
+#as: -march=armv8-a+lsfe
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+.* <ldf>:
+.*: 7c200000 ldfadd h0, h0, \[x0\]
+.*: 7c2003e0 ldfadd h0, h0, \[sp\]
+.*: 7c20001f ldfadd h0, h31, \[x0\]
+.*: 7c2003ff ldfadd h0, h31, \[sp\]
+.*: 7c3f0000 ldfadd h31, h0, \[x0\]
+.*: 7c3f03e0 ldfadd h31, h0, \[sp\]
+.*: 7c3f001f ldfadd h31, h31, \[x0\]
+.*: 7c3f03ff ldfadd h31, h31, \[sp\]
+.*: bc200000 ldfadd s0, s0, \[x0\]
+.*: bc2003e0 ldfadd s0, s0, \[sp\]
+.*: bc20001f ldfadd s0, s31, \[x0\]
+.*: bc2003ff ldfadd s0, s31, \[sp\]
+.*: bc3f0000 ldfadd s31, s0, \[x0\]
+.*: bc3f03e0 ldfadd s31, s0, \[sp\]
+.*: bc3f001f ldfadd s31, s31, \[x0\]
+.*: bc3f03ff ldfadd s31, s31, \[sp\]
+.*: fc200000 ldfadd d0, d0, \[x0\]
+.*: fc2003e0 ldfadd d0, d0, \[sp\]
+.*: fc20001f ldfadd d0, d31, \[x0\]
+.*: fc2003ff ldfadd d0, d31, \[sp\]
+.*: fc3f0000 ldfadd d31, d0, \[x0\]
+.*: fc3f03e0 ldfadd d31, d0, \[sp\]
+.*: fc3f001f ldfadd d31, d31, \[x0\]
+.*: fc3f03ff ldfadd d31, d31, \[sp\]
+.*: 7ca00000 ldfadda h0, h0, \[x0\]
+.*: 7ca003e0 ldfadda h0, h0, \[sp\]
+.*: 7ca0001f ldfadda h0, h31, \[x0\]
+.*: 7ca003ff ldfadda h0, h31, \[sp\]
+.*: 7cbf0000 ldfadda h31, h0, \[x0\]
+.*: 7cbf03e0 ldfadda h31, h0, \[sp\]
+.*: 7cbf001f ldfadda h31, h31, \[x0\]
+.*: 7cbf03ff ldfadda h31, h31, \[sp\]
+.*: bca00000 ldfadda s0, s0, \[x0\]
+.*: bca003e0 ldfadda s0, s0, \[sp\]
+.*: bca0001f ldfadda s0, s31, \[x0\]
+.*: bca003ff ldfadda s0, s31, \[sp\]
+.*: bcbf0000 ldfadda s31, s0, \[x0\]
+.*: bcbf03e0 ldfadda s31, s0, \[sp\]
+.*: bcbf001f ldfadda s31, s31, \[x0\]
+.*: bcbf03ff ldfadda s31, s31, \[sp\]
+.*: fca00000 ldfadda d0, d0, \[x0\]
+.*: fca003e0 ldfadda d0, d0, \[sp\]
+.*: fca0001f ldfadda d0, d31, \[x0\]
+.*: fca003ff ldfadda d0, d31, \[sp\]
+.*: fcbf0000 ldfadda d31, d0, \[x0\]
+.*: fcbf03e0 ldfadda d31, d0, \[sp\]
+.*: fcbf001f ldfadda d31, d31, \[x0\]
+.*: fcbf03ff ldfadda d31, d31, \[sp\]
+.*: 7ce00000 ldfaddal h0, h0, \[x0\]
+.*: 7ce003e0 ldfaddal h0, h0, \[sp\]
+.*: 7ce0001f ldfaddal h0, h31, \[x0\]
+.*: 7ce003ff ldfaddal h0, h31, \[sp\]
+.*: 7cff0000 ldfaddal h31, h0, \[x0\]
+.*: 7cff03e0 ldfaddal h31, h0, \[sp\]
+.*: 7cff001f ldfaddal h31, h31, \[x0\]
+.*: 7cff03ff ldfaddal h31, h31, \[sp\]
+.*: bce00000 ldfaddal s0, s0, \[x0\]
+.*: bce003e0 ldfaddal s0, s0, \[sp\]
+.*: bce0001f ldfaddal s0, s31, \[x0\]
+.*: bce003ff ldfaddal s0, s31, \[sp\]
+.*: bcff0000 ldfaddal s31, s0, \[x0\]
+.*: bcff03e0 ldfaddal s31, s0, \[sp\]
+.*: bcff001f ldfaddal s31, s31, \[x0\]
+.*: bcff03ff ldfaddal s31, s31, \[sp\]
+.*: fce00000 ldfaddal d0, d0, \[x0\]
+.*: fce003e0 ldfaddal d0, d0, \[sp\]
+.*: fce0001f ldfaddal d0, d31, \[x0\]
+.*: fce003ff ldfaddal d0, d31, \[sp\]
+.*: fcff0000 ldfaddal d31, d0, \[x0\]
+.*: fcff03e0 ldfaddal d31, d0, \[sp\]
+.*: fcff001f ldfaddal d31, d31, \[x0\]
+.*: fcff03ff ldfaddal d31, d31, \[sp\]
+.*: 7c600000 ldfaddl h0, h0, \[x0\]
+.*: 7c6003e0 ldfaddl h0, h0, \[sp\]
+.*: 7c60001f ldfaddl h0, h31, \[x0\]
+.*: 7c6003ff ldfaddl h0, h31, \[sp\]
+.*: 7c7f0000 ldfaddl h31, h0, \[x0\]
+.*: 7c7f03e0 ldfaddl h31, h0, \[sp\]
+.*: 7c7f001f ldfaddl h31, h31, \[x0\]
+.*: 7c7f03ff ldfaddl h31, h31, \[sp\]
+.*: bc600000 ldfaddl s0, s0, \[x0\]
+.*: bc6003e0 ldfaddl s0, s0, \[sp\]
+.*: bc60001f ldfaddl s0, s31, \[x0\]
+.*: bc6003ff ldfaddl s0, s31, \[sp\]
+.*: bc7f0000 ldfaddl s31, s0, \[x0\]
+.*: bc7f03e0 ldfaddl s31, s0, \[sp\]
+.*: bc7f001f ldfaddl s31, s31, \[x0\]
+.*: bc7f03ff ldfaddl s31, s31, \[sp\]
+.*: fc600000 ldfaddl d0, d0, \[x0\]
+.*: fc6003e0 ldfaddl d0, d0, \[sp\]
+.*: fc60001f ldfaddl d0, d31, \[x0\]
+.*: fc6003ff ldfaddl d0, d31, \[sp\]
+.*: fc7f0000 ldfaddl d31, d0, \[x0\]
+.*: fc7f03e0 ldfaddl d31, d0, \[sp\]
+.*: fc7f001f ldfaddl d31, d31, \[x0\]
+.*: fc7f03ff ldfaddl d31, d31, \[sp\]
+.*: 7c204000 ldfmax h0, h0, \[x0\]
+.*: 7c2043e0 ldfmax h0, h0, \[sp\]
+.*: 7c20401f ldfmax h0, h31, \[x0\]
+.*: 7c2043ff ldfmax h0, h31, \[sp\]
+.*: 7c3f4000 ldfmax h31, h0, \[x0\]
+.*: 7c3f43e0 ldfmax h31, h0, \[sp\]
+.*: 7c3f401f ldfmax h31, h31, \[x0\]
+.*: 7c3f43ff ldfmax h31, h31, \[sp\]
+.*: bc204000 ldfmax s0, s0, \[x0\]
+.*: bc2043e0 ldfmax s0, s0, \[sp\]
+.*: bc20401f ldfmax s0, s31, \[x0\]
+.*: bc2043ff ldfmax s0, s31, \[sp\]
+.*: bc3f4000 ldfmax s31, s0, \[x0\]
+.*: bc3f43e0 ldfmax s31, s0, \[sp\]
+.*: bc3f401f ldfmax s31, s31, \[x0\]
+.*: bc3f43ff ldfmax s31, s31, \[sp\]
+.*: fc204000 ldfmax d0, d0, \[x0\]
+.*: fc2043e0 ldfmax d0, d0, \[sp\]
+.*: fc20401f ldfmax d0, d31, \[x0\]
+.*: fc2043ff ldfmax d0, d31, \[sp\]
+.*: fc3f4000 ldfmax d31, d0, \[x0\]
+.*: fc3f43e0 ldfmax d31, d0, \[sp\]
+.*: fc3f401f ldfmax d31, d31, \[x0\]
+.*: fc3f43ff ldfmax d31, d31, \[sp\]
+.*: 7ca04000 ldfmaxa h0, h0, \[x0\]
+.*: 7ca043e0 ldfmaxa h0, h0, \[sp\]
+.*: 7ca0401f ldfmaxa h0, h31, \[x0\]
+.*: 7ca043ff ldfmaxa h0, h31, \[sp\]
+.*: 7cbf4000 ldfmaxa h31, h0, \[x0\]
+.*: 7cbf43e0 ldfmaxa h31, h0, \[sp\]
+.*: 7cbf401f ldfmaxa h31, h31, \[x0\]
+.*: 7cbf43ff ldfmaxa h31, h31, \[sp\]
+.*: bca04000 ldfmaxa s0, s0, \[x0\]
+.*: bca043e0 ldfmaxa s0, s0, \[sp\]
+.*: bca0401f ldfmaxa s0, s31, \[x0\]
+.*: bca043ff ldfmaxa s0, s31, \[sp\]
+.*: bcbf4000 ldfmaxa s31, s0, \[x0\]
+.*: bcbf43e0 ldfmaxa s31, s0, \[sp\]
+.*: bcbf401f ldfmaxa s31, s31, \[x0\]
+.*: bcbf43ff ldfmaxa s31, s31, \[sp\]
+.*: fca04000 ldfmaxa d0, d0, \[x0\]
+.*: fca043e0 ldfmaxa d0, d0, \[sp\]
+.*: fca0401f ldfmaxa d0, d31, \[x0\]
+.*: fca043ff ldfmaxa d0, d31, \[sp\]
+.*: fcbf4000 ldfmaxa d31, d0, \[x0\]
+.*: fcbf43e0 ldfmaxa d31, d0, \[sp\]
+.*: fcbf401f ldfmaxa d31, d31, \[x0\]
+.*: fcbf43ff ldfmaxa d31, d31, \[sp\]
+.*: 7ce04000 ldfmaxal h0, h0, \[x0\]
+.*: 7ce043e0 ldfmaxal h0, h0, \[sp\]
+.*: 7ce0401f ldfmaxal h0, h31, \[x0\]
+.*: 7ce043ff ldfmaxal h0, h31, \[sp\]
+.*: 7cff4000 ldfmaxal h31, h0, \[x0\]
+.*: 7cff43e0 ldfmaxal h31, h0, \[sp\]
+.*: 7cff401f ldfmaxal h31, h31, \[x0\]
+.*: 7cff43ff ldfmaxal h31, h31, \[sp\]
+.*: bce04000 ldfmaxal s0, s0, \[x0\]
+.*: bce043e0 ldfmaxal s0, s0, \[sp\]
+.*: bce0401f ldfmaxal s0, s31, \[x0\]
+.*: bce043ff ldfmaxal s0, s31, \[sp\]
+.*: bcff4000 ldfmaxal s31, s0, \[x0\]
+.*: bcff43e0 ldfmaxal s31, s0, \[sp\]
+.*: bcff401f ldfmaxal s31, s31, \[x0\]
+.*: bcff43ff ldfmaxal s31, s31, \[sp\]
+.*: fce04000 ldfmaxal d0, d0, \[x0\]
+.*: fce043e0 ldfmaxal d0, d0, \[sp\]
+.*: fce0401f ldfmaxal d0, d31, \[x0\]
+.*: fce043ff ldfmaxal d0, d31, \[sp\]
+.*: fcff4000 ldfmaxal d31, d0, \[x0\]
+.*: fcff43e0 ldfmaxal d31, d0, \[sp\]
+.*: fcff401f ldfmaxal d31, d31, \[x0\]
+.*: fcff43ff ldfmaxal d31, d31, \[sp\]
+.*: 7c604000 ldfmaxl h0, h0, \[x0\]
+.*: 7c6043e0 ldfmaxl h0, h0, \[sp\]
+.*: 7c60401f ldfmaxl h0, h31, \[x0\]
+.*: 7c6043ff ldfmaxl h0, h31, \[sp\]
+.*: 7c7f4000 ldfmaxl h31, h0, \[x0\]
+.*: 7c7f43e0 ldfmaxl h31, h0, \[sp\]
+.*: 7c7f401f ldfmaxl h31, h31, \[x0\]
+.*: 7c7f43ff ldfmaxl h31, h31, \[sp\]
+.*: bc604000 ldfmaxl s0, s0, \[x0\]
+.*: bc6043e0 ldfmaxl s0, s0, \[sp\]
+.*: bc60401f ldfmaxl s0, s31, \[x0\]
+.*: bc6043ff ldfmaxl s0, s31, \[sp\]
+.*: bc7f4000 ldfmaxl s31, s0, \[x0\]
+.*: bc7f43e0 ldfmaxl s31, s0, \[sp\]
+.*: bc7f401f ldfmaxl s31, s31, \[x0\]
+.*: bc7f43ff ldfmaxl s31, s31, \[sp\]
+.*: fc604000 ldfmaxl d0, d0, \[x0\]
+.*: fc6043e0 ldfmaxl d0, d0, \[sp\]
+.*: fc60401f ldfmaxl d0, d31, \[x0\]
+.*: fc6043ff ldfmaxl d0, d31, \[sp\]
+.*: fc7f4000 ldfmaxl d31, d0, \[x0\]
+.*: fc7f43e0 ldfmaxl d31, d0, \[sp\]
+.*: fc7f401f ldfmaxl d31, d31, \[x0\]
+.*: fc7f43ff ldfmaxl d31, d31, \[sp\]
+.*: 7c206000 ldfmaxnm h0, h0, \[x0\]
+.*: 7c2063e0 ldfmaxnm h0, h0, \[sp\]
+.*: 7c20601f ldfmaxnm h0, h31, \[x0\]
+.*: 7c2063ff ldfmaxnm h0, h31, \[sp\]
+.*: 7c3f6000 ldfmaxnm h31, h0, \[x0\]
+.*: 7c3f63e0 ldfmaxnm h31, h0, \[sp\]
+.*: 7c3f601f ldfmaxnm h31, h31, \[x0\]
+.*: 7c3f63ff ldfmaxnm h31, h31, \[sp\]
+.*: bc206000 ldfmaxnm s0, s0, \[x0\]
+.*: bc2063e0 ldfmaxnm s0, s0, \[sp\]
+.*: bc20601f ldfmaxnm s0, s31, \[x0\]
+.*: bc2063ff ldfmaxnm s0, s31, \[sp\]
+.*: bc3f6000 ldfmaxnm s31, s0, \[x0\]
+.*: bc3f63e0 ldfmaxnm s31, s0, \[sp\]
+.*: bc3f601f ldfmaxnm s31, s31, \[x0\]
+.*: bc3f63ff ldfmaxnm s31, s31, \[sp\]
+.*: fc206000 ldfmaxnm d0, d0, \[x0\]
+.*: fc2063e0 ldfmaxnm d0, d0, \[sp\]
+.*: fc20601f ldfmaxnm d0, d31, \[x0\]
+.*: fc2063ff ldfmaxnm d0, d31, \[sp\]
+.*: fc3f6000 ldfmaxnm d31, d0, \[x0\]
+.*: fc3f63e0 ldfmaxnm d31, d0, \[sp\]
+.*: fc3f601f ldfmaxnm d31, d31, \[x0\]
+.*: fc3f63ff ldfmaxnm d31, d31, \[sp\]
+.*: 7ca06000 ldfmaxnma h0, h0, \[x0\]
+.*: 7ca063e0 ldfmaxnma h0, h0, \[sp\]
+.*: 7ca0601f ldfmaxnma h0, h31, \[x0\]
+.*: 7ca063ff ldfmaxnma h0, h31, \[sp\]
+.*: 7cbf6000 ldfmaxnma h31, h0, \[x0\]
+.*: 7cbf63e0 ldfmaxnma h31, h0, \[sp\]
+.*: 7cbf601f ldfmaxnma h31, h31, \[x0\]
+.*: 7cbf63ff ldfmaxnma h31, h31, \[sp\]
+.*: bca06000 ldfmaxnma s0, s0, \[x0\]
+.*: bca063e0 ldfmaxnma s0, s0, \[sp\]
+.*: bca0601f ldfmaxnma s0, s31, \[x0\]
+.*: bca063ff ldfmaxnma s0, s31, \[sp\]
+.*: bcbf6000 ldfmaxnma s31, s0, \[x0\]
+.*: bcbf63e0 ldfmaxnma s31, s0, \[sp\]
+.*: bcbf601f ldfmaxnma s31, s31, \[x0\]
+.*: bcbf63ff ldfmaxnma s31, s31, \[sp\]
+.*: fca06000 ldfmaxnma d0, d0, \[x0\]
+.*: fca063e0 ldfmaxnma d0, d0, \[sp\]
+.*: fca0601f ldfmaxnma d0, d31, \[x0\]
+.*: fca063ff ldfmaxnma d0, d31, \[sp\]
+.*: fcbf6000 ldfmaxnma d31, d0, \[x0\]
+.*: fcbf63e0 ldfmaxnma d31, d0, \[sp\]
+.*: fcbf601f ldfmaxnma d31, d31, \[x0\]
+.*: fcbf63ff ldfmaxnma d31, d31, \[sp\]
+.*: 7ce06000 ldfmaxnmal h0, h0, \[x0\]
+.*: 7ce063e0 ldfmaxnmal h0, h0, \[sp\]
+.*: 7ce0601f ldfmaxnmal h0, h31, \[x0\]
+.*: 7ce063ff ldfmaxnmal h0, h31, \[sp\]
+.*: 7cff6000 ldfmaxnmal h31, h0, \[x0\]
+.*: 7cff63e0 ldfmaxnmal h31, h0, \[sp\]
+.*: 7cff601f ldfmaxnmal h31, h31, \[x0\]
+.*: 7cff63ff ldfmaxnmal h31, h31, \[sp\]
+.*: bce06000 ldfmaxnmal s0, s0, \[x0\]
+.*: bce063e0 ldfmaxnmal s0, s0, \[sp\]
+.*: bce0601f ldfmaxnmal s0, s31, \[x0\]
+.*: bce063ff ldfmaxnmal s0, s31, \[sp\]
+.*: bcff6000 ldfmaxnmal s31, s0, \[x0\]
+.*: bcff63e0 ldfmaxnmal s31, s0, \[sp\]
+.*: bcff601f ldfmaxnmal s31, s31, \[x0\]
+.*: bcff63ff ldfmaxnmal s31, s31, \[sp\]
+.*: fce06000 ldfmaxnmal d0, d0, \[x0\]
+.*: fce063e0 ldfmaxnmal d0, d0, \[sp\]
+.*: fce0601f ldfmaxnmal d0, d31, \[x0\]
+.*: fce063ff ldfmaxnmal d0, d31, \[sp\]
+.*: fcff6000 ldfmaxnmal d31, d0, \[x0\]
+.*: fcff63e0 ldfmaxnmal d31, d0, \[sp\]
+.*: fcff601f ldfmaxnmal d31, d31, \[x0\]
+.*: fcff63ff ldfmaxnmal d31, d31, \[sp\]
+.*: 7c606000 ldfmaxnml h0, h0, \[x0\]
+.*: 7c6063e0 ldfmaxnml h0, h0, \[sp\]
+.*: 7c60601f ldfmaxnml h0, h31, \[x0\]
+.*: 7c6063ff ldfmaxnml h0, h31, \[sp\]
+.*: 7c7f6000 ldfmaxnml h31, h0, \[x0\]
+.*: 7c7f63e0 ldfmaxnml h31, h0, \[sp\]
+.*: 7c7f601f ldfmaxnml h31, h31, \[x0\]
+.*: 7c7f63ff ldfmaxnml h31, h31, \[sp\]
+.*: bc606000 ldfmaxnml s0, s0, \[x0\]
+.*: bc6063e0 ldfmaxnml s0, s0, \[sp\]
+.*: bc60601f ldfmaxnml s0, s31, \[x0\]
+.*: bc6063ff ldfmaxnml s0, s31, \[sp\]
+.*: bc7f6000 ldfmaxnml s31, s0, \[x0\]
+.*: bc7f63e0 ldfmaxnml s31, s0, \[sp\]
+.*: bc7f601f ldfmaxnml s31, s31, \[x0\]
+.*: bc7f63ff ldfmaxnml s31, s31, \[sp\]
+.*: fc606000 ldfmaxnml d0, d0, \[x0\]
+.*: fc6063e0 ldfmaxnml d0, d0, \[sp\]
+.*: fc60601f ldfmaxnml d0, d31, \[x0\]
+.*: fc6063ff ldfmaxnml d0, d31, \[sp\]
+.*: fc7f6000 ldfmaxnml d31, d0, \[x0\]
+.*: fc7f63e0 ldfmaxnml d31, d0, \[sp\]
+.*: fc7f601f ldfmaxnml d31, d31, \[x0\]
+.*: fc7f63ff ldfmaxnml d31, d31, \[sp\]
+.*: 7c205000 ldfmin h0, h0, \[x0\]
+.*: 7c2053e0 ldfmin h0, h0, \[sp\]
+.*: 7c20501f ldfmin h0, h31, \[x0\]
+.*: 7c2053ff ldfmin h0, h31, \[sp\]
+.*: 7c3f5000 ldfmin h31, h0, \[x0\]
+.*: 7c3f53e0 ldfmin h31, h0, \[sp\]
+.*: 7c3f501f ldfmin h31, h31, \[x0\]
+.*: 7c3f53ff ldfmin h31, h31, \[sp\]
+.*: bc205000 ldfmin s0, s0, \[x0\]
+.*: bc2053e0 ldfmin s0, s0, \[sp\]
+.*: bc20501f ldfmin s0, s31, \[x0\]
+.*: bc2053ff ldfmin s0, s31, \[sp\]
+.*: bc3f5000 ldfmin s31, s0, \[x0\]
+.*: bc3f53e0 ldfmin s31, s0, \[sp\]
+.*: bc3f501f ldfmin s31, s31, \[x0\]
+.*: bc3f53ff ldfmin s31, s31, \[sp\]
+.*: fc205000 ldfmin d0, d0, \[x0\]
+.*: fc2053e0 ldfmin d0, d0, \[sp\]
+.*: fc20501f ldfmin d0, d31, \[x0\]
+.*: fc2053ff ldfmin d0, d31, \[sp\]
+.*: fc3f5000 ldfmin d31, d0, \[x0\]
+.*: fc3f53e0 ldfmin d31, d0, \[sp\]
+.*: fc3f501f ldfmin d31, d31, \[x0\]
+.*: fc3f53ff ldfmin d31, d31, \[sp\]
+.*: 7ca05000 ldfmina h0, h0, \[x0\]
+.*: 7ca053e0 ldfmina h0, h0, \[sp\]
+.*: 7ca0501f ldfmina h0, h31, \[x0\]
+.*: 7ca053ff ldfmina h0, h31, \[sp\]
+.*: 7cbf5000 ldfmina h31, h0, \[x0\]
+.*: 7cbf53e0 ldfmina h31, h0, \[sp\]
+.*: 7cbf501f ldfmina h31, h31, \[x0\]
+.*: 7cbf53ff ldfmina h31, h31, \[sp\]
+.*: bca05000 ldfmina s0, s0, \[x0\]
+.*: bca053e0 ldfmina s0, s0, \[sp\]
+.*: bca0501f ldfmina s0, s31, \[x0\]
+.*: bca053ff ldfmina s0, s31, \[sp\]
+.*: bcbf5000 ldfmina s31, s0, \[x0\]
+.*: bcbf53e0 ldfmina s31, s0, \[sp\]
+.*: bcbf501f ldfmina s31, s31, \[x0\]
+.*: bcbf53ff ldfmina s31, s31, \[sp\]
+.*: fca05000 ldfmina d0, d0, \[x0\]
+.*: fca053e0 ldfmina d0, d0, \[sp\]
+.*: fca0501f ldfmina d0, d31, \[x0\]
+.*: fca053ff ldfmina d0, d31, \[sp\]
+.*: fcbf5000 ldfmina d31, d0, \[x0\]
+.*: fcbf53e0 ldfmina d31, d0, \[sp\]
+.*: fcbf501f ldfmina d31, d31, \[x0\]
+.*: fcbf53ff ldfmina d31, d31, \[sp\]
+.*: 7ce05000 ldfminal h0, h0, \[x0\]
+.*: 7ce053e0 ldfminal h0, h0, \[sp\]
+.*: 7ce0501f ldfminal h0, h31, \[x0\]
+.*: 7ce053ff ldfminal h0, h31, \[sp\]
+.*: 7cff5000 ldfminal h31, h0, \[x0\]
+.*: 7cff53e0 ldfminal h31, h0, \[sp\]
+.*: 7cff501f ldfminal h31, h31, \[x0\]
+.*: 7cff53ff ldfminal h31, h31, \[sp\]
+.*: bce05000 ldfminal s0, s0, \[x0\]
+.*: bce053e0 ldfminal s0, s0, \[sp\]
+.*: bce0501f ldfminal s0, s31, \[x0\]
+.*: bce053ff ldfminal s0, s31, \[sp\]
+.*: bcff5000 ldfminal s31, s0, \[x0\]
+.*: bcff53e0 ldfminal s31, s0, \[sp\]
+.*: bcff501f ldfminal s31, s31, \[x0\]
+.*: bcff53ff ldfminal s31, s31, \[sp\]
+.*: fce05000 ldfminal d0, d0, \[x0\]
+.*: fce053e0 ldfminal d0, d0, \[sp\]
+.*: fce0501f ldfminal d0, d31, \[x0\]
+.*: fce053ff ldfminal d0, d31, \[sp\]
+.*: fcff5000 ldfminal d31, d0, \[x0\]
+.*: fcff53e0 ldfminal d31, d0, \[sp\]
+.*: fcff501f ldfminal d31, d31, \[x0\]
+.*: fcff53ff ldfminal d31, d31, \[sp\]
+.*: 7c605000 ldfminl h0, h0, \[x0\]
+.*: 7c6053e0 ldfminl h0, h0, \[sp\]
+.*: 7c60501f ldfminl h0, h31, \[x0\]
+.*: 7c6053ff ldfminl h0, h31, \[sp\]
+.*: 7c7f5000 ldfminl h31, h0, \[x0\]
+.*: 7c7f53e0 ldfminl h31, h0, \[sp\]
+.*: 7c7f501f ldfminl h31, h31, \[x0\]
+.*: 7c7f53ff ldfminl h31, h31, \[sp\]
+.*: bc605000 ldfminl s0, s0, \[x0\]
+.*: bc6053e0 ldfminl s0, s0, \[sp\]
+.*: bc60501f ldfminl s0, s31, \[x0\]
+.*: bc6053ff ldfminl s0, s31, \[sp\]
+.*: bc7f5000 ldfminl s31, s0, \[x0\]
+.*: bc7f53e0 ldfminl s31, s0, \[sp\]
+.*: bc7f501f ldfminl s31, s31, \[x0\]
+.*: bc7f53ff ldfminl s31, s31, \[sp\]
+.*: fc605000 ldfminl d0, d0, \[x0\]
+.*: fc6053e0 ldfminl d0, d0, \[sp\]
+.*: fc60501f ldfminl d0, d31, \[x0\]
+.*: fc6053ff ldfminl d0, d31, \[sp\]
+.*: fc7f5000 ldfminl d31, d0, \[x0\]
+.*: fc7f53e0 ldfminl d31, d0, \[sp\]
+.*: fc7f501f ldfminl d31, d31, \[x0\]
+.*: fc7f53ff ldfminl d31, d31, \[sp\]
+.*: 7c207000 ldfminnm h0, h0, \[x0\]
+.*: 7c2073e0 ldfminnm h0, h0, \[sp\]
+.*: 7c20701f ldfminnm h0, h31, \[x0\]
+.*: 7c2073ff ldfminnm h0, h31, \[sp\]
+.*: 7c3f7000 ldfminnm h31, h0, \[x0\]
+.*: 7c3f73e0 ldfminnm h31, h0, \[sp\]
+.*: 7c3f701f ldfminnm h31, h31, \[x0\]
+.*: 7c3f73ff ldfminnm h31, h31, \[sp\]
+.*: bc207000 ldfminnm s0, s0, \[x0\]
+.*: bc2073e0 ldfminnm s0, s0, \[sp\]
+.*: bc20701f ldfminnm s0, s31, \[x0\]
+.*: bc2073ff ldfminnm s0, s31, \[sp\]
+.*: bc3f7000 ldfminnm s31, s0, \[x0\]
+.*: bc3f73e0 ldfminnm s31, s0, \[sp\]
+.*: bc3f701f ldfminnm s31, s31, \[x0\]
+.*: bc3f73ff ldfminnm s31, s31, \[sp\]
+.*: fc207000 ldfminnm d0, d0, \[x0\]
+.*: fc2073e0 ldfminnm d0, d0, \[sp\]
+.*: fc20701f ldfminnm d0, d31, \[x0\]
+.*: fc2073ff ldfminnm d0, d31, \[sp\]
+.*: fc3f7000 ldfminnm d31, d0, \[x0\]
+.*: fc3f73e0 ldfminnm d31, d0, \[sp\]
+.*: fc3f701f ldfminnm d31, d31, \[x0\]
+.*: fc3f73ff ldfminnm d31, d31, \[sp\]
+.*: 7ca07000 ldfminnma h0, h0, \[x0\]
+.*: 7ca073e0 ldfminnma h0, h0, \[sp\]
+.*: 7ca0701f ldfminnma h0, h31, \[x0\]
+.*: 7ca073ff ldfminnma h0, h31, \[sp\]
+.*: 7cbf7000 ldfminnma h31, h0, \[x0\]
+.*: 7cbf73e0 ldfminnma h31, h0, \[sp\]
+.*: 7cbf701f ldfminnma h31, h31, \[x0\]
+.*: 7cbf73ff ldfminnma h31, h31, \[sp\]
+.*: bca07000 ldfminnma s0, s0, \[x0\]
+.*: bca073e0 ldfminnma s0, s0, \[sp\]
+.*: bca0701f ldfminnma s0, s31, \[x0\]
+.*: bca073ff ldfminnma s0, s31, \[sp\]
+.*: bcbf7000 ldfminnma s31, s0, \[x0\]
+.*: bcbf73e0 ldfminnma s31, s0, \[sp\]
+.*: bcbf701f ldfminnma s31, s31, \[x0\]
+.*: bcbf73ff ldfminnma s31, s31, \[sp\]
+.*: fca07000 ldfminnma d0, d0, \[x0\]
+.*: fca073e0 ldfminnma d0, d0, \[sp\]
+.*: fca0701f ldfminnma d0, d31, \[x0\]
+.*: fca073ff ldfminnma d0, d31, \[sp\]
+.*: fcbf7000 ldfminnma d31, d0, \[x0\]
+.*: fcbf73e0 ldfminnma d31, d0, \[sp\]
+.*: fcbf701f ldfminnma d31, d31, \[x0\]
+.*: fcbf73ff ldfminnma d31, d31, \[sp\]
+.*: 7ce07000 ldfminnmal h0, h0, \[x0\]
+.*: 7ce073e0 ldfminnmal h0, h0, \[sp\]
+.*: 7ce0701f ldfminnmal h0, h31, \[x0\]
+.*: 7ce073ff ldfminnmal h0, h31, \[sp\]
+.*: 7cff7000 ldfminnmal h31, h0, \[x0\]
+.*: 7cff73e0 ldfminnmal h31, h0, \[sp\]
+.*: 7cff701f ldfminnmal h31, h31, \[x0\]
+.*: 7cff73ff ldfminnmal h31, h31, \[sp\]
+.*: bce07000 ldfminnmal s0, s0, \[x0\]
+.*: bce073e0 ldfminnmal s0, s0, \[sp\]
+.*: bce0701f ldfminnmal s0, s31, \[x0\]
+.*: bce073ff ldfminnmal s0, s31, \[sp\]
+.*: bcff7000 ldfminnmal s31, s0, \[x0\]
+.*: bcff73e0 ldfminnmal s31, s0, \[sp\]
+.*: bcff701f ldfminnmal s31, s31, \[x0\]
+.*: bcff73ff ldfminnmal s31, s31, \[sp\]
+.*: fce07000 ldfminnmal d0, d0, \[x0\]
+.*: fce073e0 ldfminnmal d0, d0, \[sp\]
+.*: fce0701f ldfminnmal d0, d31, \[x0\]
+.*: fce073ff ldfminnmal d0, d31, \[sp\]
+.*: fcff7000 ldfminnmal d31, d0, \[x0\]
+.*: fcff73e0 ldfminnmal d31, d0, \[sp\]
+.*: fcff701f ldfminnmal d31, d31, \[x0\]
+.*: fcff73ff ldfminnmal d31, d31, \[sp\]
+.*: 7c607000 ldfminnml h0, h0, \[x0\]
+.*: 7c6073e0 ldfminnml h0, h0, \[sp\]
+.*: 7c60701f ldfminnml h0, h31, \[x0\]
+.*: 7c6073ff ldfminnml h0, h31, \[sp\]
+.*: 7c7f7000 ldfminnml h31, h0, \[x0\]
+.*: 7c7f73e0 ldfminnml h31, h0, \[sp\]
+.*: 7c7f701f ldfminnml h31, h31, \[x0\]
+.*: 7c7f73ff ldfminnml h31, h31, \[sp\]
+.*: bc607000 ldfminnml s0, s0, \[x0\]
+.*: bc6073e0 ldfminnml s0, s0, \[sp\]
+.*: bc60701f ldfminnml s0, s31, \[x0\]
+.*: bc6073ff ldfminnml s0, s31, \[sp\]
+.*: bc7f7000 ldfminnml s31, s0, \[x0\]
+.*: bc7f73e0 ldfminnml s31, s0, \[sp\]
+.*: bc7f701f ldfminnml s31, s31, \[x0\]
+.*: bc7f73ff ldfminnml s31, s31, \[sp\]
+.*: fc607000 ldfminnml d0, d0, \[x0\]
+.*: fc6073e0 ldfminnml d0, d0, \[sp\]
+.*: fc60701f ldfminnml d0, d31, \[x0\]
+.*: fc6073ff ldfminnml d0, d31, \[sp\]
+.*: fc7f7000 ldfminnml d31, d0, \[x0\]
+.*: fc7f73e0 ldfminnml d31, d0, \[sp\]
+.*: fc7f701f ldfminnml d31, d31, \[x0\]
+.*: fc7f73ff ldfminnml d31, d31, \[sp\]
+
+.* <ldbf>:
+.*: 3c200000 ldbfadd h0, h0, \[x0\]
+.*: 3c2003e0 ldbfadd h0, h0, \[sp\]
+.*: 3c20001f ldbfadd h0, h31, \[x0\]
+.*: 3c2003ff ldbfadd h0, h31, \[sp\]
+.*: 3c3f0000 ldbfadd h31, h0, \[x0\]
+.*: 3c3f03e0 ldbfadd h31, h0, \[sp\]
+.*: 3c3f001f ldbfadd h31, h31, \[x0\]
+.*: 3c3f03ff ldbfadd h31, h31, \[sp\]
+.*: 3ca00000 ldbfadda h0, h0, \[x0\]
+.*: 3ca003e0 ldbfadda h0, h0, \[sp\]
+.*: 3ca0001f ldbfadda h0, h31, \[x0\]
+.*: 3ca003ff ldbfadda h0, h31, \[sp\]
+.*: 3cbf0000 ldbfadda h31, h0, \[x0\]
+.*: 3cbf03e0 ldbfadda h31, h0, \[sp\]
+.*: 3cbf001f ldbfadda h31, h31, \[x0\]
+.*: 3cbf03ff ldbfadda h31, h31, \[sp\]
+.*: 3ce00000 ldbfaddal h0, h0, \[x0\]
+.*: 3ce003e0 ldbfaddal h0, h0, \[sp\]
+.*: 3ce0001f ldbfaddal h0, h31, \[x0\]
+.*: 3ce003ff ldbfaddal h0, h31, \[sp\]
+.*: 3cff0000 ldbfaddal h31, h0, \[x0\]
+.*: 3cff03e0 ldbfaddal h31, h0, \[sp\]
+.*: 3cff001f ldbfaddal h31, h31, \[x0\]
+.*: 3cff03ff ldbfaddal h31, h31, \[sp\]
+.*: 3c600000 ldbfaddl h0, h0, \[x0\]
+.*: 3c6003e0 ldbfaddl h0, h0, \[sp\]
+.*: 3c60001f ldbfaddl h0, h31, \[x0\]
+.*: 3c6003ff ldbfaddl h0, h31, \[sp\]
+.*: 3c7f0000 ldbfaddl h31, h0, \[x0\]
+.*: 3c7f03e0 ldbfaddl h31, h0, \[sp\]
+.*: 3c7f001f ldbfaddl h31, h31, \[x0\]
+.*: 3c7f03ff ldbfaddl h31, h31, \[sp\]
+.*: 3c204000 ldbfmax h0, h0, \[x0\]
+.*: 3c2043e0 ldbfmax h0, h0, \[sp\]
+.*: 3c20401f ldbfmax h0, h31, \[x0\]
+.*: 3c2043ff ldbfmax h0, h31, \[sp\]
+.*: 3c3f4000 ldbfmax h31, h0, \[x0\]
+.*: 3c3f43e0 ldbfmax h31, h0, \[sp\]
+.*: 3c3f401f ldbfmax h31, h31, \[x0\]
+.*: 3c3f43ff ldbfmax h31, h31, \[sp\]
+.*: 3ca04000 ldbfmaxa h0, h0, \[x0\]
+.*: 3ca043e0 ldbfmaxa h0, h0, \[sp\]
+.*: 3ca0401f ldbfmaxa h0, h31, \[x0\]
+.*: 3ca043ff ldbfmaxa h0, h31, \[sp\]
+.*: 3cbf4000 ldbfmaxa h31, h0, \[x0\]
+.*: 3cbf43e0 ldbfmaxa h31, h0, \[sp\]
+.*: 3cbf401f ldbfmaxa h31, h31, \[x0\]
+.*: 3cbf43ff ldbfmaxa h31, h31, \[sp\]
+.*: 3ce04000 ldbfmaxal h0, h0, \[x0\]
+.*: 3ce043e0 ldbfmaxal h0, h0, \[sp\]
+.*: 3ce0401f ldbfmaxal h0, h31, \[x0\]
+.*: 3ce043ff ldbfmaxal h0, h31, \[sp\]
+.*: 3cff4000 ldbfmaxal h31, h0, \[x0\]
+.*: 3cff43e0 ldbfmaxal h31, h0, \[sp\]
+.*: 3cff401f ldbfmaxal h31, h31, \[x0\]
+.*: 3cff43ff ldbfmaxal h31, h31, \[sp\]
+.*: 3c604000 ldbfmaxl h0, h0, \[x0\]
+.*: 3c6043e0 ldbfmaxl h0, h0, \[sp\]
+.*: 3c60401f ldbfmaxl h0, h31, \[x0\]
+.*: 3c6043ff ldbfmaxl h0, h31, \[sp\]
+.*: 3c7f4000 ldbfmaxl h31, h0, \[x0\]
+.*: 3c7f43e0 ldbfmaxl h31, h0, \[sp\]
+.*: 3c7f401f ldbfmaxl h31, h31, \[x0\]
+.*: 3c7f43ff ldbfmaxl h31, h31, \[sp\]
+.*: 3c206000 ldbfmaxnm h0, h0, \[x0\]
+.*: 3c2063e0 ldbfmaxnm h0, h0, \[sp\]
+.*: 3c20601f ldbfmaxnm h0, h31, \[x0\]
+.*: 3c2063ff ldbfmaxnm h0, h31, \[sp\]
+.*: 3c3f6000 ldbfmaxnm h31, h0, \[x0\]
+.*: 3c3f63e0 ldbfmaxnm h31, h0, \[sp\]
+.*: 3c3f601f ldbfmaxnm h31, h31, \[x0\]
+.*: 3c3f63ff ldbfmaxnm h31, h31, \[sp\]
+.*: 3ca06000 ldbfmaxnma h0, h0, \[x0\]
+.*: 3ca063e0 ldbfmaxnma h0, h0, \[sp\]
+.*: 3ca0601f ldbfmaxnma h0, h31, \[x0\]
+.*: 3ca063ff ldbfmaxnma h0, h31, \[sp\]
+.*: 3cbf6000 ldbfmaxnma h31, h0, \[x0\]
+.*: 3cbf63e0 ldbfmaxnma h31, h0, \[sp\]
+.*: 3cbf601f ldbfmaxnma h31, h31, \[x0\]
+.*: 3cbf63ff ldbfmaxnma h31, h31, \[sp\]
+.*: 3ce06000 ldbfmaxnmal h0, h0, \[x0\]
+.*: 3ce063e0 ldbfmaxnmal h0, h0, \[sp\]
+.*: 3ce0601f ldbfmaxnmal h0, h31, \[x0\]
+.*: 3ce063ff ldbfmaxnmal h0, h31, \[sp\]
+.*: 3cff6000 ldbfmaxnmal h31, h0, \[x0\]
+.*: 3cff63e0 ldbfmaxnmal h31, h0, \[sp\]
+.*: 3cff601f ldbfmaxnmal h31, h31, \[x0\]
+.*: 3cff63ff ldbfmaxnmal h31, h31, \[sp\]
+.*: 3c606000 ldbfmaxnml h0, h0, \[x0\]
+.*: 3c6063e0 ldbfmaxnml h0, h0, \[sp\]
+.*: 3c60601f ldbfmaxnml h0, h31, \[x0\]
+.*: 3c6063ff ldbfmaxnml h0, h31, \[sp\]
+.*: 3c7f6000 ldbfmaxnml h31, h0, \[x0\]
+.*: 3c7f63e0 ldbfmaxnml h31, h0, \[sp\]
+.*: 3c7f601f ldbfmaxnml h31, h31, \[x0\]
+.*: 3c7f63ff ldbfmaxnml h31, h31, \[sp\]
+.*: 3c205000 ldbfmin h0, h0, \[x0\]
+.*: 3c2053e0 ldbfmin h0, h0, \[sp\]
+.*: 3c20501f ldbfmin h0, h31, \[x0\]
+.*: 3c2053ff ldbfmin h0, h31, \[sp\]
+.*: 3c3f5000 ldbfmin h31, h0, \[x0\]
+.*: 3c3f53e0 ldbfmin h31, h0, \[sp\]
+.*: 3c3f501f ldbfmin h31, h31, \[x0\]
+.*: 3c3f53ff ldbfmin h31, h31, \[sp\]
+.*: 3ca05000 ldbfmina h0, h0, \[x0\]
+.*: 3ca053e0 ldbfmina h0, h0, \[sp\]
+.*: 3ca0501f ldbfmina h0, h31, \[x0\]
+.*: 3ca053ff ldbfmina h0, h31, \[sp\]
+.*: 3cbf5000 ldbfmina h31, h0, \[x0\]
+.*: 3cbf53e0 ldbfmina h31, h0, \[sp\]
+.*: 3cbf501f ldbfmina h31, h31, \[x0\]
+.*: 3cbf53ff ldbfmina h31, h31, \[sp\]
+.*: 3ce05000 ldbfminal h0, h0, \[x0\]
+.*: 3ce053e0 ldbfminal h0, h0, \[sp\]
+.*: 3ce0501f ldbfminal h0, h31, \[x0\]
+.*: 3ce053ff ldbfminal h0, h31, \[sp\]
+.*: 3cff5000 ldbfminal h31, h0, \[x0\]
+.*: 3cff53e0 ldbfminal h31, h0, \[sp\]
+.*: 3cff501f ldbfminal h31, h31, \[x0\]
+.*: 3cff53ff ldbfminal h31, h31, \[sp\]
+.*: 3c605000 ldbfminl h0, h0, \[x0\]
+.*: 3c6053e0 ldbfminl h0, h0, \[sp\]
+.*: 3c60501f ldbfminl h0, h31, \[x0\]
+.*: 3c6053ff ldbfminl h0, h31, \[sp\]
+.*: 3c7f5000 ldbfminl h31, h0, \[x0\]
+.*: 3c7f53e0 ldbfminl h31, h0, \[sp\]
+.*: 3c7f501f ldbfminl h31, h31, \[x0\]
+.*: 3c7f53ff ldbfminl h31, h31, \[sp\]
+.*: 3c207000 ldbfminnm h0, h0, \[x0\]
+.*: 3c2073e0 ldbfminnm h0, h0, \[sp\]
+.*: 3c20701f ldbfminnm h0, h31, \[x0\]
+.*: 3c2073ff ldbfminnm h0, h31, \[sp\]
+.*: 3c3f7000 ldbfminnm h31, h0, \[x0\]
+.*: 3c3f73e0 ldbfminnm h31, h0, \[sp\]
+.*: 3c3f701f ldbfminnm h31, h31, \[x0\]
+.*: 3c3f73ff ldbfminnm h31, h31, \[sp\]
+.*: 3ca07000 ldbfminnma h0, h0, \[x0\]
+.*: 3ca073e0 ldbfminnma h0, h0, \[sp\]
+.*: 3ca0701f ldbfminnma h0, h31, \[x0\]
+.*: 3ca073ff ldbfminnma h0, h31, \[sp\]
+.*: 3cbf7000 ldbfminnma h31, h0, \[x0\]
+.*: 3cbf73e0 ldbfminnma h31, h0, \[sp\]
+.*: 3cbf701f ldbfminnma h31, h31, \[x0\]
+.*: 3cbf73ff ldbfminnma h31, h31, \[sp\]
+.*: 3ce07000 ldbfminnmal h0, h0, \[x0\]
+.*: 3ce073e0 ldbfminnmal h0, h0, \[sp\]
+.*: 3ce0701f ldbfminnmal h0, h31, \[x0\]
+.*: 3ce073ff ldbfminnmal h0, h31, \[sp\]
+.*: 3cff7000 ldbfminnmal h31, h0, \[x0\]
+.*: 3cff73e0 ldbfminnmal h31, h0, \[sp\]
+.*: 3cff701f ldbfminnmal h31, h31, \[x0\]
+.*: 3cff73ff ldbfminnmal h31, h31, \[sp\]
+.*: 3c607000 ldbfminnml h0, h0, \[x0\]
+.*: 3c6073e0 ldbfminnml h0, h0, \[sp\]
+.*: 3c60701f ldbfminnml h0, h31, \[x0\]
+.*: 3c6073ff ldbfminnml h0, h31, \[sp\]
+.*: 3c7f7000 ldbfminnml h31, h0, \[x0\]
+.*: 3c7f73e0 ldbfminnml h31, h0, \[sp\]
+.*: 3c7f701f ldbfminnml h31, h31, \[x0\]
+.*: 3c7f73ff ldbfminnml h31, h31, \[sp\]
+
+.* <stf>:
+.*: 7c20801f stfadd h0, \[x0\]
+.*: 7c2083ff stfadd h0, \[sp\]
+.*: 7c3f801f stfadd h31, \[x0\]
+.*: 7c3f83ff stfadd h31, \[sp\]
+.*: bc20801f stfadd s0, \[x0\]
+.*: bc2083ff stfadd s0, \[sp\]
+.*: bc3f801f stfadd s31, \[x0\]
+.*: bc3f83ff stfadd s31, \[sp\]
+.*: fc20801f stfadd d0, \[x0\]
+.*: fc2083ff stfadd d0, \[sp\]
+.*: fc3f801f stfadd d31, \[x0\]
+.*: fc3f83ff stfadd d31, \[sp\]
+.*: 7c60801f stfaddl h0, \[x0\]
+.*: 7c6083ff stfaddl h0, \[sp\]
+.*: 7c7f801f stfaddl h31, \[x0\]
+.*: 7c7f83ff stfaddl h31, \[sp\]
+.*: bc60801f stfaddl s0, \[x0\]
+.*: bc6083ff stfaddl s0, \[sp\]
+.*: bc7f801f stfaddl s31, \[x0\]
+.*: bc7f83ff stfaddl s31, \[sp\]
+.*: fc60801f stfaddl d0, \[x0\]
+.*: fc6083ff stfaddl d0, \[sp\]
+.*: fc7f801f stfaddl d31, \[x0\]
+.*: fc7f83ff stfaddl d31, \[sp\]
+.*: 7c20c01f stfmax h0, \[x0\]
+.*: 7c20c3ff stfmax h0, \[sp\]
+.*: 7c3fc01f stfmax h31, \[x0\]
+.*: 7c3fc3ff stfmax h31, \[sp\]
+.*: bc20c01f stfmax s0, \[x0\]
+.*: bc20c3ff stfmax s0, \[sp\]
+.*: bc3fc01f stfmax s31, \[x0\]
+.*: bc3fc3ff stfmax s31, \[sp\]
+.*: fc20c01f stfmax d0, \[x0\]
+.*: fc20c3ff stfmax d0, \[sp\]
+.*: fc3fc01f stfmax d31, \[x0\]
+.*: fc3fc3ff stfmax d31, \[sp\]
+.*: 7c60c01f stfmaxl h0, \[x0\]
+.*: 7c60c3ff stfmaxl h0, \[sp\]
+.*: 7c7fc01f stfmaxl h31, \[x0\]
+.*: 7c7fc3ff stfmaxl h31, \[sp\]
+.*: bc60c01f stfmaxl s0, \[x0\]
+.*: bc60c3ff stfmaxl s0, \[sp\]
+.*: bc7fc01f stfmaxl s31, \[x0\]
+.*: bc7fc3ff stfmaxl s31, \[sp\]
+.*: fc60c01f stfmaxl d0, \[x0\]
+.*: fc60c3ff stfmaxl d0, \[sp\]
+.*: fc7fc01f stfmaxl d31, \[x0\]
+.*: fc7fc3ff stfmaxl d31, \[sp\]
+.*: 7c20e01f stfmaxnm h0, \[x0\]
+.*: 7c20e3ff stfmaxnm h0, \[sp\]
+.*: 7c3fe01f stfmaxnm h31, \[x0\]
+.*: 7c3fe3ff stfmaxnm h31, \[sp\]
+.*: bc20e01f stfmaxnm s0, \[x0\]
+.*: bc20e3ff stfmaxnm s0, \[sp\]
+.*: bc3fe01f stfmaxnm s31, \[x0\]
+.*: bc3fe3ff stfmaxnm s31, \[sp\]
+.*: fc20e01f stfmaxnm d0, \[x0\]
+.*: fc20e3ff stfmaxnm d0, \[sp\]
+.*: fc3fe01f stfmaxnm d31, \[x0\]
+.*: fc3fe3ff stfmaxnm d31, \[sp\]
+.*: 7c60e01f stfmaxnml h0, \[x0\]
+.*: 7c60e3ff stfmaxnml h0, \[sp\]
+.*: 7c7fe01f stfmaxnml h31, \[x0\]
+.*: 7c7fe3ff stfmaxnml h31, \[sp\]
+.*: bc60e01f stfmaxnml s0, \[x0\]
+.*: bc60e3ff stfmaxnml s0, \[sp\]
+.*: bc7fe01f stfmaxnml s31, \[x0\]
+.*: bc7fe3ff stfmaxnml s31, \[sp\]
+.*: fc60e01f stfmaxnml d0, \[x0\]
+.*: fc60e3ff stfmaxnml d0, \[sp\]
+.*: fc7fe01f stfmaxnml d31, \[x0\]
+.*: fc7fe3ff stfmaxnml d31, \[sp\]
+.*: 7c20d01f stfmin h0, \[x0\]
+.*: 7c20d3ff stfmin h0, \[sp\]
+.*: 7c3fd01f stfmin h31, \[x0\]
+.*: 7c3fd3ff stfmin h31, \[sp\]
+.*: bc20d01f stfmin s0, \[x0\]
+.*: bc20d3ff stfmin s0, \[sp\]
+.*: bc3fd01f stfmin s31, \[x0\]
+.*: bc3fd3ff stfmin s31, \[sp\]
+.*: fc20d01f stfmin d0, \[x0\]
+.*: fc20d3ff stfmin d0, \[sp\]
+.*: fc3fd01f stfmin d31, \[x0\]
+.*: fc3fd3ff stfmin d31, \[sp\]
+.*: 7c60d01f stfminl h0, \[x0\]
+.*: 7c60d3ff stfminl h0, \[sp\]
+.*: 7c7fd01f stfminl h31, \[x0\]
+.*: 7c7fd3ff stfminl h31, \[sp\]
+.*: bc60d01f stfminl s0, \[x0\]
+.*: bc60d3ff stfminl s0, \[sp\]
+.*: bc7fd01f stfminl s31, \[x0\]
+.*: bc7fd3ff stfminl s31, \[sp\]
+.*: fc60d01f stfminl d0, \[x0\]
+.*: fc60d3ff stfminl d0, \[sp\]
+.*: fc7fd01f stfminl d31, \[x0\]
+.*: fc7fd3ff stfminl d31, \[sp\]
+.*: 7c20f01f stfminnm h0, \[x0\]
+.*: 7c20f3ff stfminnm h0, \[sp\]
+.*: 7c3ff01f stfminnm h31, \[x0\]
+.*: 7c3ff3ff stfminnm h31, \[sp\]
+.*: bc20f01f stfminnm s0, \[x0\]
+.*: bc20f3ff stfminnm s0, \[sp\]
+.*: bc3ff01f stfminnm s31, \[x0\]
+.*: bc3ff3ff stfminnm s31, \[sp\]
+.*: fc20f01f stfminnm d0, \[x0\]
+.*: fc20f3ff stfminnm d0, \[sp\]
+.*: fc3ff01f stfminnm d31, \[x0\]
+.*: fc3ff3ff stfminnm d31, \[sp\]
+.*: 7c60f01f stfminnml h0, \[x0\]
+.*: 7c60f3ff stfminnml h0, \[sp\]
+.*: 7c7ff01f stfminnml h31, \[x0\]
+.*: 7c7ff3ff stfminnml h31, \[sp\]
+.*: bc60f01f stfminnml s0, \[x0\]
+.*: bc60f3ff stfminnml s0, \[sp\]
+.*: bc7ff01f stfminnml s31, \[x0\]
+.*: bc7ff3ff stfminnml s31, \[sp\]
+.*: fc60f01f stfminnml d0, \[x0\]
+.*: fc60f3ff stfminnml d0, \[sp\]
+.*: fc7ff01f stfminnml d31, \[x0\]
+.*: fc7ff3ff stfminnml d31, \[sp\]
+
+.* <stbf>:
+.*: 3c20801f stbfadd h0, \[x0\]
+.*: 3c2083ff stbfadd h0, \[sp\]
+.*: 3c3f801f stbfadd h31, \[x0\]
+.*: 3c3f83ff stbfadd h31, \[sp\]
+.*: 3c60801f stbfaddl h0, \[x0\]
+.*: 3c6083ff stbfaddl h0, \[sp\]
+.*: 3c7f801f stbfaddl h31, \[x0\]
+.*: 3c7f83ff stbfaddl h31, \[sp\]
+.*: 3c20c01f stbfmax h0, \[x0\]
+.*: 3c20c3ff stbfmax h0, \[sp\]
+.*: 3c3fc01f stbfmax h31, \[x0\]
+.*: 3c3fc3ff stbfmax h31, \[sp\]
+.*: 3c60c01f stbfmaxl h0, \[x0\]
+.*: 3c60c3ff stbfmaxl h0, \[sp\]
+.*: 3c7fc01f stbfmaxl h31, \[x0\]
+.*: 3c7fc3ff stbfmaxl h31, \[sp\]
+.*: 3c20e01f stbfmaxnm h0, \[x0\]
+.*: 3c20e3ff stbfmaxnm h0, \[sp\]
+.*: 3c3fe01f stbfmaxnm h31, \[x0\]
+.*: 3c3fe3ff stbfmaxnm h31, \[sp\]
+.*: 3c60e01f stbfmaxnml h0, \[x0\]
+.*: 3c60e3ff stbfmaxnml h0, \[sp\]
+.*: 3c7fe01f stbfmaxnml h31, \[x0\]
+.*: 3c7fe3ff stbfmaxnml h31, \[sp\]
+.*: 3c20d01f stbfmin h0, \[x0\]
+.*: 3c20d3ff stbfmin h0, \[sp\]
+.*: 3c3fd01f stbfmin h31, \[x0\]
+.*: 3c3fd3ff stbfmin h31, \[sp\]
+.*: 3c60d01f stbfminl h0, \[x0\]
+.*: 3c60d3ff stbfminl h0, \[sp\]
+.*: 3c7fd01f stbfminl h31, \[x0\]
+.*: 3c7fd3ff stbfminl h31, \[sp\]
+.*: 3c20f01f stbfminnm h0, \[x0\]
+.*: 3c20f3ff stbfminnm h0, \[sp\]
+.*: 3c3ff01f stbfminnm h31, \[x0\]
+.*: 3c3ff3ff stbfminnm h31, \[sp\]
+.*: 3c60f01f stbfminnml h0, \[x0\]
+.*: 3c60f3ff stbfminnml h0, \[sp\]
+.*: 3c7ff01f stbfminnml h31, \[x0\]
+.*: 3c7ff3ff stbfminnml h31, \[sp\]
diff --git a/gas/testsuite/gas/aarch64/lsfe.s b/gas/testsuite/gas/aarch64/lsfe.s
new file mode 100644
index 00000000000..ff11f92d643
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/lsfe.s
@@ -0,0 +1,71 @@
+ldf:
+ .irp op, add, max, maxnm, min, minnm
+ .irp suffix, , a, al, l
+ ldf\op\suffix h0, h0, [x0]
+ ldf\op\suffix h0, h0, [sp]
+ ldf\op\suffix h0, h31, [x0]
+ ldf\op\suffix h0, h31, [sp]
+ ldf\op\suffix h31, h0, [x0]
+ ldf\op\suffix h31, h0, [sp]
+ ldf\op\suffix h31, h31, [x0]
+ ldf\op\suffix h31, h31, [sp]
+ ldf\op\suffix s0, s0, [x0]
+ ldf\op\suffix s0, s0, [sp]
+ ldf\op\suffix s0, s31, [x0]
+ ldf\op\suffix s0, s31, [sp]
+ ldf\op\suffix s31, s0, [x0]
+ ldf\op\suffix s31, s0, [sp]
+ ldf\op\suffix s31, s31, [x0]
+ ldf\op\suffix s31, s31, [sp]
+ ldf\op\suffix d0, d0, [x0]
+ ldf\op\suffix d0, d0, [sp]
+ ldf\op\suffix d0, d31, [x0]
+ ldf\op\suffix d0, d31, [sp]
+ ldf\op\suffix d31, d0, [x0]
+ ldf\op\suffix d31, d0, [sp]
+ ldf\op\suffix d31, d31, [x0]
+ ldf\op\suffix d31, d31, [sp]
+ .endr
+ .endr
+
+ldbf:
+ .irp op, add, max, maxnm, min, minnm
+ .irp suffix, , a, al, l
+ ldbf\op\suffix h0, h0, [x0]
+ ldbf\op\suffix h0, h0, [sp]
+ ldbf\op\suffix h0, h31, [x0]
+ ldbf\op\suffix h0, h31, [sp]
+ ldbf\op\suffix h31, h0, [x0]
+ ldbf\op\suffix h31, h0, [sp]
+ ldbf\op\suffix h31, h31, [x0]
+ ldbf\op\suffix h31, h31, [sp]
+ .endr
+ .endr
+
+stf:
+ .irp op, add, max, maxnm, min, minnm
+ .irp suffix, , l
+ stf\op\suffix h0, [x0]
+ stf\op\suffix h0, [sp]
+ stf\op\suffix h31, [x0]
+ stf\op\suffix h31, [sp]
+ stf\op\suffix s0, [x0]
+ stf\op\suffix s0, [sp]
+ stf\op\suffix s31, [x0]
+ stf\op\suffix s31, [sp]
+ stf\op\suffix d0, [x0]
+ stf\op\suffix d0, [sp]
+ stf\op\suffix d31, [x0]
+ stf\op\suffix d31, [sp]
+ .endr
+ .endr
+
+stbf:
+ .irp op, add, max, maxnm, min, minnm
+ .irp suffix, , l
+ stbf\op\suffix h0, [x0]
+ stbf\op\suffix h0, [sp]
+ stbf\op\suffix h31, [x0]
+ stbf\op\suffix h31, [sp]
+ .endr
+ .endr
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index dfe3f05820a..cef72f0f60b 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -79,6 +79,8 @@ enum aarch64_feature_bit {
AARCH64_FEATURE_CRC,
/* LSE instructions. */
AARCH64_FEATURE_LSE,
+ /* LSFE instructions. */
+ AARCH64_FEATURE_LSFE,
/* PAN instructions. */
AARCH64_FEATURE_PAN,
/* LOR instructions. */
@@ -1067,6 +1069,7 @@ enum aarch64_insn_class
log_imm,
log_shift,
lse_atomic,
+ lsfe_atomic,
lse128_atomic,
movewide,
pcreladdr,
@@ -1419,6 +1422,7 @@ extern const aarch64_opcode aarch64_opcode_table[];
#define F_BRANCH_RET (2ULL << 37)
/* Subclass to denote that only tag update is involved. */
#define F_DP_TAG_ONLY (1ULL << 37)
+#define F_LSFE_SZ (1ULL << 42)
#define F_SUBCLASS_OTHER (F_SUBCLASS)
/* Next bit is 41. */
@@ -1505,7 +1509,7 @@ opcode_has_special_coder (const aarch64_opcode *opcode)
{
return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
| F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND
- | F_OPD_SIZE | F_RCPC3_SIZE)) != 0;
+ | F_OPD_SIZE | F_RCPC3_SIZE | F_LSFE_SZ )) != 0;
}
struct aarch64_name_value_pair
diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c
index f20bdf6ae67..e7122da2762 100644
--- a/opcodes/aarch64-asm.c
+++ b/opcodes/aarch64-asm.c
@@ -2063,6 +2063,13 @@ do_special_encoding (struct aarch64_inst *inst)
insert_field (FLD_rcpc3_size, &inst->value, value, 0);
}
+ if (inst->opcode->flags & F_LSFE_SZ)
+ {
+ value = aarch64_get_qualifier_standard_value (inst->operands[0].qualifier);
+ insert_field (FLD_ldst_size, &inst->value, value, 0);
+ return;
+ }
+
if (inst->opcode->flags & F_SIZEQ)
encode_sizeq (inst);
if (inst->opcode->flags & F_FPTYPE)
diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index 6552d0e202d..dc31dcdd272 100644
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -2831,6 +2831,23 @@ do_special_decoding (aarch64_inst *inst)
}
}
+ if (inst->opcode->flags & F_LSFE_SZ)
+ {
+ value = extract_field (FLD_ldst_size, inst->value, 0);
+
+ if (value > 0x3)
+ return 0;
+
+ for (int i = 0;
+ aarch64_operands[inst->operands[i].type].op_class != AARCH64_OPND_CLASS_ADDRESS;
+ i++)
+ {
+ inst->operands[i].qualifier = get_sreg_qualifier_from_value (value);
+ if (inst->operands[i].qualifier == AARCH64_OPND_QLF_ERR)
+ return 0;
+ }
+ }
+
if (inst->opcode->flags & F_T)
{
/* Num of consecutive '0's on the right side of imm5<3:0>. */
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 8b64eb07067..4a90d1379c1 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -1211,6 +1211,20 @@
QLF3(X, X, NIL), \
}
+/* e.g. LDBFADD <Fs>, <Ft>, [<Xn|SP>{,#0}]. */
+#define QL_FP2_H_0 \
+{ \
+ QLF3(S_H, S_H, NIL), \
+}
+
+/* e.g. LDFADD <Fs>, <Ft>, [<Xn|SP>{,#0}]. */
+#define QL_FP2_HSD_0 \
+{ \
+ QLF3(S_H, S_H, NIL), \
+ QLF3(S_S, S_S, NIL), \
+ QLF3(S_D, S_D, NIL), \
+}
+
/* e.g. CASP <Xt1>, <Xt1+1>, <Xt2>, <Xt2+1>, [<Xn|SP>{,#0}]. */
#define QL_R4NIL \
{ \
@@ -1353,6 +1367,14 @@
QLF2(S_D, NIL), \
}
+/* e.g. STFADD <Fs>, [<Xn|SP>]. */
+#define QL_FP_HSD_0 \
+{ \
+ QLF2(S_H, NIL), \
+ QLF2(S_S, NIL), \
+ QLF2(S_D, NIL), \
+}
+
/* e.g. ADDV <V><d>, <Vn>.<T>. */
#define QL_XLANES \
{ \
@@ -2693,6 +2715,8 @@ static const aarch64_feature_set aarch64_feature_crc =
AARCH64_FEATURE (CRC);
static const aarch64_feature_set aarch64_feature_lse =
AARCH64_FEATURE (LSE);
+static const aarch64_feature_set aarch64_feature_lsfe =
+ AARCH64_FEATURE (LSFE);
static const aarch64_feature_set aarch64_feature_lse128 =
AARCH64_FEATURES (2, LSE, LSE128);
static const aarch64_feature_set aarch64_feature_lor =
@@ -2875,6 +2899,7 @@ static const aarch64_feature_set aarch64_feature_sve2p1_sme2p1 =
#define SIMD &aarch64_feature_simd
#define CRC &aarch64_feature_crc
#define LSE &aarch64_feature_lse
+#define LSFE &aarch64_feature_lsfe
#define LSE128 &aarch64_feature_lse128
#define LOR &aarch64_feature_lor
#define RDMA &aarch64_feature_rdma
@@ -2976,6 +3001,8 @@ static const aarch64_feature_set aarch64_feature_sve2p1_sme2p1 =
{ NAME, OPCODE, MASK, CLASS, 0, CRC, OPS, QUALS, FLAGS, 0, 0, NULL }
#define _LSE_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, 0, LSE, OPS, QUALS, FLAGS, 0, 0, NULL }
+#define _LSFE_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS, FLAGS) \
+ { NAME, OPCODE, MASK, CLASS, 0, LSFE, OPS, QUALS, FLAGS, 0, 0, NULL }
#define _LSE128_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, 0, LSE128, OPS, QUALS, FLAGS, 0, 0, NULL }
#define _LOR_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
@@ -6450,6 +6477,87 @@ const struct aarch64_opcode aarch64_opcode_table[] =
RCPC2_INSN ("stlur", 0xd9000000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLX, 0),
RCPC2_INSN ("ldapur", 0xd9400000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLX, 0),
+ /* Floating-point atomic add in memory. */
+ _LSFE_INSN ("ldfadd", 0x3c200000, 0x3fe0fc00, lsfe_atomic, OP3 (Fm, Fd, ADDR_SIMPLE), QL_FP2_HSD_0, F_LSFE_SZ),
+ _LSFE_INSN ("ldfadda", 0x3ca00000, 0x3fe0fc00, lsfe_atomic, OP3 (Fm, Fd, ADDR_SIMPLE), QL_FP2_HSD_0, F_LSFE_SZ),
+ _LSFE_INSN ("ldfaddal", 0x3ce00000, 0x3fe0fc00, lsfe_atomic, OP3 (Fm, Fd, ADDR_SIMPLE), QL_FP2_HSD_0, F_LSFE_SZ),
+ _LSFE_INSN ("ldfaddl", 0x3c600000, 0x3fe0fc00, lsfe_atomic, OP3 (Fm, Fd, ADDR_SIMPLE), QL_FP2_HSD_0, F_LSFE_SZ),
+ /* Floating-point atomic maximum in memory. */
+ _LSFE_INSN ("ldfmax", 0x3c204000, 0x3fe0fc00, lsfe_atomic, OP3 (Fm, Fd, ADDR_SIMPLE), QL_FP2_HSD_0, F_LSFE_SZ),
+ _LSFE_INSN ("ldfmaxa", 0x3ca04000, 0x3fe0fc00, lsfe_atomic, OP3 (Fm, Fd, ADDR_SIMPLE), QL_FP2_HSD_0, F_LSFE_SZ),
+ _LSFE_INSN ("ldfmaxal", 0x3ce04000, 0x3fe0fc00, lsfe_atomic, OP3 (Fm, Fd, ADDR_SIMPLE), QL_FP2_HSD_0, F_LSFE_SZ),
+ _LSFE_INSN ("ldfmaxl", 0x3c604000, 0x3fe0fc00, lsfe_atomic, OP3 (Fm, Fd, ADDR_SIMPLE), QL_FP2_HSD_0, F_LSFE_SZ),
+ /* Floating-point atomic maximum number in memory. */
+ _LSFE_INSN ("ldfmaxnm", 0x3c206000, 0x3fe0fc00, lsfe_atomic, OP3 (Fm, Fd, ADDR_SIMPLE), QL_FP2_HSD_0, F_LSFE_SZ),
+ _LSFE_INSN ("ldfmaxnma", 0x3ca06000, 0x3fe0fc00, lsfe_atomic, OP3 (Fm, Fd, ADDR_SIMPLE), QL_FP2_HSD_0, F_LSFE_SZ),
+ _LSFE_INSN ("ldfmaxnmal", 0x3ce06000, 0x3fe0fc00, lsfe_atomic, OP3 (Fm, Fd, ADDR_SIMPLE), QL_FP2_HSD_0, F_LSFE_SZ),
+ _LSFE_INSN ("ldfmaxnml", 0x3c606000, 0x3fe0fc00, lsfe_atomic, OP3 (Fm, Fd, ADDR_SIMPLE), QL_FP2_HSD_0, F_LSFE_SZ),
+ /* Floating-point atomic minimum in memory. */
+ _LSFE_INSN ("ldfmin", 0x3c205000, 0x3fe0fc00, lsfe_atomic, OP3 (Fm, Fd, ADDR_SIMPLE), QL_FP2_HSD_0, F_LSFE_SZ),
+ _LSFE_INSN ("ldfmina", 0x3ca05000, 0x3fe0fc00, lsfe_atomic, OP3 (Fm, Fd, ADDR_SIMPLE), QL_FP2_HSD_0, F_LSFE_SZ),
+ _LSFE_INSN ("ldfminal", 0x3ce05000, 0x3fe0fc00, lsfe_atomic, OP3 (Fm, Fd, ADDR_SIMPLE), QL_FP2_HSD_0, F_LSFE_SZ),
+ _LSFE_INSN ("ldfminl", 0x3c605000, 0x3fe0fc00, lsfe_atomic, OP3 (Fm, Fd, ADDR_SIMPLE), QL_FP2_HSD_0, F_LSFE_SZ),
+ /* Floating-point atomic minimum number in memory. */
+ _LSFE_INSN ("ldfminnm", 0x3c207000, 0x3fe0fc00, lsfe_atomic, OP3 (Fm, Fd, ADDR_SIMPLE), QL_FP2_HSD_0, F_LSFE_SZ),
+ _LSFE_INSN ("ldfminnma", 0x3ca07000, 0x3fe0fc00, lsfe_atomic, OP3 (Fm, Fd, ADDR_SIMPLE), QL_FP2_HSD_0, F_LSFE_SZ),
+ _LSFE_INSN ("ldfminnmal", 0x3ce07000, 0x3fe0fc00, lsfe_atomic, OP3 (Fm, Fd, ADDR_SIMPLE), QL_FP2_HSD_0, F_LSFE_SZ),
+ _LSFE_INSN ("ldfminnml", 0x3c607000, 0x3fe0fc00, lsfe_atomic, OP3 (Fm, Fd, ADDR_SIMPLE), QL_FP2_HSD_0, F_LSFE_SZ),
+ /* BFloat16 floating-point add in memory. */
+ _LSFE_INSN ("ldbfadd", 0x3c200000, 0xffe0fc00, lsfe_atomic, OP3 (Fm, Fd, ADDR_SIMPLE), QL_FP2_H_0, 0),
+ _LSFE_INSN ("ldbfadda", 0x3ca00000, 0xffe0fc00, lsfe_atomic, OP3 (Fm, Fd, ADDR_SIMPLE), QL_FP2_H_0, 0),
+ _LSFE_INSN ("ldbfaddal", 0x3ce00000, 0xffe0fc00, lsfe_atomic, OP3 (Fm, Fd, ADDR_SIMPLE), QL_FP2_H_0, 0),
+ _LSFE_INSN ("ldbfaddl", 0x3c600000, 0xffe0fc00, lsfe_atomic, OP3 (Fm, Fd, ADDR_SIMPLE), QL_FP2_H_0, 0),
+ /* BFloat16 floating-point maximum in memory. */
+ _LSFE_INSN ("ldbfmax", 0x3c204000, 0xffe0fc00, lsfe_atomic, OP3 (Fm, Fd, ADDR_SIMPLE), QL_FP2_H_0, 0),
+ _LSFE_INSN ("ldbfmaxa", 0x3ca04000, 0xffe0fc00, lsfe_atomic, OP3 (Fm, Fd, ADDR_SIMPLE), QL_FP2_H_0, 0),
+ _LSFE_INSN ("ldbfmaxal", 0x3ce04000, 0xffe0fc00, lsfe_atomic, OP3 (Fm, Fd, ADDR_SIMPLE), QL_FP2_H_0, 0),
+ _LSFE_INSN ("ldbfmaxl", 0x3c604000, 0xffe0fc00, lsfe_atomic, OP3 (Fm, Fd, ADDR_SIMPLE), QL_FP2_H_0, 0),
+ /* BFloat16 floating-point maximum number in memory. */
+ _LSFE_INSN ("ldbfmaxnm", 0x3c206000, 0xffe0fc00, lsfe_atomic, OP3 (Fm, Fd, ADDR_SIMPLE), QL_FP2_H_0, 0),
+ _LSFE_INSN ("ldbfmaxnma", 0x3ca06000, 0xffe0fc00, lsfe_atomic, OP3 (Fm, Fd, ADDR_SIMPLE), QL_FP2_H_0, 0),
+ _LSFE_INSN ("ldbfmaxnmal", 0x3ce06000, 0xffe0fc00, lsfe_atomic, OP3 (Fm, Fd, ADDR_SIMPLE), QL_FP2_H_0, 0),
+ _LSFE_INSN ("ldbfmaxnml", 0x3c606000, 0xffe0fc00, lsfe_atomic, OP3 (Fm, Fd, ADDR_SIMPLE), QL_FP2_H_0, 0),
+ /* BFloat16 floating-point minimum in memory. */
+ _LSFE_INSN ("ldbfmin", 0x3c205000, 0xffe0fc00, lsfe_atomic, OP3 (Fm, Fd, ADDR_SIMPLE), QL_FP2_H_0, 0),
+ _LSFE_INSN ("ldbfmina", 0x3ca05000, 0xffe0fc00, lsfe_atomic, OP3 (Fm, Fd, ADDR_SIMPLE), QL_FP2_H_0, 0),
+ _LSFE_INSN ("ldbfminal", 0x3ce05000, 0xffe0fc00, lsfe_atomic, OP3 (Fm, Fd, ADDR_SIMPLE), QL_FP2_H_0, 0),
+ _LSFE_INSN ("ldbfminl", 0x3c605000, 0xffe0fc00, lsfe_atomic, OP3 (Fm, Fd, ADDR_SIMPLE), QL_FP2_H_0, 0),
+ /* BFloat16 floating-point minimum number in memory. */
+ _LSFE_INSN ("ldbfminnm", 0x3c207000, 0xffe0fc00, lsfe_atomic, OP3 (Fm, Fd, ADDR_SIMPLE), QL_FP2_H_0, 0),
+ _LSFE_INSN ("ldbfminnma", 0x3ca07000, 0xffe0fc00, lsfe_atomic, OP3 (Fm, Fd, ADDR_SIMPLE), QL_FP2_H_0, 0),
+ _LSFE_INSN ("ldbfminnmal", 0x3ce07000, 0xffe0fc00, lsfe_atomic, OP3 (Fm, Fd, ADDR_SIMPLE), QL_FP2_H_0, 0),
+ _LSFE_INSN ("ldbfminnml", 0x3c607000, 0xffe0fc00, lsfe_atomic, OP3 (Fm, Fd, ADDR_SIMPLE), QL_FP2_H_0, 0),
+ /* Floating-point atomic add in memory, without return. */
+ _LSFE_INSN ("stfadd", 0x3c20801f, 0x3fe0fc1f, lsfe_atomic, OP2 (Fm, ADDR_SIMPLE), QL_FP_HSD_0, F_LSFE_SZ),
+ _LSFE_INSN ("stfaddl", 0x3c60801f, 0x3fe0fc1f, lsfe_atomic, OP2 (Fm, ADDR_SIMPLE), QL_FP_HSD_0, F_LSFE_SZ),
+ /* Floating-point atomic maximum in memory, without return. */
+ _LSFE_INSN ("stfmax", 0x3c20c01f, 0x3fe0fc1f, lsfe_atomic, OP2 (Fm, ADDR_SIMPLE), QL_FP_HSD_0, F_LSFE_SZ),
+ _LSFE_INSN ("stfmaxl", 0x3c60c01f, 0x3fe0fc1f, lsfe_atomic, OP2 (Fm, ADDR_SIMPLE), QL_FP_HSD_0, F_LSFE_SZ),
+ /* Floating-point atomic maximum number in memory, without return. */
+ _LSFE_INSN ("stfmaxnm", 0x3c20e01f, 0x3fe0fc1f, lsfe_atomic, OP2 (Fm, ADDR_SIMPLE), QL_FP_HSD_0, F_LSFE_SZ),
+ _LSFE_INSN ("stfmaxnml", 0x3c60e01f, 0x3fe0fc1f, lsfe_atomic, OP2 (Fm, ADDR_SIMPLE), QL_FP_HSD_0, F_LSFE_SZ),
+ /* Floating-point atomic minimum in memory, without return. */
+ _LSFE_INSN ("stfmin", 0x3c20d01f, 0x3fe0fc1f, lsfe_atomic, OP2 (Fm, ADDR_SIMPLE), QL_FP_HSD_0, F_LSFE_SZ),
+ _LSFE_INSN ("stfminl", 0x3c60d01f, 0x3fe0fc1f, lsfe_atomic, OP2 (Fm, ADDR_SIMPLE), QL_FP_HSD_0, F_LSFE_SZ),
+ /* Floating-point atomic minimum number in memory, without return. */
+ _LSFE_INSN ("stfminnm", 0x3c20f01f, 0x3fe0fc1f, lsfe_atomic, OP2 (Fm, ADDR_SIMPLE), QL_FP_HSD_0, F_LSFE_SZ),
+ _LSFE_INSN ("stfminnml", 0x3c60f01f, 0x3fe0fc1f, lsfe_atomic, OP2 (Fm, ADDR_SIMPLE), QL_FP_HSD_0, F_LSFE_SZ),
+ /* BFloat16 floating-point atomic add in memory, without return. */
+ _LSFE_INSN ("stbfadd", 0x3c20801f, 0xffe0fc1f, lsfe_atomic, OP2 (Fm, ADDR_SIMPLE), QL_DST_H, 0),
+ _LSFE_INSN ("stbfaddl", 0x3c60801f, 0xffe0fc1f, lsfe_atomic, OP2 (Fm, ADDR_SIMPLE), QL_DST_H, 0),
+ /* BFloat16 floating-point atomic maximum in memory, without return. */
+ _LSFE_INSN ("stbfmax", 0x3c20c01f, 0xffe0fc1f, lsfe_atomic, OP2 (Fm, ADDR_SIMPLE), QL_DST_H, 0),
+ _LSFE_INSN ("stbfmaxl", 0x3c60c01f, 0xffe0fc1f, lsfe_atomic, OP2 (Fm, ADDR_SIMPLE), QL_DST_H, 0),
+ /* BFloat16 floating-point atomic maximum number in memory, without return. */
+ _LSFE_INSN ("stbfmaxnm", 0x3c20e01f, 0xffe0fc1f, lsfe_atomic, OP2 (Fm, ADDR_SIMPLE), QL_DST_H, 0),
+ _LSFE_INSN ("stbfmaxnml", 0x3c60e01f, 0xffe0fc1f, lsfe_atomic, OP2 (Fm, ADDR_SIMPLE), QL_DST_H, 0),
+ /* BFloat16 floating-point atomic minumum in memory, without return. */
+ _LSFE_INSN ("stbfmin", 0x3c20d01f, 0xffe0fc1f, lsfe_atomic, OP2 (Fm, ADDR_SIMPLE), QL_DST_H, 0),
+ _LSFE_INSN ("stbfminl", 0x3c60d01f, 0xffe0fc1f, lsfe_atomic, OP2 (Fm, ADDR_SIMPLE), QL_DST_H, 0),
+ /* BFloat16 floating-point atomic minumum number in memory, without return. */
+ _LSFE_INSN ("stbfminnm", 0x3c20f01f, 0xffe0fc1f, lsfe_atomic, OP2 (Fm, ADDR_SIMPLE), QL_DST_H, 0),
+ _LSFE_INSN ("stbfminnml", 0x3c60f01f, 0xffe0fc1f, lsfe_atomic, OP2 (Fm, ADDR_SIMPLE), QL_DST_H, 0),
+
/* Matrix Multiply instructions. */
INT8MATMUL_SVE_INSNC ("smmla", 0x45009800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SBB, 0, C_SCAN_MOVPRFX, 0),
INT8MATMUL_SVE_INSNC ("ummla", 0x45c09800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SBB, 0, C_SCAN_MOVPRFX, 0),
--
2.45.2
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