[PATCH v2] aarch64: Support id_aa64fpfr0_el1, id_aa64pfr2_el1

[Richard Earnshaw (lists)]

On 29/05/2025 20:13, Dmitry Chestnykh wrote:
> ---
> v2: remove explicit specification of x0 reg in test cases
> ---
>  gas/testsuite/gas/aarch64/sysreg/sysreg.d | 2 ++
>  gas/testsuite/gas/aarch64/sysreg/sysreg.s | 2 ++
>  opcodes/aarch64-sys-regs.def              | 2 ++
>  3 files changed, 6 insertions(+)
> 
> diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg.d b/gas/testsuite/gas/aarch64/sysreg/sysreg.d
> index 4fa9f0d559d..9aba54829e1 100644
> --- a/gas/testsuite/gas/aarch64/sysreg/sysreg.d
> +++ b/gas/testsuite/gas/aarch64/sysreg/sysreg.d
> @@ -40,3 +40,5 @@ Disassembly of section \.text:
>  .*:	d5384b00 	mrs	x0, s3_0_c4_c11_0
>  .*:	d5110300 	msr	trcstatr, x0
>  .*:	d5310300 	mrs	x0, trcstatr
> +.*:	d53804e0 	mrs	x0, id_aa64fpfr0_el1
> +.*:	d5380440 	mrs	x0, id_aa64pfr2_el1
> diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg.s b/gas/testsuite/gas/aarch64/sysreg/sysreg.s
> index cf0461412b5..cd33810ec15 100644
> --- a/gas/testsuite/gas/aarch64/sysreg/sysreg.s
> +++ b/gas/testsuite/gas/aarch64/sysreg/sysreg.s
> @@ -34,3 +34,5 @@
>  	rw_sys_reg sys_reg=s3_0_c12_c15_0 w=0
>  	rw_sys_reg sys_reg=s3_0_c4_c11_0
>  	rw_sys_reg sys_reg=s2_1_c0_c3_0
> +	rw_sys_reg sys_reg=id_aa64fpfr0_el1 w=0
> +	rw_sys_reg sys_reg=id_aa64pfr2_el1 w=0
> diff --git a/opcodes/aarch64-sys-regs.def b/opcodes/aarch64-sys-regs.def
> index 9713ff08d1a..d1ae109940c 100644
> --- a/opcodes/aarch64-sys-regs.def
> +++ b/opcodes/aarch64-sys-regs.def
> @@ -521,6 +521,7 @@
>    SYSREG ("id_aa64dfr0_el1",	CPENC (3,0,0,5,0),	F_REG_READ,		AARCH64_NO_FEATURES)
>    SYSREG ("id_aa64dfr1_el1",	CPENC (3,0,0,5,1),	F_REG_READ,		AARCH64_NO_FEATURES)
>    SYSREG ("id_aa64dfr2_el1",	CPENC (3,0,0,5,2),	F_REG_READ,		AARCH64_NO_FEATURES)
> +  SYSREG ("id_aa64fpfr0_el1",	CPENC (3,0,0,4,7),	F_REG_READ,		AARCH64_NO_FEATURES)
>    SYSREG ("id_aa64isar0_el1",	CPENC (3,0,0,6,0),	F_REG_READ,		AARCH64_NO_FEATURES)
>    SYSREG ("id_aa64isar1_el1",	CPENC (3,0,0,6,1),	F_REG_READ,		AARCH64_NO_FEATURES)
>    SYSREG ("id_aa64isar2_el1",	CPENC (3,0,0,6,2),	F_REG_READ,		AARCH64_NO_FEATURES)
> @@ -532,6 +533,7 @@
>    SYSREG ("id_aa64mmfr4_el1",	CPENC (3,0,0,7,4),	F_REG_READ,		AARCH64_NO_FEATURES)
>    SYSREG ("id_aa64pfr0_el1",	CPENC (3,0,0,4,0),	F_REG_READ,		AARCH64_NO_FEATURES)
>    SYSREG ("id_aa64pfr1_el1",	CPENC (3,0,0,4,1),	F_REG_READ,		AARCH64_NO_FEATURES)
> +  SYSREG ("id_aa64pfr2_el1",	CPENC (3,0,0,4,2),	F_REG_READ,		AARCH64_NO_FEATURES)
>    SYSREG ("id_aa64smfr0_el1",	CPENC (3,0,0,4,5),	F_REG_READ|F_ARCHEXT,	AARCH64_FEATURE (SME))
>    SYSREG ("id_aa64zfr0_el1",	CPENC (3,0,0,4,4),	F_REG_READ|F_ARCHEXT,	AARCH64_FEATURE (SVE))
>    SYSREG ("id_afr0_el1",	CPENC (3,0,0,1,3),	F_REG_READ,		AARCH64_NO_FEATURES)

Thanks, I've committed this.

For a patch this size I don't think we need to worry about a DCO or copyright assignment, but if you intend to send further patches, that might become necessary.

Thanks for contributing.

Richard.