[PATCH 1/2] aarch64: Add support for FEAT_FPRCVT
richard.ball@arm.com
richard.ball@arm.com
Tue Jun 3 15:27:50 GMT 2025
From: Richard Ball <Richard.Ball@arm.com>
FEAT_FPRCVT introduces new versions of previous instructions.
The instructions are used to convert between floating points and
Integers.
These new versions take as operands SIMD&FP registers for both
the source and destination register.
---
gas/config/tc-aarch64.c | 1 +
gas/doc/c-aarch64.texi | 2 +
gas/testsuite/gas/aarch64/fprcvt-bad.d | 4 ++
gas/testsuite/gas/aarch64/fprcvt-bad.l | 49 ++++++++++++++++
gas/testsuite/gas/aarch64/fprcvt.d | 80 ++++++++++++++++++++++++++
gas/testsuite/gas/aarch64/fprcvt.s | 63 ++++++++++++++++++++
include/opcode/aarch64.h | 4 ++
opcodes/aarch64-asm.c | 3 +-
opcodes/aarch64-dis.c | 11 +++-
opcodes/aarch64-opc.h | 10 ++++
opcodes/aarch64-tbl.h | 35 +++++++++++
11 files changed, 260 insertions(+), 2 deletions(-)
create mode 100644 gas/testsuite/gas/aarch64/fprcvt-bad.d
create mode 100644 gas/testsuite/gas/aarch64/fprcvt-bad.l
create mode 100644 gas/testsuite/gas/aarch64/fprcvt.d
create mode 100644 gas/testsuite/gas/aarch64/fprcvt.s
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 398b7d618c7..0a5d16b8ef2 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -10670,6 +10670,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
{"rdm", AARCH64_FEATURE (RDMA), AARCH64_FEATURE (SIMD)},
{"fp16", AARCH64_FEATURE (F16), AARCH64_FEATURE (FP)},
{"fp16fml", AARCH64_FEATURE (F16_FML), AARCH64_FEATURE (F16)},
+ {"fprcvt", AARCH64_FEATURE (FPRCVT), AARCH64_FEATURE (FP)},
{"profile", AARCH64_FEATURE (PROFILE), AARCH64_NO_FEATURES},
{"sve", AARCH64_FEATURE (SVE), AARCH64_FEATURE (COMPNUM)},
{"tme", AARCH64_FEATURE (TME), AARCH64_NO_FEATURES},
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index 10888d1e78f..ec50c13660a 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -205,6 +205,8 @@ automatically cause those extensions to be disabled.
@tab Enable Armv8.2 16-bit floating-point multiplication variant support.
@item @code{fp16} @tab @code{fp}
@tab Enable Armv8.2 16-bit floating-point support.
+@item @code{fprcvt} @tab
+ @tab Enable Armv9.6 fprcvt instructions.
@item @code{frintts} @tab @code{fp}
@tab Enable floating-point round to integral value instructions.
@item @code{gcs} @tab
diff --git a/gas/testsuite/gas/aarch64/fprcvt-bad.d b/gas/testsuite/gas/aarch64/fprcvt-bad.d
new file mode 100644
index 00000000000..2dde4f24d15
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/fprcvt-bad.d
@@ -0,0 +1,4 @@
+#name: Illegal test of FPRCVT instructions
+#as: -march=armv8-a
+#source: fprcvt.s
+#error_output: fprcvt-bad.l
\ No newline at end of file
diff --git a/gas/testsuite/gas/aarch64/fprcvt-bad.l b/gas/testsuite/gas/aarch64/fprcvt-bad.l
new file mode 100644
index 00000000000..7192ce4175b
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/fprcvt-bad.l
@@ -0,0 +1,49 @@
+[^:]*: Assembler messages:
+.*: Error: selected processor does not support `fcvtas s7,h7'
+.*: Error: selected processor does not support `fcvtas d7,h7'
+.*: Error: selected processor does not support `fcvtas d7,s7'
+.*: Error: selected processor does not support `fcvtas s7,d7'
+.*: Error: selected processor does not support `fcvtau s7,h7'
+.*: Error: selected processor does not support `fcvtau d7,h7'
+.*: Error: selected processor does not support `fcvtau d7,s7'
+.*: Error: selected processor does not support `fcvtau s7,d7'
+.*: Error: selected processor does not support `fcvtms s7,h7'
+.*: Error: selected processor does not support `fcvtms d7,h7'
+.*: Error: selected processor does not support `fcvtms d7,s7'
+.*: Error: selected processor does not support `fcvtms s7,d7'
+.*: Error: selected processor does not support `fcvtmu s7,h7'
+.*: Error: selected processor does not support `fcvtmu d7,h7'
+.*: Error: selected processor does not support `fcvtmu d7,s7'
+.*: Error: selected processor does not support `fcvtmu s7,d7'
+.*: Error: selected processor does not support `fcvtns s7,h7'
+.*: Error: selected processor does not support `fcvtns d7,h7'
+.*: Error: selected processor does not support `fcvtns d7,s7'
+.*: Error: selected processor does not support `fcvtns s7,d7'
+.*: Error: selected processor does not support `fcvtnu s7,h7'
+.*: Error: selected processor does not support `fcvtnu d7,h7'
+.*: Error: selected processor does not support `fcvtnu d7,s7'
+.*: Error: selected processor does not support `fcvtnu s7,d7'
+.*: Error: selected processor does not support `fcvtps s7,h7'
+.*: Error: selected processor does not support `fcvtps d7,h7'
+.*: Error: selected processor does not support `fcvtps d7,s7'
+.*: Error: selected processor does not support `fcvtps s7,d7'
+.*: Error: selected processor does not support `fcvtpu s7,h7'
+.*: Error: selected processor does not support `fcvtpu d7,h7'
+.*: Error: selected processor does not support `fcvtpu d7,s7'
+.*: Error: selected processor does not support `fcvtpu s7,d7'
+.*: Error: selected processor does not support `fcvtzs s7,h7'
+.*: Error: selected processor does not support `fcvtzs d7,h7'
+.*: Error: selected processor does not support `fcvtzs d7,s7'
+.*: Error: selected processor does not support `fcvtzs s7,d7'
+.*: Error: selected processor does not support `fcvtzu s7,h7'
+.*: Error: selected processor does not support `fcvtzu d7,h7'
+.*: Error: selected processor does not support `fcvtzu d7,s7'
+.*: Error: selected processor does not support `fcvtzu s7,d7'
+.*: Error: selected processor does not support `scvtf h7,s7'
+.*: Error: selected processor does not support `scvtf d7,s7'
+.*: Error: selected processor does not support `scvtf h7,d7'
+.*: Error: selected processor does not support `scvtf s7,d7'
+.*: Error: selected processor does not support `ucvtf h7,s7'
+.*: Error: selected processor does not support `ucvtf d7,s7'
+.*: Error: selected processor does not support `ucvtf h7,d7'
+.*: Error: selected processor does not support `ucvtf s7,d7'
\ No newline at end of file
diff --git a/gas/testsuite/gas/aarch64/fprcvt.d b/gas/testsuite/gas/aarch64/fprcvt.d
new file mode 100644
index 00000000000..42b0b4c9287
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/fprcvt.d
@@ -0,0 +1,80 @@
+#name: FPRCVT instructions
+#as: -march=armv8-a+fprcvt
+#objdump: -dr
+
+.*: file format .*
+
+
+Disassembly of section .*:
+
+.* <a>:
+.* 1efa00e7 fcvtas s7, h7
+.* 9efa00e7 fcvtas d7, h7
+.* 9e3a00e7 fcvtas d7, s7
+.* 1e7a00e7 fcvtas s7, d7
+
+.* <b>:
+.* 1efb00e7 fcvtau s7, h7
+.* 9efb00e7 fcvtau d7, h7
+.* 9e3b00e7 fcvtau d7, s7
+.* 1e7b00e7 fcvtau s7, d7
+
+.* <c>:
+.* 1ef400e7 fcvtms s7, h7
+.* 9ef400e7 fcvtms d7, h7
+.* 9e3400e7 fcvtms d7, s7
+.* 1e7400e7 fcvtms s7, d7
+
+.* <d>:
+.* 1ef500e7 fcvtmu s7, h7
+.* 9ef500e7 fcvtmu d7, h7
+.* 9e3500e7 fcvtmu d7, s7
+.* 1e7500e7 fcvtmu s7, d7
+
+.* <e>:
+.* 1eea00e7 fcvtns s7, h7
+.* 9eea00e7 fcvtns d7, h7
+.* 9e2a00e7 fcvtns d7, s7
+.* 1e6a00e7 fcvtns s7, d7
+
+.* <f>:
+.* 1eeb00e7 fcvtnu s7, h7
+.* 9eeb00e7 fcvtnu d7, h7
+.* 9e2b00e7 fcvtnu d7, s7
+.* 1e6b00e7 fcvtnu s7, d7
+
+.* <g>:
+.* 1ef200e7 fcvtps s7, h7
+.* 9ef200e7 fcvtps d7, h7
+.* 9e3200e7 fcvtps d7, s7
+.* 1e7200e7 fcvtps s7, d7
+
+.* <h>:
+.* 1ef300e7 fcvtpu s7, h7
+.* 9ef300e7 fcvtpu d7, h7
+.* 9e3300e7 fcvtpu d7, s7
+.* 1e7300e7 fcvtpu s7, d7
+
+.* <i>:
+.* 1ef600e7 fcvtzs s7, h7
+.* 9ef600e7 fcvtzs d7, h7
+.* 9e3600e7 fcvtzs d7, s7
+.* 1e7600e7 fcvtzs s7, d7
+
+.* <j>:
+.* 1ef700e7 fcvtzu s7, h7
+.* 9ef700e7 fcvtzu d7, h7
+.* 9e3700e7 fcvtzu d7, s7
+.* 1e7700e7 fcvtzu s7, d7
+
+.* <k>:
+.* 1efc00e7 scvtf h7, s7
+.* 1e7c00e7 scvtf d7, s7
+.* 9efc00e7 scvtf h7, d7
+.* 9e3c00e7 scvtf s7, d7
+
+.* <l>:
+.* 1efd00e7 ucvtf h7, s7
+.* 1e7d00e7 ucvtf d7, s7
+.* 9efd00e7 ucvtf h7, d7
+.* 9e3d00e7 ucvtf s7, d7
diff --git a/gas/testsuite/gas/aarch64/fprcvt.s b/gas/testsuite/gas/aarch64/fprcvt.s
new file mode 100644
index 00000000000..4848c9862b0
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/fprcvt.s
@@ -0,0 +1,63 @@
+/* fprcvt.s Test file for AArch64 floating-point<->fixed-point
+ conversion and floating-point<->integer conversion instructions. */
+
+a:
+ fcvtas s7, h7
+ fcvtas d7, h7
+ fcvtas d7, s7
+ fcvtas s7, d7
+b:
+ fcvtau s7, h7
+ fcvtau d7, h7
+ fcvtau d7, s7
+ fcvtau s7, d7
+c:
+ fcvtms s7, h7
+ fcvtms d7, h7
+ fcvtms d7, s7
+ fcvtms s7, d7
+d:
+ fcvtmu s7, h7
+ fcvtmu d7, h7
+ fcvtmu d7, s7
+ fcvtmu s7, d7
+e:
+ fcvtns s7, h7
+ fcvtns d7, h7
+ fcvtns d7, s7
+ fcvtns s7, d7
+f:
+ fcvtnu s7, h7
+ fcvtnu d7, h7
+ fcvtnu d7, s7
+ fcvtnu s7, d7
+g:
+ fcvtps s7, h7
+ fcvtps d7, h7
+ fcvtps d7, s7
+ fcvtps s7, d7
+h:
+ fcvtpu s7, h7
+ fcvtpu d7, h7
+ fcvtpu d7, s7
+ fcvtpu s7, d7
+i:
+ fcvtzs s7, h7
+ fcvtzs d7, h7
+ fcvtzs d7, s7
+ fcvtzs s7, d7
+j:
+ fcvtzu s7, h7
+ fcvtzu d7, h7
+ fcvtzu d7, s7
+ fcvtzu s7, d7
+k:
+ scvtf h7, s7
+ scvtf d7, s7
+ scvtf h7, d7
+ scvtf s7, d7
+l:
+ ucvtf h7, s7
+ ucvtf d7, s7
+ ucvtf h7, d7
+ ucvtf s7, d7
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index df90bb76e56..35431408fa6 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -270,6 +270,8 @@ enum aarch64_feature_bit {
AARCH64_FEATURE_SME_B16B16,
/* Armv9.5-A processors. */
AARCH64_FEATURE_V9_5A,
+ /* FPRCVT instructions. */
+ AARCH64_FEATURE_FPRCVT,
/* Virtual features. These are used to gate instructions that are enabled
by either of two (or more) sets of command line flags. */
@@ -1055,6 +1057,8 @@ enum aarch64_insn_class
floatdp3,
floatimm,
floatsel,
+ fprcvtfloat2int,
+ int2float,
ldst_immpost,
ldst_immpre,
ldst_imm9, /* immpost or immpre */
diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c
index f20bdf6ae67..cef689db326 100644
--- a/opcodes/aarch64-asm.c
+++ b/opcodes/aarch64-asm.c
@@ -2033,7 +2033,8 @@ do_special_encoding (struct aarch64_inst *inst)
{
idx = select_operand_for_sf_field_coding (inst->opcode);
value = (inst->operands[idx].qualifier == AARCH64_OPND_QLF_X
- || inst->operands[idx].qualifier == AARCH64_OPND_QLF_SP)
+ || inst->operands[idx].qualifier == AARCH64_OPND_QLF_SP
+ || inst->operands[idx].qualifier == AARCH64_OPND_QLF_S_D)
? 1 : 0;
insert_field (FLD_sf, &inst->value, value, 0);
if (inst->opcode->flags & F_N)
diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index 6552d0e202d..16cdf18e158 100644
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -2746,7 +2746,16 @@ do_special_decoding (aarch64_inst *inst)
{
idx = select_operand_for_sf_field_coding (inst->opcode);
value = extract_field (FLD_sf, inst->value, 0);
- inst->operands[idx].qualifier = get_greg_qualifier_from_value (value);
+ if (inst->opcode->iclass == fprcvtfloat2int
+ || inst->opcode->iclass == int2float)
+ {
+ if (value == 0)
+ inst->operands[idx].qualifier = AARCH64_OPND_QLF_S_S;
+ else
+ inst->operands[idx].qualifier = AARCH64_OPND_QLF_S_D;
+ }
+ else
+ inst->operands[idx].qualifier = get_greg_qualifier_from_value (value);
if (inst->operands[idx].qualifier == AARCH64_OPND_QLF_ERR)
return 0;
if ((inst->opcode->flags & F_N)
diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h
index 9ab9bdf5123..528a58d45af 100644
--- a/opcodes/aarch64-opc.h
+++ b/opcodes/aarch64-opc.h
@@ -551,6 +551,11 @@ static inline int
select_operand_for_sf_field_coding (const aarch64_opcode *opcode)
{
int idx = -1;
+ if (opcode->iclass == fprcvtfloat2int)
+ return 0;
+ else if (opcode->iclass == int2float)
+ return 1;
+
if (aarch64_get_operand_class (opcode->operands[0])
== AARCH64_OPND_CLASS_INT_REG)
/* normal case. */
@@ -572,6 +577,11 @@ static inline int
select_operand_for_fptype_field_coding (const aarch64_opcode *opcode)
{
int idx;
+ if (opcode->iclass == fprcvtfloat2int)
+ return 1;
+ else if (opcode->iclass == int2float)
+ return 0;
+
if (aarch64_get_operand_class (opcode->operands[1])
== AARCH64_OPND_CLASS_FP_REG)
/* normal case. */
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index f43e1e32b80..cefce0c0e84 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -359,6 +359,15 @@
QLF2 (S_H, X), \
}
+/* e.g. FCVTAS <Xd>, <Dn>. */
+#define QL_INT2FP_FPRCVT \
+{ \
+ QLF2(S_H,S_S), \
+ QLF2(S_H,S_D), \
+ QLF2(S_S,S_D), \
+ QLF2(S_D,S_S), \
+}
+
/* e.g. FCVTNS <Xd>, <Dn>. */
#define QL_FP2INT \
{ \
@@ -368,6 +377,15 @@
QLF2(X,S_S), \
}
+/* e.g. FCVTAS <Sd>, <Dn>. */
+#define QL_FP2INT_FPRCVT \
+{ \
+ QLF2(S_D,S_S), \
+ QLF2(S_S,S_D), \
+ QLF2(S_D,S_H), \
+ QLF2(S_S,S_H), \
+}
+
/* e.g. FMOV <Xd>, <Dn>. */
#define QL_FP2INT_FMOV \
{ \
@@ -2703,6 +2721,8 @@ static const aarch64_feature_set aarch64_feature_fp_f16 =
AARCH64_FEATURES (2, F16, FP);
static const aarch64_feature_set aarch64_feature_simd_f16 =
AARCH64_FEATURES (2, F16, SIMD);
+static const aarch64_feature_set aarch64_feature_fprcvt =
+ AARCH64_FEATURE (FPRCVT);
static const aarch64_feature_set aarch64_feature_sve =
AARCH64_FEATURE (SVE);
static const aarch64_feature_set aarch64_feature_pauth =
@@ -2880,6 +2900,7 @@ static const aarch64_feature_set aarch64_feature_sve2p1_sme2p1 =
#define RDMA &aarch64_feature_rdma
#define FP_F16 &aarch64_feature_fp_f16
#define SIMD_F16 &aarch64_feature_simd_f16
+#define FPRCVT &aarch64_feature_fprcvt
#define SVE &aarch64_feature_sve
#define PAUTH &aarch64_feature_pauth
#define COMPNUM &aarch64_feature_compnum
@@ -2986,6 +3007,8 @@ static const aarch64_feature_set aarch64_feature_sve2p1_sme2p1 =
{ NAME, OPCODE, MASK, CLASS, 0, FP_F16, OPS, QUALS, FLAGS, 0, 0, NULL }
#define SF16_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, 0, SIMD_F16, OPS, QUALS, FLAGS, 0, 0, NULL }
+#define FPRCVT_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
+ { NAME, OPCODE, MASK, CLASS, 0, FPRCVT, OPS, QUALS, FLAGS, 0, 0, NULL }
#define _SVE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
{ NAME, OPCODE, MASK, CLASS, OP, SVE, OPS, QUALS, \
FLAGS | F_STRICT, 0, TIED, NULL }
@@ -4091,32 +4114,44 @@ const struct aarch64_opcode aarch64_opcode_table[] =
/* Floating-point<->integer conversions. */
__FP_INSN ("fcvtns",0x1e200000, 0x7f3ffc00, float2int, 0, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF),
FF16_INSN ("fcvtns",0x1ee00000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF),
+ FPRCVT_INSN ("fcvtns",0x1e2a0000, 0x7f3ffc00, fprcvtfloat2int, OP2 (Fd, Fn), QL_FP2INT_FPRCVT, F_FPTYPE | F_SF),
__FP_INSN ("fcvtnu",0x1e210000, 0x7f3ffc00, float2int, 0, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF),
FF16_INSN ("fcvtnu",0x1ee10000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF),
+ FPRCVT_INSN ("fcvtnu",0x1e2b0000, 0x7f3ffc00, fprcvtfloat2int, OP2 (Fd, Fn), QL_FP2INT_FPRCVT, F_FPTYPE | F_SF),
__FP_INSN ("scvtf", 0x1e220000, 0x7f3ffc00, float2int, 0, OP2 (Fd, Rn), QL_INT2FP, F_FPTYPE | F_SF),
FF16_INSN ("scvtf", 0x1ee20000, 0x7f3ffc00, float2int, OP2 (Fd, Rn), QL_INT2FP_H, F_FPTYPE | F_SF),
+ FPRCVT_INSN ("scvtf",0x1e3c0000, 0x7f3ffc00, int2float, OP2 (Fd, Fn), QL_INT2FP_FPRCVT, F_FPTYPE | F_SF),
__FP_INSN ("ucvtf", 0x1e230000, 0x7f3ffc00, float2int, 0, OP2 (Fd, Rn), QL_INT2FP, F_FPTYPE | F_SF),
FF16_INSN ("ucvtf", 0x1ee30000, 0x7f3ffc00, float2int, OP2 (Fd, Rn), QL_INT2FP_H, F_FPTYPE | F_SF),
+ FPRCVT_INSN ("ucvtf",0x1e3d0000, 0x7f3ffc00, int2float, OP2 (Fd, Fn), QL_INT2FP_FPRCVT, F_FPTYPE | F_SF),
__FP_INSN ("fcvtas",0x1e240000, 0x7f3ffc00, float2int, 0, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF),
FF16_INSN ("fcvtas",0x1ee40000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF),
+ FPRCVT_INSN ("fcvtas",0x1e3a0000, 0x7f3ffc00, fprcvtfloat2int, OP2 (Fd, Fn), QL_FP2INT_FPRCVT, F_FPTYPE | F_SF),
__FP_INSN ("fcvtau",0x1e250000, 0x7f3ffc00, float2int, 0, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF),
FF16_INSN ("fcvtau",0x1ee50000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF),
+ FPRCVT_INSN ("fcvtau",0x1e3b0000, 0x7f3ffc00, fprcvtfloat2int, OP2 (Fd, Fn), QL_FP2INT_FPRCVT, F_FPTYPE | F_SF),
__FP_INSN ("fmov", 0x1e260000, 0x7f3ffc00, float2int, 0, OP2 (Rd, Fn), QL_FP2INT_FMOV, F_FPTYPE | F_SF),
FF16_INSN ("fmov", 0x1ee60000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF),
__FP_INSN ("fmov", 0x1e270000, 0x7f3ffc00, float2int, 0, OP2 (Fd, Rn), QL_INT2FP_FMOV, F_FPTYPE | F_SF),
FF16_INSN ("fmov", 0x1ee70000, 0x7f3ffc00, float2int, OP2 (Fd, Rn), QL_INT2FP_H, F_FPTYPE | F_SF),
__FP_INSN ("fcvtps",0x1e280000, 0x7f3ffc00, float2int, 0, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF),
FF16_INSN ("fcvtps",0x1ee80000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF),
+ FPRCVT_INSN ("fcvtps",0x1e320000, 0x7f3ffc00, fprcvtfloat2int, OP2 (Fd, Fn), QL_FP2INT_FPRCVT, F_FPTYPE | F_SF),
__FP_INSN ("fcvtpu",0x1e290000, 0x7f3ffc00, float2int, 0, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF),
FF16_INSN ("fcvtpu",0x1ee90000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF),
+ FPRCVT_INSN ("fcvtpu",0x1e330000, 0x7f3ffc00, fprcvtfloat2int, OP2 (Fd, Fn), QL_FP2INT_FPRCVT, F_FPTYPE | F_SF),
__FP_INSN ("fcvtms",0x1e300000, 0x7f3ffc00, float2int, 0, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF),
FF16_INSN ("fcvtms",0x1ef00000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF),
+ FPRCVT_INSN ("fcvtms",0x1e340000, 0x7f3ffc00, fprcvtfloat2int, OP2 (Fd, Fn), QL_FP2INT_FPRCVT, F_FPTYPE | F_SF),
__FP_INSN ("fcvtmu",0x1e310000, 0x7f3ffc00, float2int, 0, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF),
FF16_INSN ("fcvtmu",0x1ef10000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF),
+ FPRCVT_INSN ("fcvtmu",0x1e350000, 0x7f3ffc00, fprcvtfloat2int, OP2 (Fd, Fn), QL_FP2INT_FPRCVT, F_FPTYPE | F_SF),
__FP_INSN ("fcvtzs",0x1e380000, 0x7f3ffc00, float2int, 0, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF),
FF16_INSN ("fcvtzs",0x1ef80000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF),
+ FPRCVT_INSN ("fcvtzs",0x1e360000, 0x7f3ffc00, fprcvtfloat2int, OP2 (Fd, Fn), QL_FP2INT_FPRCVT, F_FPTYPE | F_SF),
__FP_INSN ("fcvtzu",0x1e390000, 0x7f3ffc00, float2int, 0, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF),
FF16_INSN ("fcvtzu",0x1ef90000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF),
+ FPRCVT_INSN ("fcvtzu",0x1e370000, 0x7f3ffc00, fprcvtfloat2int, OP2 (Fd, Fn), QL_FP2INT_FPRCVT, F_FPTYPE | F_SF),
__FP_INSN ("fmov", 0x9eae0000, 0xfffffc00, float2int, 0, OP2 (Rd, VnD1), QL_XVD1, 0),
__FP_INSN ("fmov", 0x9eaf0000, 0xfffffc00, float2int, 0, OP2 (VdD1, Rn), QL_VD1X, 0),
JSCVT_INSN ("fjcvtzs", 0x1e7e0000, 0xfffffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_W_D, 0),
--
2.34.1
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