[PATCH v2] aarch64: Support for FEAT_SVE_F16F32MM, FEAT_F8F16M, FEAT_F8F32MM
Ezra.Sitorus@arm.com
Ezra.Sitorus@arm.com
Mon Jun 2 13:05:52 GMT 2025
From: Ezra Sitorus <ezra.sitorus@arm.com>
FEAT_SVE_F16F32MM introduces the SVE half-precision floating-point
matrix multiply-accumulate to single-precision instruction.
FEAT_F8F32MM introduces the Advanced SIMD 8-bit floating-point matrix
multiply-accumulate to single-precision instruction.
FEAT_F8F16MM introduces the Advanced SIMD 8-bit floating-point matrix
multiply-accumulate to half-precision instruction.
---
I've addressed Alice's comments from the v1 patch. This includes:
*) using the looser feature dependencies agrees with LLVM
*) splitting up of tests to have non-sve and sve versions
*) remove the unneeded feature bits
*) renaming variables for consistency.
Regression tested on aarch64-none-linux-gnu.
Ezra
gas/config/tc-aarch64.c | 3 ++
gas/doc/c-aarch64.texi | 6 ++++
gas/testsuite/gas/aarch64/f8f16mm-bad.d | 4 +++
gas/testsuite/gas/aarch64/f8f16mm-bad.l | 9 ++++++
gas/testsuite/gas/aarch64/f8f16mm.d | 18 +++++++++++
gas/testsuite/gas/aarch64/f8f16mm.s | 9 ++++++
gas/testsuite/gas/aarch64/f8f16mm_sve2-bad.d | 4 +++
gas/testsuite/gas/aarch64/f8f16mm_sve2-bad.l | 9 ++++++
gas/testsuite/gas/aarch64/f8f16mm_sve2.d | 18 +++++++++++
gas/testsuite/gas/aarch64/f8f16mm_sve2.s | 9 ++++++
gas/testsuite/gas/aarch64/f8f32mm-bad.d | 4 +++
gas/testsuite/gas/aarch64/f8f32mm-bad.l | 9 ++++++
gas/testsuite/gas/aarch64/f8f32mm.d | 18 +++++++++++
gas/testsuite/gas/aarch64/f8f32mm.s | 9 ++++++
gas/testsuite/gas/aarch64/f8f32mm_sve2-bad.d | 4 +++
gas/testsuite/gas/aarch64/f8f32mm_sve2-bad.l | 9 ++++++
gas/testsuite/gas/aarch64/f8f32mm_sve2.d | 18 +++++++++++
gas/testsuite/gas/aarch64/f8f32mm_sve2.s | 9 ++++++
gas/testsuite/gas/aarch64/sve-f16f32mm-bad.d | 4 +++
gas/testsuite/gas/aarch64/sve-f16f32mm-bad.l | 9 ++++++
gas/testsuite/gas/aarch64/sve-f16f32mm.d | 18 +++++++++++
gas/testsuite/gas/aarch64/sve-f16f32mm.s | 9 ++++++
include/opcode/aarch64.h | 6 ++++
opcodes/aarch64-tbl.h | 34 ++++++++++++++++++++
24 files changed, 249 insertions(+)
create mode 100644 gas/testsuite/gas/aarch64/f8f16mm-bad.d
create mode 100644 gas/testsuite/gas/aarch64/f8f16mm-bad.l
create mode 100644 gas/testsuite/gas/aarch64/f8f16mm.d
create mode 100644 gas/testsuite/gas/aarch64/f8f16mm.s
create mode 100644 gas/testsuite/gas/aarch64/f8f16mm_sve2-bad.d
create mode 100644 gas/testsuite/gas/aarch64/f8f16mm_sve2-bad.l
create mode 100644 gas/testsuite/gas/aarch64/f8f16mm_sve2.d
create mode 100644 gas/testsuite/gas/aarch64/f8f16mm_sve2.s
create mode 100644 gas/testsuite/gas/aarch64/f8f32mm-bad.d
create mode 100644 gas/testsuite/gas/aarch64/f8f32mm-bad.l
create mode 100644 gas/testsuite/gas/aarch64/f8f32mm.d
create mode 100644 gas/testsuite/gas/aarch64/f8f32mm.s
create mode 100644 gas/testsuite/gas/aarch64/f8f32mm_sve2-bad.d
create mode 100644 gas/testsuite/gas/aarch64/f8f32mm_sve2-bad.l
create mode 100644 gas/testsuite/gas/aarch64/f8f32mm_sve2.d
create mode 100644 gas/testsuite/gas/aarch64/f8f32mm_sve2.s
create mode 100644 gas/testsuite/gas/aarch64/sve-f16f32mm-bad.d
create mode 100644 gas/testsuite/gas/aarch64/sve-f16f32mm-bad.l
create mode 100644 gas/testsuite/gas/aarch64/sve-f16f32mm.d
create mode 100644 gas/testsuite/gas/aarch64/sve-f16f32mm.s
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index acb56044fb5..6be807a8b49 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -10710,6 +10710,9 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
{"sve-b16b16", AARCH64_FEATURE (SVE_B16B16), AARCH64_NO_FEATURES},
{"sme2p1", AARCH64_FEATURE (SME2p1), AARCH64_FEATURE (SME2)},
{"sve2p1", AARCH64_FEATURE (SVE2p1), AARCH64_FEATURE (SVE2)},
+ {"sve-f16f32mm", AARCH64_FEATURE (SVE_F16F32MM), AARCH64_FEATURE (SVE)},
+ {"f8f32mm", AARCH64_FEATURE (F8F32MM), AARCH64_FEATURES (2, SIMD, FP8)},
+ {"f8f16mm", AARCH64_FEATURE (F8F16MM), AARCH64_FEATURES (2, SIMD, FP8)},
{"rcpc3", AARCH64_FEATURE (RCPC3), AARCH64_FEATURE (RCPC2)},
{"cpa", AARCH64_FEATURE (CPA), AARCH64_NO_FEATURES},
{"faminmax", AARCH64_FEATURE (FAMINMAX), AARCH64_FEATURE (SIMD)},
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index 10888d1e78f..db28a2a9c6a 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -185,6 +185,10 @@ automatically cause those extensions to be disabled.
@tab Enable the F32 Matrix Multiply extension
@item @code{f64mm} @tab @code{sve}
@tab Enable the F64 Matrix Multiply extension.
+@item @code{f8f16mm} @tab @code{simd} @code{fp8}
+ @tab Enable 8-bit floating-point matrix multiply-accumulate to half-precision instructions.
+@item @code{f8f32mm} @tab @code{simd} @code{fp}
+ @tab Enable 8-bit floating-point matrix multiply-accumulate to single-precision instructions.
@item @code{fcma} @tab @code{fp16}, @code{simd}
@tab Enable the complex number SIMD extensions.
@item @code{flagm} @tab
@@ -297,6 +301,8 @@ automatically cause those extensions to be disabled.
@tab Enable the Scalable Vector Extension.
@item @code{sve-b16b16} @tab
@tab Enable the SVE B16B16 extension. These instructions also require either @code{+sve2} or @code{+sme2}.
+@item @code{sve-f16f32mm} @tab @code{sve2}
+@tab Enable the SVE_F16F32MM extension.
@item @code{sve2} @tab @code{sve}
@tab Enable SVE2.
@item @code{sve2-aes} @tab @code{sve2}, @code{aes}
diff --git a/gas/testsuite/gas/aarch64/f8f16mm-bad.d b/gas/testsuite/gas/aarch64/f8f16mm-bad.d
new file mode 100644
index 00000000000..9e034e1cd3e
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/f8f16mm-bad.d
@@ -0,0 +1,4 @@
+#name: Illegal test of F8F16MM FMMLA instruction
+#as: -march=armv8-a
+#source: f8f16mm.s
+#error_output: f8f16mm-bad.l
diff --git a/gas/testsuite/gas/aarch64/f8f16mm-bad.l b/gas/testsuite/gas/aarch64/f8f16mm-bad.l
new file mode 100644
index 00000000000..01acbac92a6
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/f8f16mm-bad.l
@@ -0,0 +1,9 @@
+[^:]*: Assembler messages:
+.*: Error: selected processor does not support `fmmla v0.8h,v0.16b,v0.16b'
+.*: Error: selected processor does not support `fmmla v0.8h,v0.16b,v31.16b'
+.*: Error: selected processor does not support `fmmla v0.8h,v31.16b,v0.16b'
+.*: Error: selected processor does not support `fmmla v0.8h,v31.16b,v31.16b'
+.*: Error: selected processor does not support `fmmla v31.8h,v0.16b,v0.16b'
+.*: Error: selected processor does not support `fmmla v31.8h,v0.16b,v31.16b'
+.*: Error: selected processor does not support `fmmla v31.8h,v31.16b,v0.16b'
+.*: Error: selected processor does not support `fmmla v31.8h,v31.16b,v31.16b'
diff --git a/gas/testsuite/gas/aarch64/f8f16mm.d b/gas/testsuite/gas/aarch64/f8f16mm.d
new file mode 100644
index 00000000000..bcfc9194cc6
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/f8f16mm.d
@@ -0,0 +1,18 @@
+#name: F8F16MM FMMLA instructions
+#as: -march=armv8-a+f8f16mm
+#objdump: -dr
+
+.*: file format .*
+
+
+Disassembly of section .*:
+
+.* <a>:
+.*: 6e00ec00 fmmla v0.8h, v0.16b, v0.16b
+.*: 6e1fec00 fmmla v0.8h, v0.16b, v31.16b
+.*: 6e00efe0 fmmla v0.8h, v31.16b, v0.16b
+.*: 6e1fefe0 fmmla v0.8h, v31.16b, v31.16b
+.*: 6e00ec1f fmmla v31.8h, v0.16b, v0.16b
+.*: 6e1fec1f fmmla v31.8h, v0.16b, v31.16b
+.*: 6e00efff fmmla v31.8h, v31.16b, v0.16b
+.*: 6e1fefff fmmla v31.8h, v31.16b, v31.16b
diff --git a/gas/testsuite/gas/aarch64/f8f16mm.s b/gas/testsuite/gas/aarch64/f8f16mm.s
new file mode 100644
index 00000000000..41d61004175
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/f8f16mm.s
@@ -0,0 +1,9 @@
+a:
+ fmmla v0.8h, v0.16b, v0.16b
+ fmmla v0.8h, v0.16b, v31.16b
+ fmmla v0.8h, v31.16b, v0.16b
+ fmmla v0.8h, v31.16b, v31.16b
+ fmmla v31.8h, v0.16b, v0.16b
+ fmmla v31.8h, v0.16b, v31.16b
+ fmmla v31.8h, v31.16b, v0.16b
+ fmmla v31.8h, v31.16b, v31.16b
diff --git a/gas/testsuite/gas/aarch64/f8f16mm_sve2-bad.d b/gas/testsuite/gas/aarch64/f8f16mm_sve2-bad.d
new file mode 100644
index 00000000000..4e1f53bf16f
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/f8f16mm_sve2-bad.d
@@ -0,0 +1,4 @@
+#name: Illegal test of F8F16MM SVE2 FMMLA instruction
+#as: -march=armv8-a
+#source: f8f16mm_sve2.s
+#error_output: f8f16mm_sve2-bad.l
diff --git a/gas/testsuite/gas/aarch64/f8f16mm_sve2-bad.l b/gas/testsuite/gas/aarch64/f8f16mm_sve2-bad.l
new file mode 100644
index 00000000000..3560c17e415
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/f8f16mm_sve2-bad.l
@@ -0,0 +1,9 @@
+[^:]*: Assembler messages:
+.*: Error: selected processor does not support `fmmla z0.h,z0.b,z0.b'
+.*: Error: selected processor does not support `fmmla z0.h,z0.b,z31.b'
+.*: Error: selected processor does not support `fmmla z0.h,z31.b,z0.b'
+.*: Error: selected processor does not support `fmmla z0.h,z31.b,z31.b'
+.*: Error: selected processor does not support `fmmla z31.h,z0.b,z0.b'
+.*: Error: selected processor does not support `fmmla z31.h,z0.b,z31.b'
+.*: Error: selected processor does not support `fmmla z31.h,z31.b,z0.b'
+.*: Error: selected processor does not support `fmmla z31.h,z31.b,z31.b'
diff --git a/gas/testsuite/gas/aarch64/f8f16mm_sve2.d b/gas/testsuite/gas/aarch64/f8f16mm_sve2.d
new file mode 100644
index 00000000000..3bb69ceafae
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/f8f16mm_sve2.d
@@ -0,0 +1,18 @@
+#name: F8F16MM SVE2 FMMLA instructions
+#as: -march=armv8-a+sve2+f8f16mm
+#objdump: -dr
+
+.*: file format .*
+
+
+Disassembly of section .*:
+
+.* <a>:
+.*: 6460e000 fmmla z0.h, z0.b, z0.b
+.*: 647fe000 fmmla z0.h, z0.b, z31.b
+.*: 6460e3e0 fmmla z0.h, z31.b, z0.b
+.*: 647fe3e0 fmmla z0.h, z31.b, z31.b
+.*: 6460e01f fmmla z31.h, z0.b, z0.b
+.*: 647fe01f fmmla z31.h, z0.b, z31.b
+.*: 6460e3ff fmmla z31.h, z31.b, z0.b
+.*: 647fe3ff fmmla z31.h, z31.b, z31.b
diff --git a/gas/testsuite/gas/aarch64/f8f16mm_sve2.s b/gas/testsuite/gas/aarch64/f8f16mm_sve2.s
new file mode 100644
index 00000000000..c1a32c98c09
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/f8f16mm_sve2.s
@@ -0,0 +1,9 @@
+a:
+ fmmla z0.h, z0.b, z0.b
+ fmmla z0.h, z0.b, z31.b
+ fmmla z0.h, z31.b, z0.b
+ fmmla z0.h, z31.b, z31.b
+ fmmla z31.h, z0.b, z0.b
+ fmmla z31.h, z0.b, z31.b
+ fmmla z31.h, z31.b, z0.b
+ fmmla z31.h, z31.b, z31.b
diff --git a/gas/testsuite/gas/aarch64/f8f32mm-bad.d b/gas/testsuite/gas/aarch64/f8f32mm-bad.d
new file mode 100644
index 00000000000..3d920f0a036
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/f8f32mm-bad.d
@@ -0,0 +1,4 @@
+#name: Illegal test of F8F32MM FMMLA instruction
+#as: -march=armv8-a
+#source: f8f32mm.s
+#error_output: f8f32mm-bad.l
diff --git a/gas/testsuite/gas/aarch64/f8f32mm-bad.l b/gas/testsuite/gas/aarch64/f8f32mm-bad.l
new file mode 100644
index 00000000000..910a2e16963
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/f8f32mm-bad.l
@@ -0,0 +1,9 @@
+[^:]*: Assembler messages:
+.*: Error: selected processor does not support `fmmla v0.4s,v0.16b,v0.16b'
+.*: Error: selected processor does not support `fmmla v0.4s,v0.16b,v31.16b'
+.*: Error: selected processor does not support `fmmla v0.4s,v31.16b,v0.16b'
+.*: Error: selected processor does not support `fmmla v0.4s,v31.16b,v31.16b'
+.*: Error: selected processor does not support `fmmla v31.4s,v0.16b,v0.16b'
+.*: Error: selected processor does not support `fmmla v31.4s,v0.16b,v31.16b'
+.*: Error: selected processor does not support `fmmla v31.4s,v31.16b,v0.16b'
+.*: Error: selected processor does not support `fmmla v31.4s,v31.16b,v31.16b'
diff --git a/gas/testsuite/gas/aarch64/f8f32mm.d b/gas/testsuite/gas/aarch64/f8f32mm.d
new file mode 100644
index 00000000000..b1e6bebfd9c
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/f8f32mm.d
@@ -0,0 +1,18 @@
+#name: F8F32MM FMMLA instructions
+#as: -march=armv8-a+f8f32mm
+#objdump: -dr
+
+.*: file format .*
+
+
+Disassembly of section .*:
+
+.* <a>:
+.*: 6e80ec00 fmmla v0.4s, v0.16b, v0.16b
+.*: 6e9fec00 fmmla v0.4s, v0.16b, v31.16b
+.*: 6e80efe0 fmmla v0.4s, v31.16b, v0.16b
+.*: 6e9fefe0 fmmla v0.4s, v31.16b, v31.16b
+.*: 6e80ec1f fmmla v31.4s, v0.16b, v0.16b
+.*: 6e9fec1f fmmla v31.4s, v0.16b, v31.16b
+.*: 6e80efff fmmla v31.4s, v31.16b, v0.16b
+.*: 6e9fefff fmmla v31.4s, v31.16b, v31.16b
diff --git a/gas/testsuite/gas/aarch64/f8f32mm.s b/gas/testsuite/gas/aarch64/f8f32mm.s
new file mode 100644
index 00000000000..4c8421db179
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/f8f32mm.s
@@ -0,0 +1,9 @@
+a:
+ fmmla v0.4s, v0.16b, v0.16b
+ fmmla v0.4s, v0.16b, v31.16b
+ fmmla v0.4s, v31.16b, v0.16b
+ fmmla v0.4s, v31.16b, v31.16b
+ fmmla v31.4s, v0.16b, v0.16b
+ fmmla v31.4s, v0.16b, v31.16b
+ fmmla v31.4s, v31.16b, v0.16b
+ fmmla v31.4s, v31.16b, v31.16b
diff --git a/gas/testsuite/gas/aarch64/f8f32mm_sve2-bad.d b/gas/testsuite/gas/aarch64/f8f32mm_sve2-bad.d
new file mode 100644
index 00000000000..200f49c93a2
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/f8f32mm_sve2-bad.d
@@ -0,0 +1,4 @@
+#name: Illegal test of F8F32MM SVE2 FMMLA instruction
+#as: -march=armv8-a
+#source: f8f32mm_sve2.s
+#error_output: f8f32mm_sve2-bad.l
diff --git a/gas/testsuite/gas/aarch64/f8f32mm_sve2-bad.l b/gas/testsuite/gas/aarch64/f8f32mm_sve2-bad.l
new file mode 100644
index 00000000000..46b62b2736c
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/f8f32mm_sve2-bad.l
@@ -0,0 +1,9 @@
+[^:]*: Assembler messages:
+.*: Error: selected processor does not support `fmmla z0.s,z0.b,z0.b'
+.*: Error: selected processor does not support `fmmla z0.s,z0.b,z31.b'
+.*: Error: selected processor does not support `fmmla z0.s,z31.b,z0.b'
+.*: Error: selected processor does not support `fmmla z0.s,z31.b,z31.b'
+.*: Error: selected processor does not support `fmmla z31.s,z0.b,z0.b'
+.*: Error: selected processor does not support `fmmla z31.s,z0.b,z31.b'
+.*: Error: selected processor does not support `fmmla z31.s,z31.b,z0.b'
+.*: Error: selected processor does not support `fmmla z31.s,z31.b,z31.b'
diff --git a/gas/testsuite/gas/aarch64/f8f32mm_sve2.d b/gas/testsuite/gas/aarch64/f8f32mm_sve2.d
new file mode 100644
index 00000000000..30670c989a4
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/f8f32mm_sve2.d
@@ -0,0 +1,18 @@
+#name: F8F32MM SVE2 FMMLA instructions
+#as: -march=armv8-a+sve2+f8f32mm
+#objdump: -dr
+
+.*: file format .*
+
+
+Disassembly of section .*:
+
+.* <a>:
+.*: 6420e000 fmmla z0.s, z0.b, z0.b
+.*: 643fe000 fmmla z0.s, z0.b, z31.b
+.*: 6420e3e0 fmmla z0.s, z31.b, z0.b
+.*: 643fe3e0 fmmla z0.s, z31.b, z31.b
+.*: 6420e01f fmmla z31.s, z0.b, z0.b
+.*: 643fe01f fmmla z31.s, z0.b, z31.b
+.*: 6420e3ff fmmla z31.s, z31.b, z0.b
+.*: 643fe3ff fmmla z31.s, z31.b, z31.b
diff --git a/gas/testsuite/gas/aarch64/f8f32mm_sve2.s b/gas/testsuite/gas/aarch64/f8f32mm_sve2.s
new file mode 100644
index 00000000000..a293e3f1391
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/f8f32mm_sve2.s
@@ -0,0 +1,9 @@
+a:
+ fmmla z0.s, z0.b, z0.b
+ fmmla z0.s, z0.b, z31.b
+ fmmla z0.s, z31.b, z0.b
+ fmmla z0.s, z31.b, z31.b
+ fmmla z31.s, z0.b, z0.b
+ fmmla z31.s, z0.b, z31.b
+ fmmla z31.s, z31.b, z0.b
+ fmmla z31.s, z31.b, z31.b
diff --git a/gas/testsuite/gas/aarch64/sve-f16f32mm-bad.d b/gas/testsuite/gas/aarch64/sve-f16f32mm-bad.d
new file mode 100644
index 00000000000..3adce337592
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve-f16f32mm-bad.d
@@ -0,0 +1,4 @@
+#name: Illegal test of SVE_F16F32MM FMMLA instruction
+#as: -march=armv8-a
+#source: sve-f16f32mm.s
+#error_output: sve-f16f32mm-bad.l
diff --git a/gas/testsuite/gas/aarch64/sve-f16f32mm-bad.l b/gas/testsuite/gas/aarch64/sve-f16f32mm-bad.l
new file mode 100644
index 00000000000..bb955681bae
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve-f16f32mm-bad.l
@@ -0,0 +1,9 @@
+[^:]*: Assembler messages:
+.*: Error: selected processor does not support `fmmla z0.s,z0.h,z0.h'
+.*: Error: selected processor does not support `fmmla z0.s,z0.h,z31.h'
+.*: Error: selected processor does not support `fmmla z0.s,z31.h,z0.h'
+.*: Error: selected processor does not support `fmmla z0.s,z31.h,z31.h'
+.*: Error: selected processor does not support `fmmla z31.s,z0.h,z0.h'
+.*: Error: selected processor does not support `fmmla z31.s,z0.h,z31.h'
+.*: Error: selected processor does not support `fmmla z31.s,z31.h,z0.h'
+.*: Error: selected processor does not support `fmmla z31.s,z31.h,z31.h'
diff --git a/gas/testsuite/gas/aarch64/sve-f16f32mm.d b/gas/testsuite/gas/aarch64/sve-f16f32mm.d
new file mode 100644
index 00000000000..8b72bf2b681
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve-f16f32mm.d
@@ -0,0 +1,18 @@
+#name: SVE_F16F32MM FMMLA instructions
+#as: -march=armv8-a+sve-f16f32mm
+#objdump: -dr
+
+.*: file format .*
+
+
+Disassembly of section .*:
+
+.* <a>:
+.*: 6420e400 fmmla z0.s, z0.h, z0.h
+.*: 643fe400 fmmla z0.s, z0.h, z31.h
+.*: 6420e7e0 fmmla z0.s, z31.h, z0.h
+.*: 643fe7e0 fmmla z0.s, z31.h, z31.h
+.*: 6420e41f fmmla z31.s, z0.h, z0.h
+.*: 643fe41f fmmla z31.s, z0.h, z31.h
+.*: 6420e7ff fmmla z31.s, z31.h, z0.h
+.*: 643fe7ff fmmla z31.s, z31.h, z31.h
diff --git a/gas/testsuite/gas/aarch64/sve-f16f32mm.s b/gas/testsuite/gas/aarch64/sve-f16f32mm.s
new file mode 100644
index 00000000000..49792581aa8
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve-f16f32mm.s
@@ -0,0 +1,9 @@
+a:
+ fmmla z0.s, z0.h, z0.h
+ fmmla z0.s, z0.h, z31.h
+ fmmla z0.s, z31.h, z0.h
+ fmmla z0.s, z31.h, z31.h
+ fmmla z31.s, z0.h, z0.h
+ fmmla z31.s, z0.h, z31.h
+ fmmla z31.s, z31.h, z0.h
+ fmmla z31.s, z31.h, z31.h
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 97215e3c46d..0e29bbfca8f 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -230,6 +230,12 @@ enum aarch64_feature_bit {
AARCH64_FEATURE_SME2p1,
/* SVE2.1 instructions. */
AARCH64_FEATURE_SVE2p1,
+ /* SVE_F16F32MM instructions. */
+ AARCH64_FEATURE_SVE_F16F32MM,
+ /* F8F32MM instructions. */
+ AARCH64_FEATURE_F8F32MM,
+ /* F8F16MM instructions. */
+ AARCH64_FEATURE_F8F16MM,
/* RCPC3 instructions. */
AARCH64_FEATURE_RCPC3,
/* Enhanced Software Step Extension. */
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 8b64eb07067..951fc7115e2 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2815,6 +2815,16 @@ static const aarch64_feature_set aarch64_feature_sme2p1 =
AARCH64_FEATURE (SME2p1);
static const aarch64_feature_set aarch64_feature_sve2p1 =
AARCH64_FEATURE (SVE2p1);
+static const aarch64_feature_set aarch64_feature_sve_f16f32mm =
+ AARCH64_FEATURE (SVE_F16F32MM);
+static const aarch64_feature_set aarch64_feature_f8f32mm =
+ AARCH64_FEATURE (F8F32MM);
+static const aarch64_feature_set aarch64_feature_f8f32mm_sve2 =
+ AARCH64_FEATURES (2, SVE2, F8F32MM);
+static const aarch64_feature_set aarch64_feature_f8f16mm =
+ AARCH64_FEATURE (F8F16MM);
+static const aarch64_feature_set aarch64_feature_f8f16mm_sve2 =
+ AARCH64_FEATURES (2, SVE2, F8F16MM);
static const aarch64_feature_set aarch64_feature_rcpc3 =
AARCH64_FEATURE (RCPC3);
static const aarch64_feature_set aarch64_feature_cpa =
@@ -2936,6 +2946,11 @@ static const aarch64_feature_set aarch64_feature_sve2p1_sme2p1 =
#define SME_B16B16 &aarch64_feature_sme_b16b16
#define SME2p1 &aarch64_feature_sme2p1
#define SVE2p1 &aarch64_feature_sve2p1
+#define SVE_F16F32MM &aarch64_feature_sve_f16f32mm
+#define F8F32MM &aarch64_feature_f8f32mm
+#define F8F32MM_SVE2 &aarch64_feature_f8f32mm_sve2
+#define F8F16MM &aarch64_feature_f8f16mm
+#define F8F16MM_SVE2 &aarch64_feature_f8f16mm_sve2
#define RCPC3 &aarch64_feature_rcpc3
#define CPA &aarch64_feature_cpa
#define CPA_SVE &aarch64_feature_cpa_sve
@@ -3032,6 +3047,16 @@ static const aarch64_feature_set aarch64_feature_sve2p1_sme2p1 =
#define SME2p1_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
{ NAME, OPCODE, MASK, CLASS, OP, SME2p1, OPS, QUALS, \
FLAGS | F_STRICT, 0, TIED, NULL }
+#define SVE_F16F32MM_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
+ { NAME, OPCODE, MASK, CLASS, OP, SVE_F16F32MM, OPS, QUALS, FLAGS, 0, 0, NULL }
+#define F8F32MM_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
+ { NAME, OPCODE, MASK, CLASS, OP, F8F32MM, OPS, QUALS, FLAGS, 0, 0, NULL }
+#define F8F32MM_SVE2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
+ { NAME, OPCODE, MASK, CLASS, OP, F8F32MM_SVE2, OPS, QUALS, FLAGS, 0, 0, NULL }
+#define F8F16MM_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
+ { NAME, OPCODE, MASK, CLASS, OP, F8F16MM, OPS, QUALS, FLAGS, 0, 0, NULL }
+#define F8F16MM_SVE2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
+ { NAME, OPCODE, MASK, CLASS, OP, F8F16MM_SVE2, OPS, QUALS, FLAGS, 0, 0, NULL }
#define SVE2_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \
{ NAME, OPCODE, MASK, CLASS, OP, SVE2, OPS, QUALS, \
FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL }
@@ -6504,6 +6529,15 @@ const struct aarch64_opcode aarch64_opcode_table[] =
BFLOAT16_INSN ("bfmlalt", 0x4fc0f000, 0xffc0f400, bfloat16, OP3 (Vd, Vn, Em16), QL_V3BFML4S, 0),
BFLOAT16_INSN ("bfmlalb", 0x0fc0f000, 0xffc0f400, bfloat16, OP3 (Vd, Vn, Em16), QL_V3BFML4S, 0),
+ /* SVE_F16F32 Matrix Multiply-Accumulate. */
+ SVE_F16F32MM_INSN ("fmmla", 0x6420e400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SHH, 0),
+ /* F8F32 Matrix Multiply-Accumulate. */
+ F8F32MM_INSN ("fmmla", 0x6e80ec00, 0xffe0fc00, asimdmisc, 0, OP3 (Vd, Vn, Vm), QL_V3FMLL4S, 0),
+ F8F32MM_SVE2_INSN ("fmmla", 0x6420e000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SBB, 0),
+ /* F8F16 Matrix Multiply-Accumulate. */
+ F8F16MM_INSN ("fmmla", 0x6e00ec00, 0xffe0fc00, asimdmisc, 0, OP3 (Vd, Vn, Vm), QL_V3FML8H, 0),
+ F8F16MM_SVE2_INSN ("fmmla", 0x6460e000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_H_B, 0),
+
/* cpyfp cpyfprn cpyfpwn cpyfpn
cpyfm cpyfmrn cpyfmwn cpyfmn
cpyfe cpyfern cpyfewn cpyfen
--
2.45.2
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