[PATCH] Set rv64gcv as default to enable vector extension for disassembly

[Andrew Burgess]

Hi!

Thanks for working on this.  Patches to the opcodes/ directory need to
be reviewed on the binutils@sourceware.org list (Added to the To: list).

>From the GDB side, I have no problems with this change, but I cannot
approve it.

Reviewed-By: Andrew Burgess <aburgess@redhat.com>

Thanks,
Andrew


Soham Gargote <sgargote@whileone.in> writes:

> Co-Authored-By: Sameer Natu <snatu@whileone.in>
>
> ---
>  opcodes/riscv-dis.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
> index f6af9c47a25..a67b51bad74 100644
> --- a/opcodes/riscv-dis.c
> +++ b/opcodes/riscv-dis.c
> @@ -1444,7 +1444,7 @@ riscv_init_disasm_info (struct disassemble_info *info)
>    pd->riscv_rps_dis.xlen = &pd->xlen;
>    pd->riscv_rps_dis.isa_spec = &pd->default_isa_spec;
>    pd->riscv_rps_dis.check_unknown_prefixed_ext = false;
> -  pd->default_arch = "rv64gc";
> +  pd->default_arch = "rv64gcv";
>    if (info->section != NULL)
>      {
>        bfd *abfd = info->section->owner;
> -- 
> 2.48.1