[PATCH] aarch64: Refactor exclusion of reg names in immediates

[Richard Sandiford]

Alice Carlotti <alice.carlotti@arm.com> writes:
>> > ---
>> >
>> > I'm not sure about the choice of flag names in this patch - if anyone has
>> > better suggestions, I'd be happy to hear them.
>> 
>> Yeah, my first reaction was that it would be good to have more mnemonic
>> names.  I can see why that isn't easy though.  Maybe:
>> 
>>   F_INVALID_IMM_SYMS_BASE
>>   F_INVALID_IMM_SYMS_SVE
>>   F_INVALID_IMM_SYMS_SVE_PN
>> 
>> Or:
>> 
>>   F_REG_SYMS_BASE
>>   F_REG_SYMS_SVE
>>   F_REG_SYMS_SVE_PN
>> 
>> But the problem with that is that the next thing we need it for might
>> not follow an obvious progression.  Numbers don't tell you much, but that
>> can also make them less misleading.
>
> Yeah, the existing logic is actually quite confusing - until I looked more
> closely I was expecting the increments to be plus Z/P vectors for SVE and plus
> ZA for SME(2), so the link to the feature names was definitely misleading
> (particularly with WSP/SP varying as well).

At least to me, treating SP as a valid immediate seemed like a historical
oversight.  Since I had to make a decision whether to carry that over
to the new instructions or not, it seemed better not to carry it over.
(I can't remember off-hand whether there were any SVE instructions
that were actually ambiguous without the SP exclusion, either in the
final ISA or in the various draft versions that this code also supported.)

ZA is more special-purpose.  I wouldn't expect it to lead to any
ambiguities.

Richard