[PATCH v3] aarch64: Support for FEAT_SVE_AES2
Alice Carlotti
alice.carlotti@arm.com
Tue Jul 8 19:31:14 GMT 2025
On Tue, Jul 08, 2025 at 11:10:53AM +0100, Ezra.Sitorus@arm.com wrote:
> From: Ezra Sitorus <ezra.sitorus@arm.com>
>
> FEAT_SVE_AES2 implements the SVE multi-vector Advanced Encryption
> Standard and 128-bit destination element polynomial multiply long
> instructions, when the PE is not in Streaming SVE mode.
> ---
> v2->v3
> *) Merged the 2 tests sve-aes2-ssve-aes.d and sve-aes2-sve2.d into 1
> file.
> *) sve2aes instructions require SVE_AES and SVE2_SSVE_AES, as mentioned
> by Alice.
> *) Fixed up illegal-sve2.l test as a result of change.
> *) Documentation updated.
>
> Regression tested on aarch64-none-linux-gnu.
>
> Ezra
>
> gas/config/tc-aarch64.c | 8 +-
> gas/doc/c-aarch64.texi | 6 +
> gas/testsuite/gas/aarch64/illegal-sve-aes2.d | 4 +
> gas/testsuite/gas/aarch64/illegal-sve-aes2.l | 103 +++++++++++++++++
> gas/testsuite/gas/aarch64/illegal-sve-aes2.s | 59 ++++++++++
> gas/testsuite/gas/aarch64/illegal-sve2.l | 12 +-
> .../gas/aarch64/sve-aes2-sve2-ssve-aes.d | 109 ++++++++++++++++++
> gas/testsuite/gas/aarch64/sve-aes2.s | 99 ++++++++++++++++
> include/opcode/aarch64.h | 9 ++
> opcodes/aarch64-opc.c | 2 +
> opcodes/aarch64-tbl.h | 25 +++-
> 11 files changed, 428 insertions(+), 8 deletions(-)
> create mode 100644 gas/testsuite/gas/aarch64/illegal-sve-aes2.d
> create mode 100644 gas/testsuite/gas/aarch64/illegal-sve-aes2.l
> create mode 100644 gas/testsuite/gas/aarch64/illegal-sve-aes2.s
> create mode 100644 gas/testsuite/gas/aarch64/sve-aes2-sve2-ssve-aes.d
> create mode 100644 gas/testsuite/gas/aarch64/sve-aes2.s
>
> diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
> index acb56044fb5..7fc7d4505c2 100644
> --- a/gas/config/tc-aarch64.c
> +++ b/gas/config/tc-aarch64.c
> @@ -6910,6 +6910,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
> case AARCH64_OPND_SME_Zn_INDEX1_16:
> case AARCH64_OPND_SME_Zn_INDEX2_15:
> case AARCH64_OPND_SME_Zn_INDEX2_16:
> + case AARCH64_OPND_SME_Zn_INDEX2_19:
> case AARCH64_OPND_SME_Zn_INDEX3_14:
> case AARCH64_OPND_SME_Zn_INDEX3_15:
> case AARCH64_OPND_SME_Zn_INDEX4_14:
> @@ -10676,7 +10677,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
> {"sve2-sm4", AARCH64_FEATURE (SVE2_SM4),
> AARCH64_FEATURES (2, SVE2, SM4)},
> {"sve2-aes", AARCH64_FEATURE (SVE2_AES),
> - AARCH64_FEATURES (2, SVE2, AES)},
> + AARCH64_FEATURES (2, SVE2, SVE_AES)},
> {"sve2-sha3", AARCH64_FEATURE (SVE2_SHA3),
> AARCH64_FEATURES (2, SVE2, SHA3)},
> {"sve2-bitperm", AARCH64_FEATURE (SVE2_BITPERM),
> @@ -10710,6 +10711,9 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
> {"sve-b16b16", AARCH64_FEATURE (SVE_B16B16), AARCH64_NO_FEATURES},
> {"sme2p1", AARCH64_FEATURE (SME2p1), AARCH64_FEATURE (SME2)},
> {"sve2p1", AARCH64_FEATURE (SVE2p1), AARCH64_FEATURE (SVE2)},
> + {"sve-aes", AARCH64_FEATURE (SVE_AES), AARCH64_NO_FEATURES},
> + {"sve-aes2", AARCH64_FEATURE (SVE_AES2), AARCH64_FEATURE (AES)},
I think you updated the wrong line here (removed dependency from sve-aes
instead of sve-aes2; the documentation update is correct).
> + {"ssve-aes", AARCH64_FEATURE (SSVE_AES), AARCH64_FEATURES (2, SME2, SVE_AES)},
> {"rcpc3", AARCH64_FEATURE (RCPC3), AARCH64_FEATURE (RCPC2)},
> {"cpa", AARCH64_FEATURE (CPA), AARCH64_NO_FEATURES},
> {"faminmax", AARCH64_FEATURE (FAMINMAX), AARCH64_FEATURE (SIMD)},
> @@ -10745,6 +10749,8 @@ struct aarch64_virtual_dependency_table
> };
>
> static const struct aarch64_virtual_dependency_table aarch64_dependencies[] = {
> + {AARCH64_FEATURE (SVE2), AARCH64_FEATURE (SVE2_SSVE_AES)},
> + {AARCH64_FEATURE (SSVE_AES), AARCH64_FEATURE (SVE2_SSVE_AES)},
> {AARCH64_FEATURES (2, FP8FMA, SVE2), AARCH64_FEATURE (FP8FMA_SVE)},
> {AARCH64_FEATURE (SSVE_FP8FMA), AARCH64_FEATURE (FP8FMA_SVE)},
> {AARCH64_FEATURES (2, FP8DOT4, SVE2), AARCH64_FEATURE (FP8DOT4_SVE)},
> diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
> index 10888d1e78f..da314942819 100644
> --- a/gas/doc/c-aarch64.texi
> +++ b/gas/doc/c-aarch64.texi
> @@ -289,12 +289,18 @@ automatically cause those extensions to be disabled.
> @tab Enable Speculative Store Bypassing Safe state read and write.
> @item @code{ssve-fp8dot2} @tab @code{sme2}, @code{fp8}
> @tab Enable the Streaming SVE FP8 2-way dot product instructions.
> +@item @code{ssve-aes} @tab @code{sme2}, @code{sve-aes}
> + @tab Enable SVE AES instructions in streaming mode.
> @item @code{ssve-fp8dot4} @tab @code{sme2}, @code{fp8}
> @tab Enable the Streaming SVE FP8 4-way dot product instructions.
> @item @code{ssve-fp8fma} @tab @code{sme2}, @code{fp8}
> @tab Enable the Streaming SVE FP8 FMA instructions.
> @item @code{sve} @tab @code{fcma}
> @tab Enable the Scalable Vector Extension.
> +@item @code{sve-aes} @tab @code{aes}
> + @tab Enable the SVE PMULL128 instructions.
> +@item @code{sve-aes2} @tab
> +@tab Enable the SVE-AES2 extension.
> @item @code{sve-b16b16} @tab
> @tab Enable the SVE B16B16 extension. These instructions also require either @code{+sve2} or @code{+sme2}.
> @item @code{sve2} @tab @code{sve}
> diff --git a/gas/testsuite/gas/aarch64/illegal-sve-aes2.d b/gas/testsuite/gas/aarch64/illegal-sve-aes2.d
> new file mode 100644
> index 00000000000..23c391dfae1
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/illegal-sve-aes2.d
> @@ -0,0 +1,4 @@
> +#name: Illegal SVE-AES2
> +#as: -march=armv8-a+sve-aes2
> +#source: illegal-sve-aes2.s
> +#error_output: illegal-sve-aes2.l
> diff --git a/gas/testsuite/gas/aarch64/illegal-sve-aes2.l b/gas/testsuite/gas/aarch64/illegal-sve-aes2.l
> new file mode 100644
> index 00000000000..3f0c1ed59d9
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/illegal-sve-aes2.l
> @@ -0,0 +1,103 @@
> +[^ :]+: Assembler messages:
> +[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `aesdimc { ?z0\.b-z1\.b ?},{ ?z0\.b-z1\.b ?},z0\.q\[4\]'
> +[^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `aesdimc { ?z0\.b-z1\.b ?},{ ?z1\.b-z2\.b ?},z0\.q\[0\]'
> +[^ :]+:[0-9]+: Error: operand mismatch -- `aesdimc { ?z0\.q-z1\.q ?},{ ?z0\.b-z1\.b ?},z0\.q\[0\]'
> +[^ :]+:[0-9]+: Info: did you mean this\?
> +[^ :]+:[0-9]+: Info: aesdimc { ?z0\.b-z1\.b ?}, { ?z0\.b-z1\.b ?}, z0\.q\[0\]
> +[^ :]+:[0-9]+: Error: operand mismatch -- `aesdimc { ?z0\.q-z1\.q ?},{ ?z0\.q-z1\.q ?},z0\.q\[0\]'
> +[^ :]+:[0-9]+: Info: did you mean this\?
> +[^ :]+:[0-9]+: Info: aesdimc { ?z0\.b-z1\.b ?}, { ?z0\.b-z1\.b ?}, z0\.q\[0\]
> +[^ :]+:[0-9]+: Error: operand mismatch -- `aesdimc { ?z0\.b-z1\.b ?},{ ?z0\.b-z1\.b ?},z0\.b\[0\]'
> +[^ :]+:[0-9]+: Info: did you mean this\?
> +[^ :]+:[0-9]+: Info: aesdimc { ?z0\.b-z1\.b ?}, { ?z0\.b-z1\.b ?}, z0\.q\[0\]
> +[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `aesdimc { ?z0\.b-z3\.b ?},{ ?z0\.b-z3\.b ?},z0\.q\[4\]'
> +[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 2 -- `aesdimc { ?z0\.b-z3\.b ?},{ ?z3\.b-z2\.b ?},z0\.q\[0\]'
> +[^ :]+:[0-9]+: Error: operand mismatch -- `aesdimc { ?z0\.q-z3\.q ?},{ ?z0\.b-z3\.b ?},z0\.q\[0\]'
> +[^ :]+:[0-9]+: Info: did you mean this\?
> +[^ :]+:[0-9]+: Info: aesdimc { ?z0\.b-z3\.b ?}, { ?z0\.b-z3\.b ?}, z0\.q\[0\]
> +[^ :]+:[0-9]+: Error: operand mismatch -- `aesdimc { ?z0\.q-z3\.q ?},{ ?z0\.q-z3\.q ?},z0\.q\[0\]'
> +[^ :]+:[0-9]+: Info: did you mean this\?
> +[^ :]+:[0-9]+: Info: aesdimc { ?z0\.b-z3\.b ?}, { ?z0\.b-z3\.b ?}, z0\.q\[0\]
> +[^ :]+:[0-9]+: Error: operand mismatch -- `aesdimc { ?z0\.b-z3\.b ?},{ ?z0\.b-z3\.b ?},z0\.b\[0\]'
> +[^ :]+:[0-9]+: Info: did you mean this\?
> +[^ :]+:[0-9]+: Info: aesdimc { ?z0\.b-z3\.b ?}, { ?z0\.b-z3\.b ?}, z0\.q\[0\]
> +[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `aesd { ?z0\.b-z1\.b ?},{ ?z0\.b-z1\.b ?},z0\.q\[4\]'
> +[^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `aesd { ?z0\.b-z1\.b ?},{ ?z1\.b-z2\.b ?},z0\.q\[0\]'
> +[^ :]+:[0-9]+: Error: operand mismatch -- `aesd { ?z0\.q-z1\.q ?},{ ?z0\.b-z1\.b ?},z0\.q\[0\]'
> +[^ :]+:[0-9]+: Info: did you mean this\?
> +[^ :]+:[0-9]+: Info: aesd { ?z0\.b-z1\.b ?}, { ?z0\.b-z1\.b ?}, z0\.q\[0\]
> +[^ :]+:[0-9]+: Error: operand mismatch -- `aesd { ?z0\.q-z1\.q ?},{ ?z0\.q-z1\.q ?},z0\.q\[0\]'
> +[^ :]+:[0-9]+: Info: did you mean this\?
> +[^ :]+:[0-9]+: Info: aesd { ?z0\.b-z1\.b ?}, { ?z0\.b-z1\.b ?}, z0\.q\[0\]
> +[^ :]+:[0-9]+: Error: operand mismatch -- `aesd { ?z0\.b-z1\.b ?},{ ?z0\.b-z1\.b ?},z0\.b\[0\]'
> +[^ :]+:[0-9]+: Info: did you mean this\?
> +[^ :]+:[0-9]+: Info: aesd { ?z0\.b-z1\.b ?}, { ?z0\.b-z1\.b ?}, z0\.q\[0\]
> +[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `aesd { ?z0\.b-z3\.b ?},{ ?z0\.b-z3\.b ?},z0\.q\[4\]'
> +[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 2 -- `aesd { ?z0\.b-z3\.b ?},{ ?z3\.b-z2\.b ?},z0\.q\[0\]'
> +[^ :]+:[0-9]+: Error: operand mismatch -- `aesd { ?z0\.q-z3\.q ?},{ ?z0\.b-z3\.b ?},z0\.q\[0\]'
> +[^ :]+:[0-9]+: Info: did you mean this\?
> +[^ :]+:[0-9]+: Info: aesd { ?z0\.b-z3\.b ?}, { ?z0\.b-z3\.b ?}, z0\.q\[0\]
> +[^ :]+:[0-9]+: Error: operand mismatch -- `aesd { ?z0\.q-z3\.q ?},{ ?z0\.q-z3\.q ?},z0\.q\[0\]'
> +[^ :]+:[0-9]+: Info: did you mean this\?
> +[^ :]+:[0-9]+: Info: aesd { ?z0\.b-z3\.b ?}, { ?z0\.b-z3\.b ?}, z0\.q\[0\]
> +[^ :]+:[0-9]+: Error: operand mismatch -- `aesd { ?z0\.b-z3\.b ?},{ ?z0\.b-z3\.b ?},z0\.b\[0\]'
> +[^ :]+:[0-9]+: Info: did you mean this\?
> +[^ :]+:[0-9]+: Info: aesd { ?z0\.b-z3\.b ?}, { ?z0\.b-z3\.b ?}, z0\.q\[0\]
> +[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `aesemc { ?z0\.b-z1\.b ?},{ ?z0\.b-z1\.b ?},z0\.q\[4\]'
> +[^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `aesemc { ?z0\.b-z1\.b ?},{ ?z1\.b-z2\.b ?},z0\.q\[0\]'
> +[^ :]+:[0-9]+: Error: operand mismatch -- `aesemc { ?z0\.q-z1\.q ?},{ ?z0\.b-z1\.b ?},z0\.q\[0\]'
> +[^ :]+:[0-9]+: Info: did you mean this\?
> +[^ :]+:[0-9]+: Info: aesemc { ?z0\.b-z1\.b ?}, { ?z0\.b-z1\.b ?}, z0\.q\[0\]
> +[^ :]+:[0-9]+: Error: operand mismatch -- `aesemc { ?z0\.q-z1\.q ?},{ ?z0\.q-z1\.q ?},z0\.q\[0\]'
> +[^ :]+:[0-9]+: Info: did you mean this\?
> +[^ :]+:[0-9]+: Info: aesemc { ?z0\.b-z1\.b ?}, { ?z0\.b-z1\.b ?}, z0\.q\[0\]
> +[^ :]+:[0-9]+: Error: operand mismatch -- `aesemc { ?z0\.b-z1\.b ?},{ ?z0\.b-z1\.b ?},z0\.b\[0\]'
> +[^ :]+:[0-9]+: Info: did you mean this\?
> +[^ :]+:[0-9]+: Info: aesemc { ?z0\.b-z1\.b ?}, { ?z0\.b-z1\.b ?}, z0\.q\[0\]
> +[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `aesemc { ?z0\.b-z3\.b ?},{ ?z0\.b-z3\.b ?},z0\.q\[4\]'
> +[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 2 -- `aesemc { ?z0\.b-z3\.b ?},{ ?z3\.b-z2\.b ?},z0\.q\[0\]'
> +[^ :]+:[0-9]+: Error: operand mismatch -- `aesemc { ?z0\.q-z3\.q ?},{ ?z0\.b-z3\.b ?},z0\.q\[0\]'
> +[^ :]+:[0-9]+: Info: did you mean this\?
> +[^ :]+:[0-9]+: Info: aesemc { ?z0\.b-z3\.b ?}, { ?z0\.b-z3\.b ?}, z0\.q\[0\]
> +[^ :]+:[0-9]+: Error: operand mismatch -- `aesemc { ?z0\.q-z3\.q ?},{ ?z0\.q-z3\.q ?},z0\.q\[0\]'
> +[^ :]+:[0-9]+: Info: did you mean this\?
> +[^ :]+:[0-9]+: Info: aesemc { ?z0\.b-z3\.b ?}, { ?z0\.b-z3\.b ?}, z0\.q\[0\]
> +[^ :]+:[0-9]+: Error: operand mismatch -- `aesemc { ?z0\.b-z3\.b ?},{ ?z0\.b-z3\.b ?},z0\.b\[0\]'
> +[^ :]+:[0-9]+: Info: did you mean this\?
> +[^ :]+:[0-9]+: Info: aesemc { ?z0\.b-z3\.b ?}, { ?z0\.b-z3\.b ?}, z0\.q\[0\]
> +[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `aese { ?z0\.b-z1\.b ?},{ ?z0\.b-z1\.b ?},z0\.q\[4\]'
> +[^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `aese { ?z0\.b-z1\.b ?},{ ?z1\.b-z2\.b ?},z0\.q\[0\]'
> +[^ :]+:[0-9]+: Error: operand mismatch -- `aese { ?z0\.q-z1\.q ?},{ ?z0\.b-z1\.b ?},z0\.q\[0\]'
> +[^ :]+:[0-9]+: Info: did you mean this\?
> +[^ :]+:[0-9]+: Info: aese { ?z0\.b-z1\.b ?}, { ?z0\.b-z1\.b ?}, z0\.q\[0\]
> +[^ :]+:[0-9]+: Error: operand mismatch -- `aese { ?z0\.q-z1\.q ?},{ ?z0\.q-z1\.q ?},z0\.q\[0\]'
> +[^ :]+:[0-9]+: Info: did you mean this\?
> +[^ :]+:[0-9]+: Info: aese { ?z0\.b-z1\.b ?}, { ?z0\.b-z1\.b ?}, z0\.q\[0\]
> +[^ :]+:[0-9]+: Error: operand mismatch -- `aese { ?z0\.b-z1\.b ?},{ ?z0\.b-z1\.b ?},z0\.b\[0\]'
> +[^ :]+:[0-9]+: Info: did you mean this\?
> +[^ :]+:[0-9]+: Info: aese { ?z0\.b-z1\.b ?}, { ?z0\.b-z1\.b ?}, z0\.q\[0\]
> +[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `aese { ?z0\.b-z3\.b ?},{ ?z0\.b-z3\.b ?},z0\.q\[4\]'
> +[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 2 -- `aese { ?z0\.b-z3\.b ?},{ ?z3\.b-z2\.b ?},z0\.q\[0\]'
> +[^ :]+:[0-9]+: Error: operand mismatch -- `aese { ?z0\.q-z3\.q ?},{ ?z0\.b-z3\.b ?},z0\.q\[0\]'
> +[^ :]+:[0-9]+: Info: did you mean this\?
> +[^ :]+:[0-9]+: Info: aese { ?z0\.b-z3\.b ?}, { ?z0\.b-z3\.b ?}, z0\.q\[0\]
> +[^ :]+:[0-9]+: Error: operand mismatch -- `aese { ?z0\.q-z3\.q ?},{ ?z0\.q-z3\.q ?},z0\.q\[0\]'
> +[^ :]+:[0-9]+: Info: did you mean this\?
> +[^ :]+:[0-9]+: Info: aese { ?z0\.b-z3\.b ?}, { ?z0\.b-z3\.b ?}, z0\.q\[0\]
> +[^ :]+:[0-9]+: Error: operand mismatch -- `aese { ?z0\.b-z3\.b ?},{ ?z0\.b-z3\.b ?},z0\.b\[0\]'
> +[^ :]+:[0-9]+: Info: did you mean this\?
> +[^ :]+:[0-9]+: Info: aese { ?z0\.b-z3\.b ?}, { ?z0\.b-z3\.b ?}, z0\.q\[0\]
> +[^ :]+:[0-9]+: Error: operand mismatch -- `pmlal { ?z0\.b-z1\.b},z0\.d,z0\.d'
> +[^ :]+:[0-9]+: Info: did you mean this\?
> +[^ :]+:[0-9]+: Info: pmlal { ?z0\.q-z1\.q}, z0\.d, z0\.d
> +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 1 -- `pmlal { ?z0\.q-z3\.q},z0\.d,z0\.d'
> +[^ :]+:[0-9]+: Error: missing braces at operand 1 -- `pmlal z0\.q,z0\.q,z0\.d'
> +[^ :]+:[0-9]+: Error: missing braces at operand 1 -- `pmlal z0\.q,{ ?z0\.q-z1\.q},z0\.d'
> +[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `pmlal { ?z0\.b-z1\.b},z0\.d,{ ?z1\.d-z2\.d}'
> +[^ :]+:[0-9]+: Error: operand mismatch -- `pmull { ?z0\.b-z1\.b},z0\.d,z0\.d'
> +[^ :]+:[0-9]+: Info: did you mean this\?
> +[^ :]+:[0-9]+: Info: pmull { ?z0\.q-z1\.q}, z0\.d, z0\.d
> +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 1 -- `pmull { ?z0\.q-z3\.q},z0\.d,z0\.d'
> +[^ :]+:[0-9]+: Error: missing braces at operand 1 -- `pmull z0\.q,z0\.q,z0\.d'
> +[^ :]+:[0-9]+: Error: missing braces at operand 1 -- `pmull z0\.q,{ ?z0\.q-z1\.q},z0\.d'
> +[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `pmull { ?z0\.b-z1\.b},z0\.d,{ ?z1\.d-z2\.d}'
> diff --git a/gas/testsuite/gas/aarch64/illegal-sve-aes2.s b/gas/testsuite/gas/aarch64/illegal-sve-aes2.s
> new file mode 100644
> index 00000000000..4eb7810862e
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/illegal-sve-aes2.s
> @@ -0,0 +1,59 @@
> +aesdimc {z0.b-z1.b}, {z0.b-z1.b}, z0.q[4]
> +aesdimc {z0.b-z1.b}, {z1.b-z2.b}, z0.q[0]
> +aesdimc {z0.q-z1.q}, {z0.b-z1.b}, z0.q[0]
> +aesdimc {z0.q-z1.q}, {z0.q-z1.q}, z0.q[0]
> +aesdimc {z0.b-z1.b}, {z0.b-z1.b}, z0.b[0]
> +
> +aesdimc {z0.b-z3.b}, {z0.b-z3.b}, z0.q[4]
> +aesdimc {z0.b-z3.b}, {z3.b-z2.b}, z0.q[0]
> +aesdimc {z0.q-z3.q}, {z0.b-z3.b}, z0.q[0]
> +aesdimc {z0.q-z3.q}, {z0.q-z3.q}, z0.q[0]
> +aesdimc {z0.b-z3.b}, {z0.b-z3.b}, z0.b[0]
> +
> +aesd {z0.b-z1.b}, {z0.b-z1.b}, z0.q[4]
> +aesd {z0.b-z1.b}, {z1.b-z2.b}, z0.q[0]
> +aesd {z0.q-z1.q}, {z0.b-z1.b}, z0.q[0]
> +aesd {z0.q-z1.q}, {z0.q-z1.q}, z0.q[0]
> +aesd {z0.b-z1.b}, {z0.b-z1.b}, z0.b[0]
> +
> +aesd {z0.b-z3.b}, {z0.b-z3.b}, z0.q[4]
> +aesd {z0.b-z3.b}, {z3.b-z2.b}, z0.q[0]
> +aesd {z0.q-z3.q}, {z0.b-z3.b}, z0.q[0]
> +aesd {z0.q-z3.q}, {z0.q-z3.q}, z0.q[0]
> +aesd {z0.b-z3.b}, {z0.b-z3.b}, z0.b[0]
> +
> +aesemc {z0.b-z1.b}, {z0.b-z1.b}, z0.q[4]
> +aesemc {z0.b-z1.b}, {z1.b-z2.b}, z0.q[0]
> +aesemc {z0.q-z1.q}, {z0.b-z1.b}, z0.q[0]
> +aesemc {z0.q-z1.q}, {z0.q-z1.q}, z0.q[0]
> +aesemc {z0.b-z1.b}, {z0.b-z1.b}, z0.b[0]
> +
> +aesemc {z0.b-z3.b}, {z0.b-z3.b}, z0.q[4]
> +aesemc {z0.b-z3.b}, {z3.b-z2.b}, z0.q[0]
> +aesemc {z0.q-z3.q}, {z0.b-z3.b}, z0.q[0]
> +aesemc {z0.q-z3.q}, {z0.q-z3.q}, z0.q[0]
> +aesemc {z0.b-z3.b}, {z0.b-z3.b}, z0.b[0]
> +
> +aese {z0.b-z1.b}, {z0.b-z1.b}, z0.q[4]
> +aese {z0.b-z1.b}, {z1.b-z2.b}, z0.q[0]
> +aese {z0.q-z1.q}, {z0.b-z1.b}, z0.q[0]
> +aese {z0.q-z1.q}, {z0.q-z1.q}, z0.q[0]
> +aese {z0.b-z1.b}, {z0.b-z1.b}, z0.b[0]
> +
> +aese {z0.b-z3.b}, {z0.b-z3.b}, z0.q[4]
> +aese {z0.b-z3.b}, {z3.b-z2.b}, z0.q[0]
> +aese {z0.q-z3.q}, {z0.b-z3.b}, z0.q[0]
> +aese {z0.q-z3.q}, {z0.q-z3.q}, z0.q[0]
> +aese {z0.b-z3.b}, {z0.b-z3.b}, z0.b[0]
> +
> +pmlal {z0.b-z1.b}, z0.d, z0.d
> +pmlal {z0.q-z3.q}, z0.d, z0.d
> +pmlal z0.q, z0.q, z0.d
> +pmlal z0.q, {z0.q-z1.q}, z0.d
> +pmlal {z0.b-z1.b}, z0.d, {z1.d-z2.d}
> +
> +pmull {z0.b-z1.b}, z0.d, z0.d
> +pmull {z0.q-z3.q}, z0.d, z0.d
> +pmull z0.q, z0.q, z0.d
> +pmull z0.q, {z0.q-z1.q}, z0.d
> +pmull {z0.b-z1.b}, z0.d, {z1.d-z2.d}
> diff --git a/gas/testsuite/gas/aarch64/illegal-sve2.l b/gas/testsuite/gas/aarch64/illegal-sve2.l
> index b5e166259bd..afefd5bf364 100644
> --- a/gas/testsuite/gas/aarch64/illegal-sve2.l
> +++ b/gas/testsuite/gas/aarch64/illegal-sve2.l
> @@ -50,27 +50,27 @@
> [^ :]+:[0-9]+: Error: expected a register at operand 1 -- `addp z32\.s,p0/m,z32\.s,z0\.s'
> [^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `addp z0\.s,p0/m,z0\.s,z32\.s'
> [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `addp z0\.s,p8/m,z0\.s,z0\.s'
> -[^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `aesd z0\.b,z0\.b,z0\.b'
> +[^ :]+:[0-9]+: Warning: SVE instruction expected after `movprfx' -- `aesd z0\.b,z0\.b,z0\.b'
> [^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `aesd z0\.b,z1\.b,z0\.b'
> [^ :]+:[0-9]+: Error: operand mismatch -- `aesd z0\.b,z0\.s,z0\.b'
> [^ :]+:[0-9]+: Info: did you mean this\?
> [^ :]+:[0-9]+: Info: aesd z0\.b, z0\.b, z0\.b
> -[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `aesd z32\.b,z0\.b,z0\.b'
> +[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `aesd z32\.b,z0\.b,z0\.b'
> [^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `aesd z0\.b,z0\.b,z32\.b'
> -[^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `aese z0\.b,z0\.b,z0\.b'
> +[^ :]+:[0-9]+: Warning: SVE instruction expected after `movprfx' -- `aese z0\.b,z0\.b,z0\.b'
> [^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `aese z0\.b,z1\.b,z0\.b'
> [^ :]+:[0-9]+: Error: operand mismatch -- `aese z0\.b,z0\.s,z0\.b'
> [^ :]+:[0-9]+: Info: did you mean this\?
> [^ :]+:[0-9]+: Info: aese z0\.b, z0\.b, z0\.b
> -[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `aese z32\.b,z0\.b,z0\.b'
> +[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `aese z32\.b,z0\.b,z0\.b'
> [^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `aese z0\.b,z0\.b,z32\.b'
> -[^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `aesimc z0\.b,z0\.b'
> +[^ :]+:[0-9]+: Warning: SVE instruction expected after `movprfx' -- `aesimc z0\.b,z0\.b'
> [^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `aesimc z0\.b,z1\.b'
> [^ :]+:[0-9]+: Error: operand mismatch -- `aesimc z0\.b,z0\.s'
> [^ :]+:[0-9]+: Info: did you mean this\?
> [^ :]+:[0-9]+: Info: aesimc z0\.b, z0\.b
> [^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `aesimc z32\.b,z0\.b'
> -[^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `aesmc z0\.b,z0\.b'
> +[^ :]+:[0-9]+: Warning: SVE instruction expected after `movprfx' -- `aesmc z0\.b,z0\.b'
> [^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `aesmc z0\.b,z1\.b'
> [^ :]+:[0-9]+: Error: operand mismatch -- `aesmc z0\.b,z0\.s'
> [^ :]+:[0-9]+: Info: did you mean this\?
For reference, these error message changes are wrong, but I'm going to fix this
before the release by changing how the choice of error message is determined.
So the change is fine for this patch.
> diff --git a/gas/testsuite/gas/aarch64/sve-aes2-sve2-ssve-aes.d b/gas/testsuite/gas/aarch64/sve-aes2-sve2-ssve-aes.d
> new file mode 100644
> index 00000000000..33ca9c41e06
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/sve-aes2-sve2-ssve-aes.d
> @@ -0,0 +1,109 @@
> +#name: Test of SVE-AES2 instructions.
> +#as: -march=armv9-a+sve-aes2+ssve-aes
> +#as: -march=armv9-a+sve-aes2+sve2
> +#source: sve-aes2.s
> +#objdump: -dr
> +
> +[^:]+: file format .*
> +
> +.*:
> +
> +.*:
> +.*: 4523ec00 aesdimc { ?z0\.b-z1\.b ?}, { ?z0\.b-z1\.b ?}, z0\.q\[0\]
> +.*: 453bec00 aesdimc { ?z0\.b-z1\.b ?}, { ?z0\.b-z1\.b ?}, z0\.q\[3\]
> +.*: 4523efe0 aesdimc { ?z0\.b-z1\.b ?}, { ?z0\.b-z1\.b ?}, z31\.q\[0\]
> +.*: 453befe0 aesdimc { ?z0\.b-z1\.b ?}, { ?z0\.b-z1\.b ?}, z31\.q\[3\]
> +.*: 4523ec1e aesdimc { ?z30\.b-z31\.b ?}, { ?z30\.b-z31\.b ?}, z0\.q\[0\]
> +.*: 453bec1e aesdimc { ?z30\.b-z31\.b ?}, { ?z30\.b-z31\.b ?}, z0\.q\[3\]
> +.*: 4523effe aesdimc { ?z30\.b-z31\.b ?}, { ?z30\.b-z31\.b ?}, z31\.q\[0\]
> +.*: 453beffe aesdimc { ?z30\.b-z31\.b ?}, { ?z30\.b-z31\.b ?}, z31\.q\[3\]
> +
> +.*:
> +.*: 4527ec00 aesdimc { ?z0\.b-z3\.b ?}, { ?z0\.b-z3\.b ?}, z0\.q\[0\]
> +.*: 453fec00 aesdimc { ?z0\.b-z3\.b ?}, { ?z0\.b-z3\.b ?}, z0\.q\[3\]
> +.*: 4527efe0 aesdimc { ?z0\.b-z3\.b ?}, { ?z0\.b-z3\.b ?}, z31\.q\[0\]
> +.*: 453fefe0 aesdimc { ?z0\.b-z3\.b ?}, { ?z0\.b-z3\.b ?}, z31\.q\[3\]
> +.*: 4527ec1c aesdimc { ?z28\.b-z31\.b ?}, { ?z28\.b-z31\.b ?}, z0\.q\[0\]
> +.*: 453fec1c aesdimc { ?z28\.b-z31\.b ?}, { ?z28\.b-z31\.b ?}, z0\.q\[3\]
> +.*: 4527effc aesdimc { ?z28\.b-z31\.b ?}, { ?z28\.b-z31\.b ?}, z31\.q\[0\]
> +.*: 453feffc aesdimc { ?z28\.b-z31\.b ?}, { ?z28\.b-z31\.b ?}, z31\.q\[3\]
> +
> +.*:
> +.*: 4522ec00 aesd { ?z0\.b-z1\.b ?}, { ?z0\.b-z1\.b ?}, z0\.q\[0\]
> +.*: 453aec00 aesd { ?z0\.b-z1\.b ?}, { ?z0\.b-z1\.b ?}, z0\.q\[3\]
> +.*: 4522efe0 aesd { ?z0\.b-z1\.b ?}, { ?z0\.b-z1\.b ?}, z31\.q\[0\]
> +.*: 453aefe0 aesd { ?z0\.b-z1\.b ?}, { ?z0\.b-z1\.b ?}, z31\.q\[3\]
> +.*: 4522ec1e aesd { ?z30\.b-z31\.b ?}, { ?z30\.b-z31\.b ?}, z0\.q\[0\]
> +.*: 453aec1e aesd { ?z30\.b-z31\.b ?}, { ?z30\.b-z31\.b ?}, z0\.q\[3\]
> +.*: 4522effe aesd { ?z30\.b-z31\.b ?}, { ?z30\.b-z31\.b ?}, z31\.q\[0\]
> +.*: 453aeffe aesd { ?z30\.b-z31\.b ?}, { ?z30\.b-z31\.b ?}, z31\.q\[3\]
> +
> +.*:
> +.*: 4526ec00 aesd { ?z0\.b-z3\.b ?}, { ?z0\.b-z3\.b ?}, z0\.q\[0\]
> +.*: 453eec00 aesd { ?z0\.b-z3\.b ?}, { ?z0\.b-z3\.b ?}, z0\.q\[3\]
> +.*: 4526efe0 aesd { ?z0\.b-z3\.b ?}, { ?z0\.b-z3\.b ?}, z31\.q\[0\]
> +.*: 453eefe0 aesd { ?z0\.b-z3\.b ?}, { ?z0\.b-z3\.b ?}, z31\.q\[3\]
> +.*: 4526ec1c aesd { ?z28\.b-z31\.b ?}, { ?z28\.b-z31\.b ?}, z0\.q\[0\]
> +.*: 453eec1c aesd { ?z28\.b-z31\.b ?}, { ?z28\.b-z31\.b ?}, z0\.q\[3\]
> +.*: 4526effc aesd { ?z28\.b-z31\.b ?}, { ?z28\.b-z31\.b ?}, z31\.q\[0\]
> +.*: 453eeffc aesd { ?z28\.b-z31\.b ?}, { ?z28\.b-z31\.b ?}, z31\.q\[3\]
> +
> +.*:
> +.*: 4523e800 aesemc { ?z0\.b-z1\.b ?}, { ?z0\.b-z1\.b ?}, z0\.q\[0\]
> +.*: 453be800 aesemc { ?z0\.b-z1\.b ?}, { ?z0\.b-z1\.b ?}, z0\.q\[3\]
> +.*: 4523ebe0 aesemc { ?z0\.b-z1\.b ?}, { ?z0\.b-z1\.b ?}, z31\.q\[0\]
> +.*: 453bebe0 aesemc { ?z0\.b-z1\.b ?}, { ?z0\.b-z1\.b ?}, z31\.q\[3\]
> +.*: 4523e81e aesemc { ?z30\.b-z31\.b ?}, { ?z30\.b-z31\.b ?}, z0\.q\[0\]
> +.*: 453be81e aesemc { ?z30\.b-z31\.b ?}, { ?z30\.b-z31\.b ?}, z0\.q\[3\]
> +.*: 4523ebfe aesemc { ?z30\.b-z31\.b ?}, { ?z30\.b-z31\.b ?}, z31\.q\[0\]
> +.*: 453bebfe aesemc { ?z30\.b-z31\.b ?}, { ?z30\.b-z31\.b ?}, z31\.q\[3\]
> +
> +.*:
> +.*: 4527e800 aesemc { ?z0\.b-z3\.b ?}, { ?z0\.b-z3\.b ?}, z0\.q\[0\]
> +.*: 453fe800 aesemc { ?z0\.b-z3\.b ?}, { ?z0\.b-z3\.b ?}, z0\.q\[3\]
> +.*: 4527ebe0 aesemc { ?z0\.b-z3\.b ?}, { ?z0\.b-z3\.b ?}, z31\.q\[0\]
> +.*: 453febe0 aesemc { ?z0\.b-z3\.b ?}, { ?z0\.b-z3\.b ?}, z31\.q\[3\]
> +.*: 4527e81c aesemc { ?z28\.b-z31\.b ?}, { ?z28\.b-z31\.b ?}, z0\.q\[0\]
> +.*: 453fe81c aesemc { ?z28\.b-z31\.b ?}, { ?z28\.b-z31\.b ?}, z0\.q\[3\]
> +.*: 4527ebfc aesemc { ?z28\.b-z31\.b ?}, { ?z28\.b-z31\.b ?}, z31\.q\[0\]
> +.*: 453febfc aesemc { ?z28\.b-z31\.b ?}, { ?z28\.b-z31\.b ?}, z31\.q\[3\]
> +
> +.*:
> +.*: 4522e800 aese { ?z0\.b-z1\.b ?}, { ?z0\.b-z1\.b ?}, z0\.q\[0\]
> +.*: 453ae800 aese { ?z0\.b-z1\.b ?}, { ?z0\.b-z1\.b ?}, z0\.q\[3\]
> +.*: 4522ebe0 aese { ?z0\.b-z1\.b ?}, { ?z0\.b-z1\.b ?}, z31\.q\[0\]
> +.*: 453aebe0 aese { ?z0\.b-z1\.b ?}, { ?z0\.b-z1\.b ?}, z31\.q\[3\]
> +.*: 4522e81e aese { ?z30\.b-z31\.b ?}, { ?z30\.b-z31\.b ?}, z0\.q\[0\]
> +.*: 453ae81e aese { ?z30\.b-z31\.b ?}, { ?z30\.b-z31\.b ?}, z0\.q\[3\]
> +.*: 4522ebfe aese { ?z30\.b-z31\.b ?}, { ?z30\.b-z31\.b ?}, z31\.q\[0\]
> +.*: 453aebfe aese { ?z30\.b-z31\.b ?}, { ?z30\.b-z31\.b ?}, z31\.q\[3\]
> +
> +.*:
> +.*: 4526e800 aese { ?z0\.b-z3\.b ?}, { ?z0\.b-z3\.b ?}, z0\.q\[0\]
> +.*: 453ee800 aese { ?z0\.b-z3\.b ?}, { ?z0\.b-z3\.b ?}, z0\.q\[3\]
> +.*: 4526ebe0 aese { ?z0\.b-z3\.b ?}, { ?z0\.b-z3\.b ?}, z31\.q\[0\]
> +.*: 453eebe0 aese { ?z0\.b-z3\.b ?}, { ?z0\.b-z3\.b ?}, z31\.q\[3\]
> +.*: 4526e81c aese { ?z28\.b-z31\.b ?}, { ?z28\.b-z31\.b ?}, z0\.q\[0\]
> +.*: 453ee81c aese { ?z28\.b-z31\.b ?}, { ?z28\.b-z31\.b ?}, z0\.q\[3\]
> +.*: 4526ebfc aese { ?z28\.b-z31\.b ?}, { ?z28\.b-z31\.b ?}, z31\.q\[0\]
> +.*: 453eebfc aese { ?z28\.b-z31\.b ?}, { ?z28\.b-z31\.b ?}, z31\.q\[3\]
> +
> +.*:
> +.*: 4520fc00 pmlal { ?z0\.q-z1\.q ?}, z0\.d, z0\.d
> +.*: 453ffc00 pmlal { ?z0\.q-z1\.q ?}, z0\.d, z31\.d
> +.*: 4520ffe0 pmlal { ?z0\.q-z1\.q ?}, z31\.d, z0\.d
> +.*: 453fffe0 pmlal { ?z0\.q-z1\.q ?}, z31\.d, z31\.d
> +.*: 4520fc1e pmlal { ?z30\.q-z31\.q ?}, z0\.d, z0\.d
> +.*: 453ffc1e pmlal { ?z30\.q-z31\.q ?}, z0\.d, z31\.d
> +.*: 4520fffe pmlal { ?z30\.q-z31\.q ?}, z31\.d, z0\.d
> +.*: 453ffffe pmlal { ?z30\.q-z31\.q ?}, z31\.d, z31\.d
> +
> +.*:
> +.*: 4520f800 pmull { ?z0\.q-z1\.q ?}, z0\.d, z0\.d
> +.*: 453ff800 pmull { ?z0\.q-z1\.q ?}, z0\.d, z31\.d
> +.*: 4520fbe0 pmull { ?z0\.q-z1\.q ?}, z31\.d, z0\.d
> +.*: 453ffbe0 pmull { ?z0\.q-z1\.q ?}, z31\.d, z31\.d
> +.*: 4520f81e pmull { ?z30\.q-z31\.q ?}, z0\.d, z0\.d
> +.*: 453ff81e pmull { ?z30\.q-z31\.q ?}, z0\.d, z31\.d
> +.*: 4520fbfe pmull { ?z30\.q-z31\.q ?}, z31\.d, z0\.d
> +.*: 453ffbfe pmull { ?z30\.q-z31\.q ?}, z31\.d, z31\.d
> diff --git a/gas/testsuite/gas/aarch64/sve-aes2.s b/gas/testsuite/gas/aarch64/sve-aes2.s
> new file mode 100644
> index 00000000000..d4f20915250
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/sve-aes2.s
> @@ -0,0 +1,99 @@
> +a:
> + aesdimc {z0.b-z1.b}, {z0.b-z1.b}, z0.q[0]
> + aesdimc {z0.b-z1.b}, {z0.b-z1.b}, z0.q[3]
> + aesdimc {z0.b-z1.b}, {z0.b-z1.b}, z31.q[0]
> + aesdimc {z0.b-z1.b}, {z0.b-z1.b}, z31.q[3]
> + aesdimc {z30.b-z31.b}, {z30.b-z31.b}, z0.q[0]
> + aesdimc {z30.b-z31.b}, {z30.b-z31.b}, z0.q[3]
> + aesdimc {z30.b-z31.b}, {z30.b-z31.b}, z31.q[0]
> + aesdimc {z30.b-z31.b}, {z30.b-z31.b}, z31.q[3]
> +
> +b:
> + aesdimc {z0.b-z3.b}, {z0.b-z3.b}, z0.q[0]
> + aesdimc {z0.b-z3.b}, {z0.b-z3.b}, z0.q[3]
> + aesdimc {z0.b-z3.b}, {z0.b-z3.b}, z31.q[0]
> + aesdimc {z0.b-z3.b}, {z0.b-z3.b}, z31.q[3]
> + aesdimc {z28.b-z31.b}, {z28.b-z31.b}, z0.q[0]
> + aesdimc {z28.b-z31.b}, {z28.b-z31.b}, z0.q[3]
> + aesdimc {z28.b-z31.b}, {z28.b-z31.b}, z31.q[0]
> + aesdimc {z28.b-z31.b}, {z28.b-z31.b}, z31.q[3]
> +
> +c:
> + aesd {z0.b-z1.b}, {z0.b-z1.b}, z0.q[0]
> + aesd {z0.b-z1.b}, {z0.b-z1.b}, z0.q[3]
> + aesd {z0.b-z1.b}, {z0.b-z1.b}, z31.q[0]
> + aesd {z0.b-z1.b}, {z0.b-z1.b}, z31.q[3]
> + aesd {z30.b-z31.b}, {z30.b-z31.b}, z0.q[0]
> + aesd {z30.b-z31.b}, {z30.b-z31.b}, z0.q[3]
> + aesd {z30.b-z31.b}, {z30.b-z31.b}, z31.q[0]
> + aesd {z30.b-z31.b}, {z30.b-z31.b}, z31.q[3]
> +
> +d:
> + aesd {z0.b-z3.b}, {z0.b-z3.b}, z0.q[0]
> + aesd {z0.b-z3.b}, {z0.b-z3.b}, z0.q[3]
> + aesd {z0.b-z3.b}, {z0.b-z3.b}, z31.q[0]
> + aesd {z0.b-z3.b}, {z0.b-z3.b}, z31.q[3]
> + aesd {z28.b-z31.b}, {z28.b-z31.b}, z0.q[0]
> + aesd {z28.b-z31.b}, {z28.b-z31.b}, z0.q[3]
> + aesd {z28.b-z31.b}, {z28.b-z31.b}, z31.q[0]
> + aesd {z28.b-z31.b}, {z28.b-z31.b}, z31.q[3]
> +
> +e:
> + aesemc {z0.b-z1.b}, {z0.b-z1.b}, z0.q[0]
> + aesemc {z0.b-z1.b}, {z0.b-z1.b}, z0.q[3]
> + aesemc {z0.b-z1.b}, {z0.b-z1.b}, z31.q[0]
> + aesemc {z0.b-z1.b}, {z0.b-z1.b}, z31.q[3]
> + aesemc {z30.b-z31.b}, {z30.b-z31.b}, z0.q[0]
> + aesemc {z30.b-z31.b}, {z30.b-z31.b}, z0.q[3]
> + aesemc {z30.b-z31.b}, {z30.b-z31.b}, z31.q[0]
> + aesemc {z30.b-z31.b}, {z30.b-z31.b}, z31.q[3]
> +
> +f:
> + aesemc {z0.b-z3.b}, {z0.b-z3.b}, z0.q[0]
> + aesemc {z0.b-z3.b}, {z0.b-z3.b}, z0.q[3]
> + aesemc {z0.b-z3.b}, {z0.b-z3.b}, z31.q[0]
> + aesemc {z0.b-z3.b}, {z0.b-z3.b}, z31.q[3]
> + aesemc {z28.b-z31.b}, {z28.b-z31.b}, z0.q[0]
> + aesemc {z28.b-z31.b}, {z28.b-z31.b}, z0.q[3]
> + aesemc {z28.b-z31.b}, {z28.b-z31.b}, z31.q[0]
> + aesemc {z28.b-z31.b}, {z28.b-z31.b}, z31.q[3]
> +
> +g:
> + aese {z0.b-z1.b}, {z0.b-z1.b}, z0.q[0]
> + aese {z0.b-z1.b}, {z0.b-z1.b}, z0.q[3]
> + aese {z0.b-z1.b}, {z0.b-z1.b}, z31.q[0]
> + aese {z0.b-z1.b}, {z0.b-z1.b}, z31.q[3]
> + aese {z30.b-z31.b}, {z30.b-z31.b}, z0.q[0]
> + aese {z30.b-z31.b}, {z30.b-z31.b}, z0.q[3]
> + aese {z30.b-z31.b}, {z30.b-z31.b}, z31.q[0]
> + aese {z30.b-z31.b}, {z30.b-z31.b}, z31.q[3]
> +
> +h:
> + aese {z0.b-z3.b}, {z0.b-z3.b}, z0.q[0]
> + aese {z0.b-z3.b}, {z0.b-z3.b}, z0.q[3]
> + aese {z0.b-z3.b}, {z0.b-z3.b}, z31.q[0]
> + aese {z0.b-z3.b}, {z0.b-z3.b}, z31.q[3]
> + aese {z28.b-z31.b}, {z28.b-z31.b}, z0.q[0]
> + aese {z28.b-z31.b}, {z28.b-z31.b}, z0.q[3]
> + aese {z28.b-z31.b}, {z28.b-z31.b}, z31.q[0]
> + aese {z28.b-z31.b}, {z28.b-z31.b}, z31.q[3]
> +
> +i:
> + pmlal {z0.q-z1.q}, z0.d, z0.d
> + pmlal {z0.q-z1.q}, z0.d, z31.d
> + pmlal {z0.q-z1.q}, z31.d, z0.d
> + pmlal {z0.q-z1.q}, z31.d, z31.d
> + pmlal {z30.q-z31.q}, z0.d, z0.d
> + pmlal {z30.q-z31.q}, z0.d, z31.d
> + pmlal {z30.q-z31.q}, z31.d, z0.d
> + pmlal {z30.q-z31.q}, z31.d, z31.d
> +
> +j:
> + pmull {z0.q-z1.q}, z0.d, z0.d
> + pmull {z0.q-z1.q}, z0.d, z31.d
> + pmull {z0.q-z1.q}, z31.d, z0.d
> + pmull {z0.q-z1.q}, z31.d, z31.d
> + pmull {z30.q-z31.q}, z0.d, z0.d
> + pmull {z30.q-z31.q}, z0.d, z31.d
> + pmull {z30.q-z31.q}, z31.d, z0.d
> + pmull {z30.q-z31.q}, z31.d, z31.d
> diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
> index dfe3f05820a..1aa24ff7e42 100644
> --- a/include/opcode/aarch64.h
> +++ b/include/opcode/aarch64.h
> @@ -230,6 +230,12 @@ enum aarch64_feature_bit {
> AARCH64_FEATURE_SME2p1,
> /* SVE2.1 instructions. */
> AARCH64_FEATURE_SVE2p1,
> + /* SVE_PMULL128 extension. */
> + AARCH64_FEATURE_SVE_AES,
> + /* SVE AES2 instructions. */
> + AARCH64_FEATURE_SVE_AES2,
> + /* SSVE_AES extension. */
> + AARCH64_FEATURE_SSVE_AES,
> /* RCPC3 instructions. */
> AARCH64_FEATURE_RCPC3,
> /* Enhanced Software Step Extension. */
> @@ -273,6 +279,8 @@ enum aarch64_feature_bit {
>
> /* Virtual features. These are used to gate instructions that are enabled
> by either of two (or more) sets of command line flags. */
> + /* +sve2 or +ssve-aes */
> + AARCH64_FEATURE_SVE2_SSVE_AES,
> /* +fp8fma+sve or +ssve-fp8fma */
> AARCH64_FEATURE_FP8FMA_SVE,
> /* +fp8dot4+sve or +ssve-fp8dot4 */
> @@ -874,6 +882,7 @@ enum aarch64_opnd
> AARCH64_OPND_SME_Zn_INDEX1_16, /* Zn[index], bits [9:5] and [16:16]. */
> AARCH64_OPND_SME_Zn_INDEX2_15, /* Zn[index], bits [9:5] and [16:15]. */
> AARCH64_OPND_SME_Zn_INDEX2_16, /* Zn[index], bits [9:5] and [17:16]. */
> + AARCH64_OPND_SME_Zn_INDEX2_19, /* Zn[index], bits [9:5] and [20:19]. */
> AARCH64_OPND_SME_Zn_INDEX3_14, /* Zn[index], bits [9:5] and [16:14]. */
> AARCH64_OPND_SME_Zn_INDEX3_15, /* Zn[index], bits [9:5] and [17:15]. */
> AARCH64_OPND_SME_Zn_INDEX4_14, /* Zn[index], bits [9:5] and [17:14]. */
> diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
> index 4f0c71696fa..8d117a931d7 100644
> --- a/opcodes/aarch64-opc.c
> +++ b/opcodes/aarch64-opc.c
> @@ -1893,6 +1893,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
> return 0;
> break;
>
> + case AARCH64_OPND_SME_Zn_INDEX2_19:
> case AARCH64_OPND_SVE_Zm2_22_INDEX:
> size = get_operand_fields_width (get_operand_from_code (type));
> if (!check_reglane (opnd, mismatch_detail, idx, "z", 0, 31, 0, 3))
> @@ -4375,6 +4376,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
> case AARCH64_OPND_SME_Zn_INDEX1_16:
> case AARCH64_OPND_SME_Zn_INDEX2_15:
> case AARCH64_OPND_SME_Zn_INDEX2_16:
> + case AARCH64_OPND_SME_Zn_INDEX2_19:
> case AARCH64_OPND_SME_Zn_INDEX3_14:
> case AARCH64_OPND_SME_Zn_INDEX3_15:
> case AARCH64_OPND_SME_Zn_INDEX4_14:
> diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
> index 8b64eb07067..e6e1558fa8d 100644
> --- a/opcodes/aarch64-tbl.h
> +++ b/opcodes/aarch64-tbl.h
> @@ -2210,6 +2210,10 @@
> QLF3(S_S,S_S,S_S), \
> QLF3(S_D,S_D,S_D), \
> }
> +#define OP_SVE_BBQ \
> +{ \
> + QLF3(S_B, S_B, S_Q) \
> +}
> #define OP_SVE_VVV_D \
> { \
> QLF3(S_D,S_D,S_D), \
> @@ -2748,7 +2752,7 @@ static const aarch64_feature_set aarch64_feature_tme =
> static const aarch64_feature_set aarch64_feature_sve2 =
> AARCH64_FEATURE (SVE2);
> static const aarch64_feature_set aarch64_feature_sve2aes =
> - AARCH64_FEATURES (2, SVE2, SVE2_AES);
> + AARCH64_FEATURES (2, SVE_AES, SVE2_SSVE_AES);
> static const aarch64_feature_set aarch64_feature_sve2sha3 =
> AARCH64_FEATURES (2, SVE2, SVE2_SHA3);
> static const aarch64_feature_set aarch64_feature_sve2sm4 =
> @@ -2815,6 +2819,8 @@ static const aarch64_feature_set aarch64_feature_sme2p1 =
> AARCH64_FEATURE (SME2p1);
> static const aarch64_feature_set aarch64_feature_sve2p1 =
> AARCH64_FEATURE (SVE2p1);
> +static const aarch64_feature_set aarch64_feature_sve_aes2 =
> + AARCH64_FEATURES (2, SVE_AES2, SVE2_SSVE_AES);
> static const aarch64_feature_set aarch64_feature_rcpc3 =
> AARCH64_FEATURE (RCPC3);
> static const aarch64_feature_set aarch64_feature_cpa =
> @@ -2936,6 +2942,7 @@ static const aarch64_feature_set aarch64_feature_sve2p1_sme2p1 =
> #define SME_B16B16 &aarch64_feature_sme_b16b16
> #define SME2p1 &aarch64_feature_sme2p1
> #define SVE2p1 &aarch64_feature_sve2p1
> +#define SVE_AES2 &aarch64_feature_sve_aes2
> #define RCPC3 &aarch64_feature_rcpc3
> #define CPA &aarch64_feature_cpa
> #define CPA_SVE &aarch64_feature_cpa_sve
> @@ -3059,6 +3066,9 @@ static const aarch64_feature_set aarch64_feature_sve2p1_sme2p1 =
> #define SVE2AES_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
> { NAME, OPCODE, MASK, CLASS, OP, SVE2_AES, OPS, QUALS, \
> FLAGS | F_STRICT, 0, TIED, NULL }
> +#define SVE_AES2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
> + { NAME, OPCODE, MASK, CLASS, OP, SVE_AES2, OPS, QUALS, \
> + FLAGS | F_STRICT, 0, TIED, NULL }
> #define SVE2SHA3_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
> { NAME, OPCODE, MASK, CLASS, OP, SVE2_SHA3, OPS, QUALS, \
> FLAGS | F_STRICT, 0, TIED, NULL }
> @@ -5785,6 +5795,17 @@ const struct aarch64_opcode aarch64_opcode_table[] =
> SVE2BITPERM_INSN ("bdep", 0x4500b400, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
> SVE2BITPERM_INSN ("bext", 0x4500b000, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
> SVE2BITPERM_INSN ("bgrp", 0x4500b800, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
> + /* SVE_AES2 instructions */
> + SVE_AES2_INSN ("aesdimc", 0x4523ec00, 0xffe7fc01, sve_misc, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zn_INDEX2_19), OP_SVE_BBQ, 0, 1),
> + SVE_AES2_INSN ("aesdimc", 0x4527ec00, 0xffe7fc03, sve_misc, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zn_INDEX2_19), OP_SVE_BBQ, 0, 1),
> + SVE_AES2_INSN ("aesd", 0x4522ec00, 0xffe7fc01, sve_misc, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zn_INDEX2_19), OP_SVE_BBQ, 0, 1),
> + SVE_AES2_INSN ("aesd", 0x4526ec00, 0xffe7fc03, sve_misc, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zn_INDEX2_19), OP_SVE_BBQ, 0, 1),
> + SVE_AES2_INSN ("aesemc", 0x4523e800, 0xffe7fc01, sve_misc, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zn_INDEX2_19), OP_SVE_BBQ, 0, 1),
> + SVE_AES2_INSN ("aesemc", 0x4527e800, 0xffe7fc03, sve_misc, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zn_INDEX2_19), OP_SVE_BBQ, 0, 1),
> + SVE_AES2_INSN ("aese", 0x4522e800, 0xffe7fc01, sve_misc, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zn_INDEX2_19), OP_SVE_BBQ, 0, 1),
> + SVE_AES2_INSN ("aese", 0x4526e800, 0xffe7fc03, sve_misc, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zn_INDEX2_19), OP_SVE_BBQ, 0, 1),
> + SVE_AES2_INSN ("pmlal", 0x4520fc00, 0xffe0fc01, sve_misc, 0, OP3 (SME_Zdnx2, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_Q_D, 0, 0),
> + SVE_AES2_INSN ("pmull", 0x4520f800, 0xffe0fc01, sve_misc, 0, OP3 (SME_Zdnx2, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_Q_D, 0, 0),
> /* SME instructions. */
> SME_INSN ("addha", 0xc0900000, 0xffff001c, sme_misc, 0, OP4 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn), OP_SVE_SMMS, 0, 0),
> SME_I16I64_INSN ("addha", 0xc0d00000, 0xffff0018, sme_misc, 0, OP4 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn), OP_SVE_DMMD, 0, 0),
> @@ -7657,6 +7678,8 @@ const struct aarch64_opcode aarch64_opcode_table[] =
> F(FLD_SVE_Zn, FLD_imm2_15), "an indexed SVE vector register") \
> Y(SVE_REG, simple_index, "SME_Zn_INDEX2_16", 0, \
> F(FLD_SVE_Zn, FLD_imm2_16), "an indexed SVE vector register") \
> + Y(SVE_REG, simple_index, "SME_Zn_INDEX2_19", 0, \
> + F(FLD_SVE_Zn, FLD_imm2_19), "an indexed SVE vector register") \
> Y(SVE_REG, simple_index, "SME_Zn_INDEX3_14", 0, \
> F(FLD_SVE_Zn, FLD_imm3_14), "an indexed SVE vector register") \
> Y(SVE_REG, simple_index, "SME_Zn_INDEX3_15", 0, \
> --
> 2.45.2
>
More information about the Binutils
mailing list