[PATCH 0/4] s390: Make vector index register operands mandatory

[Andreas Krebbel]

Hi Jens,

the patches are ok. Thanks for taking care of this! Clearly an oversight 
in my initial implementation :(

Bye,

Andreas


On 1/24/25 12:52 PM, Jens Remus wrote:
> Index register operands in a conventional displacement D, index X, and
> base (B) triplet "D(X,B)" are treated as optional.  This is because
> register 0 contents are not used in conventional addressing
> computations.  Instead a value of zero is implied.
> The assembler therefore implies register 0, if an index/base register
> is omitted (e.g. when coding "D(,B)" or "D(B)").
> The disassembler disassembles index/base register 0 as "0" instead of
> "%r0", as this clarifies that a value of zero is implied instead of
> using the contents of register 0.
>
> Vector index register operands, so far only used in the VRV instruction
> format, are different though.  Vector index register 0 contents are used
> in the addressing computation:
>
> "For VRV format instructions, a vector element is used in the formation
> of the intermediate value.  This vector element is an unsigned binary
> integer value that is added to the base address and 12-bit displacement
> to form a 64-bit intermediate sum.  The vector element is designated by
> a vector register and an element index.  A zero V field accesses the
> element in vector register zero and does not imply a zero value." [1]
>
> Therefore make the following changes to the assembler and disassembler:
>
> Patch 2 changes the disassembler to no longer omit vector index
> register 0 operands in disassembly.  Furthermore it disassembles them
> as "%v0" instead of "0" to clarify, that the vector register 0 value is
> used in the addressing computation.
>
> Patch 3 changes the assembler not to warn about vector index register 0
> being used.
>
> Patch 4 changes the assembler to require the specification of vector
> index register operands.  That is they may no longer be omitted.  This
> is a non-backward compatible change.  The rationale is that any (very
> unlikely) existing assembler code that omits the specification of
> vector index register 0, may potentially be in error, as the programmer
> may likely have assumed a value of zero to be implied instead of vector
> register 0 contents to be used.
>
> Regards,
> Jens
>
> Jens Remus (4):
>    s390: Additional tests for omitted base register operands
>    s390: Do not omit vector index register 0 in disassembly
>    s390: Do not warn about vector index register 0 in assembly
>    s390: Error if vector index register omitted in assembly
>
>   gas/config/tc-s390.c                          | 13 ++++-
>   .../gas/s390/zarch-base-index-0-err.l         | 18 ++++--
>   .../gas/s390/zarch-base-index-0-err.s         | 10 +++-
>   gas/testsuite/gas/s390/zarch-base-index-0.d   | 26 +++------
>   gas/testsuite/gas/s390/zarch-base-index-0.s   | 18 +++---
>   .../gas/s390/zarch-omitted-base-index-err.l   | 37 ++++++------
>   .../gas/s390/zarch-omitted-base-index-err.s   |  3 +
>   .../gas/s390/zarch-omitted-base-index.d       |  5 +-
>   .../gas/s390/zarch-omitted-base-index.s       |  6 +-
>   gas/testsuite/gas/s390/zarch-warn-areg-zero.l | 16 +++---
>   gas/testsuite/gas/s390/zarch-warn-areg-zero.s | 56 +++++++++----------
>   opcodes/s390-dis.c                            | 13 ++---
>   12 files changed, 121 insertions(+), 100 deletions(-)
>