[PATCH 3/3] x86: support RMPREAD insn

[Jan Beulich]

Like for RMPUPDATE documentation is about to change as far as operands
are concerned. They're merely the other way around here.

While adjustind gas documentation, also add the missing RMPQUERY
counterparts there.

--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -1214,6 +1214,7 @@ static const arch_entry cpu_arch[] =
   VECARCH (avx_ne_convert, AVX_NE_CONVERT, ANY_AVX_NE_CONVERT, reset),
   SUBARCH (rao_int, RAO_INT, RAO_INT, false),
   SUBARCH (rmpquery, RMPQUERY, ANY_RMPQUERY, false),
+  SUBARCH (rmpread, RMPREAD, ANY_RMPREAD, false),
   SUBARCH (fred, FRED, ANY_FRED, false),
   SUBARCH (lkgs, LKGS, ANY_LKGS, false),
   VECARCH (avx_vnni_int16, AVX_VNNI_INT16, ANY_AVX_VNNI_INT16, reset),
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -281,6 +281,8 @@ accept various extension mnemonics.  For
 @code{snp},
 @code{invlpgb},
 @code{tlbsync},
+@code{rmpquery},
+@code{rmpread},
 @code{svme},
 @code{gmism2},
 @code{gmiccs},
@@ -1719,8 +1721,8 @@ supported on the CPU specified.  The cho
 @item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}
 @item @samp{.padlock} @tab @samp{.clzero} @tab @samp{.mwaitx} @tab @samp{.rdpru}
 @item @samp{.mcommit} @tab @samp{.sev_es} @tab @samp{.snp} @tab @samp{.invlpgb}
-@item @samp{.tlbsync} @tab @samp{.apx_f} @tab @samp{.gmism2} @tab @samp{.gmiccs}
-@item @samp{.padlockrng2} @tab @samp{.padlockphe2}
+@item @samp{.tlbsync} @tab @samp{.rmpquery} @tab @samp{.rmpread} @tab @samp{.apx_f}
+@item @samp{.gmism2} @tab @samp{.gmiccs} @tab @samp{.padlockrng2} @tab @samp{.padlockphe2}
 
 @end multitable
 
--- a/gas/testsuite/gas/i386/snp.s
+++ b/gas/testsuite/gas/i386/snp.s
@@ -16,6 +16,8 @@ att:
         rmpadjust
         rmpadjust %rax, %rcx, %rdx
         rmpadjust %eax, %rcx, %rdx
+        rmpread %rax, (%rcx)
+        rmpread %rax, (%ecx)
 .else
         pvalidate %ax, %ecx, %edx
 .endif
@@ -36,6 +38,8 @@ intel:
         rmpadjust
         rmpadjust rax, rcx, rdx
         rmpadjust eax, rcx, rdx
+        rmpread [rcx], rax
+        rmpread [ecx], rax
 .else
         pvalidate ax, ecx, edx
 .endif
--- a/gas/testsuite/gas/i386/snp64.d
+++ b/gas/testsuite/gas/i386/snp64.d
@@ -21,6 +21,8 @@ Disassembly of section \.text:
 [ 	]*[a-f0-9]+:[ 	]+f3 0f 01 fe[ 	]+rmpadjust
 [ 	]*[a-f0-9]+:[ 	]+f3 0f 01 fe[ 	]+rmpadjust
 [ 	]*[a-f0-9]+:[ 	]+67 f3 0f 01 fe[ 	]+addr32 rmpadjust
+[ 	]*[a-f0-9]+:[ 	]+f2 0f 01 fd[ 	]+rmpread %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:[ 	]+67 f2 0f 01 fd[ 	]+rmpread %rax,\(%ecx\)
 
 [0-9a-f]+ <intel>:
 [ 	]*[a-f0-9]+:[ 	]+f2 0f 01 ff[ 	]+pvalidate
@@ -36,4 +38,6 @@ Disassembly of section \.text:
 [ 	]*[a-f0-9]+:[ 	]+f3 0f 01 fe[ 	]+rmpadjust
 [ 	]*[a-f0-9]+:[ 	]+f3 0f 01 fe[ 	]+rmpadjust
 [ 	]*[a-f0-9]+:[ 	]+67 f3 0f 01 fe[ 	]+addr32 rmpadjust
+[ 	]*[a-f0-9]+:[ 	]+f2 0f 01 fd[ 	]+rmpread %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:[ 	]+67 f2 0f 01 fd[ 	]+rmpread %rax,\(%ecx\)
 #pass
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -1347,6 +1347,7 @@ enum
   X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1,
   X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1,
   X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_1,
+  X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_3,
   X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1,
   X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3,
   X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1,
@@ -3253,6 +3254,8 @@ static const struct dis386 prefix_table[
   {
     { "rdpru", { Skip_MODRM }, 0 },
     { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_1) },
+    { Bad_Opcode },
+    { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_3) },
   },
 
   /* PREFIX_0F01_REG_7_MOD_3_RM_6 */
@@ -4632,6 +4635,12 @@ static const struct dis386 x86_64_table[
     { "rmpquery", { Skip_MODRM }, 0 },
   },
 
+  /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3 */
+  {
+    { Bad_Opcode },
+    { "rmpread",	{ DSCX, RMrAX, Skip_MODRM }, 0 },
+  },
+
   /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1 */
   {
     { Bad_Opcode },
@@ -13143,7 +13152,7 @@ OP_DSreg (instr_info *ins, int code, int
     {
       switch (ins->codep[-1])
 	{
-	case 0x01:	/* rmpupdate */
+	case 0x01:	/* rmpupdate/rmpread */
 	  break;
 	case 0x6f:	/* outsw/outsl */
 	  intel_operand_size (ins, z_mode, sizeflag);
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -251,6 +251,8 @@ static const dependency isa_dependencies
     "SEV_ES" },
   { "RMPQUERY",
     "SNP|64" },
+  { "RMPREAD",
+    "SNP|64" },
   { "TSX",
     "RTM|HLE" },
   { "TSXLDTRK",
@@ -470,6 +472,7 @@ static bitfield cpu_flags[] =
   BITFIELD (TLBSYNC),
   BITFIELD (SNP),
   BITFIELD (RMPQUERY),
+  BITFIELD (RMPREAD),
   BITFIELD (64),
   BITFIELD (No64),
 #ifdef CpuUnused
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -316,6 +316,8 @@ enum i386_cpu
   CpuSNP,
   /* RMPQUERY instruction required */
   CpuRMPQUERY,
+  /* RMPREAD instruction required */
+  CpuRMPREAD,
 
   /* NOTE: These items, which can be combined with other ISA flags above, need
      to remain second to last and in sync with CPU_FLAGS_COMMON. */
@@ -549,6 +551,7 @@ typedef union i386_cpu_flags
       unsigned int cputlbsync:1;
       unsigned int cpusnp:1;
       unsigned int cpurmpquery:1;
+      unsigned int cpurmpread:1;
       CPU_FLAGS_COMMON;
 #ifdef CpuUnused
       unsigned int unused:(CpuNumOfBits - CpuUnused);
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -3181,6 +3181,12 @@ rmpquery, 0xf30f01fd, RMPQUERY, AddrPref
 
 // RMPQUERY instruction end
 
+// RMPREAD instruction
+
+rmpread, 0xf20f01fd, RMPREAD&x64, IsString|NoSuf|NoRex64, { Acc|Qword, RegC|Unspecified|BaseIndex }
+
+// RMPREAD instruction end
+
 // RDPRU instruction
 
 rdpru, 0x0f01fd, RDPRU, NoSuf, {}