[PATCH 1/2] RISC-V: Add support for RISC-V Profiles 20/22.
Jiawei
jiawei@iscas.ac.cn
Wed Jan 22 01:13:05 GMT 2025
在 2025/1/22 0:32, Kito Cheng 写道:
>
> Wait, the point i want to make is that should check there should be an
> underline between profile name and extensions not we should check m with v
>
>
Sorry, I think I misunderstand your point, I will add this check in next
version.
BR,
Jiawei
> Jiawei <jiawei@iscas.ac.cn> 於 2025年1月21日 週二 22:04 寫道：
>
>
> 在 2025/1/21 21:29, Kito Cheng 写道:
> > -march=rva20u64v accepted without warning or error, this should just
> > reject and error, could you handle that and add a test case for both
> > -march=rva20u64v and -march=rva20u64_v
>
> Okay, I think this also present in gas with -march=rv64iv
> -mabi=lp64, I will
>
> send a new patch to fix this.
>
> ```
>
> riscv64-unknown-elf-as -march=rv64iv add.s
>
> ```
>
> >
> > On Tue, Jan 21, 2025 at 5:30 PM Jiawei <jiawei@iscas.ac.cn> wrote:
> >> ---
> >> bfd/elfxx-riscv.c | 79
> +++++++++++++++++++++++--
> >> bfd/elfxx-riscv.h | 3 +
> >> gas/NEWS | 2 +
> >> gas/doc/as.texi | 2 +-
> >> gas/doc/c-riscv.texi | 14 +++--
> >> gas/testsuite/gas/riscv/attribute-15.d | 6 ++
> >> gas/testsuite/gas/riscv/attribute-16.d | 6 ++
> >> 8 files changed, 103 insertions(+), 9 deletions(-)
> >> create mode 100644 gas/testsuite/gas/riscv/attribute-15.d
> >> create mode 100644 gas/testsuite/gas/riscv/attribute-16.d
> >>
> >> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
> >> index c9e4b03b17d..73f06056d39 100644
> >> --- a/bfd/elfxx-riscv.c
> >> +++ b/bfd/elfxx-riscv.c
> >> @@ -1022,6 +1022,12 @@ static const struct elf_reloc_map
> riscv_reloc_map[] =
> >> { BFD_RELOC_RISCV_SUB_ULEB128, R_RISCV_SUB_ULEB128 },
> >> };
> >>
> >> +struct riscv_profiles
> >> +{
> >> + const char *profile_name;
> >> + const char *profile_string;
> >> +};
> >> +
> >> /* Given a BFD reloc type, return a howto structure. */
> >>
> >> reloc_howto_type *
> >> @@ -1285,6 +1291,31 @@ static struct riscv_implicit_subset
> riscv_implicit_subsets[] =
> >> {NULL, NULL, NULL}
> >> };
> >>
> >> +/* This table records the mapping form RISC-V Profiles into
> march string. */
> >> +static struct riscv_profiles riscv_profiles_table[] =
> >> +{
> >> + /* RVI20U only contains the base extension 'i' as mandatory
> extension. */
> >> + {"rvi20u64", "rv64i"},
> >> + {"rvi20u32", "rv32i"},
> >> +
> >> + /* RVA20U contains the
> 'i,m,a,f,d,c,zicsr,zicntr,ziccif,ziccrse,ziccamoa,
> >> + zicclsm,za128rs' as mandatory extensions. */
> >> + {"rva20u64", "rv64imafdc_zicsr_zicntr_ziccif_ziccrse_ziccamoa"
> >> + "_zicclsm_za128rs"},
> >> +
> >> + /* RVA22U contains the
> 'i,m,a,f,d,c,zicsr,zihintpause,zba,zbb,zbs,zicntr,
> >> + zihpm,ziccif,ziccrse,ziccamoa,
> zicclsm,zic64b,za64rs,zicbom,zicbop,zicboz,
> >> + zfhmin,zkt' as mandatory extensions. */
> >> + {"rva22u64", "rv64imafdc_zicsr_zicntr_ziccif_ziccrse_ziccamoa"
> >> + "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop"
> >> + "_zicboz_zfhmin_zkt"},
> >> +
> >> + /* Currently we do not define S/M mode Profiles. */
> >> +
> >> + /* Terminate the list. */
> >> + {NULL, NULL}
> >> +};
> >> +
> >> /* For default_enable field, decide if the extension should
> >> be enbaled by default. */
> >>
> >> @@ -2172,6 +2203,45 @@ riscv_set_default_arch
> (riscv_parse_subset_t *rps)
> >> }
> >> }
> >>
> >> +const char *
> >> +riscv_handle_profiles (const char *p)
> >> +{
> >> + /* Checking if input string contains a Profiles.
> >> + There are two cases use Profiles in -march option:
> >> +
> >> + 1. Only use Profiles in '-march' as input
> >> + 2. Mixed Profiles with other extensions
> >> +
> >> + Use '_' to split Profiles and other extensions. */
> >> + for (int i = 0; riscv_profiles_table[i].profile_name !=
> NULL; ++i)
> >> + {
> >> + const char *match = strstr (p,
> riscv_profiles_table[i].profile_name);
> >> + const char *plus_ext = strchr (p, '_');
> >> + /* Find profile at the beginning. */
> >> + if (match != NULL && match == p)
> >> + {
> >> + /* If there's no '_' sign, return the profile_string
> directly. */
> >> + if (!plus_ext)
> >> + return riscv_profiles_table[i].profile_string;
> >> + /* If there's a '_' sign, need to add profiles with
> other ext. */
> >> + else
> >> + {
> >> + size_t arch_len = (strlen
> (riscv_profiles_table[i].profile_string)
> >> + + strlen (plus_ext));
> >> + /* Reset the input string with Profiles mandatory
> extensions,
> >> + end with '_' to connect other additional
> extensions. */
> >> + char *result = (char *) malloc (arch_len + 2);
> >> + strcpy (result,
> riscv_profiles_table[i].profile_string);
> >> + strcat (result, "_");
> >> + strcat (result, plus_ext + 1); /* skip the '_'. */
> >> + return result;
> >> + }
> >> + }
> >> + }
> >> + return p;
> >> +}
> >> +
> >> +
> >> /* Function for parsing ISA string.
> >>
> >> Return Value:
> >> @@ -2198,18 +2268,19 @@ riscv_parse_subset
> (riscv_parse_subset_t *rps,
> >> return riscv_parse_check_conflicts (rps);
> >> }
> >>
> >> - for (p = arch; *p != '\0'; p++)
> >> + p = riscv_handle_profiles (arch);
> >> +
> >> + for (const char *q = p; *q != '\0'; q++)
> >> {
> >> - if (ISUPPER (*p))
> >> + if (ISUPPER (*q))
> >> {
> >> rps->error_handler
> >> (_("%s: ISA string cannot contain uppercase letters"),
> >> - arch);
> >> + q);
> >> return false;
> >> }
> >> }
> >>
> >> - p = arch;
> >> if (startswith (p, "rv32"))
> >> {
> >> *rps->xlen = 32;
> >> diff --git a/bfd/elfxx-riscv.h b/bfd/elfxx-riscv.h
> >> index 19e04adfa6a..50bd19c3189 100644
> >> --- a/bfd/elfxx-riscv.h
> >> +++ b/bfd/elfxx-riscv.h
> >> @@ -121,6 +121,9 @@ riscv_multi_subset_supports
> (riscv_parse_subset_t *, enum riscv_insn_class);
> >> extern const char *
> >> riscv_multi_subset_supports_ext (riscv_parse_subset_t *, enum
> riscv_insn_class);
> >>
> >> +extern const char *
> >> +riscv_handle_profiles(const char*);
> >> +
> >> extern void
> >> riscv_print_extensions (void);
> >>
> >> diff --git a/gas/NEWS b/gas/NEWS
> >> index 70f3ad40dba..cddd2b31219 100644
> >> --- a/gas/NEWS
> >> +++ b/gas/NEWS
> >> @@ -34,6 +34,8 @@ Changes in 2.44:
> >> CORE-V, xcvbitmanip v1.0 and xcvsimd v1.0.
> >> SiFive, xsfvqmaccdod v1.0, xsfvqmaccqoqv1.0 and
> xsfvfnrclipxfqf v1.0.
> >>
> >> +* Add support for RISC-V Profiles 20/22.
> >> +
> >> * Add support for 4 formats of .cfi directives register
> aliases for LoongArch,
> >> for example, .cfi_offset r1,8, .cfi_offset ra,8,
> .cfi_offset $r1,8,
> >> .cfi_offset $ra,8.
> >> diff --git a/gas/doc/as.texi b/gas/doc/as.texi
> >> index afe1737f4ce..ad096fc02c8 100644
> >> --- a/gas/doc/as.texi
> >> +++ b/gas/doc/as.texi
> >> @@ -552,7 +552,7 @@ gcc(1), ld(1), and the Info entries for
> @file{binutils} and @file{ld}.
> >>
> >> @emph{Target RISC-V options:}
> >> [@b{-fpic}|@b{-fPIC}|@b{-fno-pic}]
> >> - [@b{-march}=@var{ISA}]
> >> + [@b{-march}=@var{ISA/Profiles/Profiles+ISA}]
> >> [@b{-mabi}=@var{ABI}]
> >> [@b{-mlittle-endian}|@b{-mbig-endian}]
> >> @end ifset
> >> diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
> >> index d2e47455e7c..f5f13a976e5 100644
> >> --- a/gas/doc/c-riscv.texi
> >> +++ b/gas/doc/c-riscv.texi
> >> @@ -41,9 +41,10 @@ Generate position-independent code
> >> @item -fno-pic
> >> Don't generate position-independent code (default)
> >>
> >> -@cindex @samp{-march=ISA} option, RISC-V
> >> -@item -march=ISA
> >> -Select the base isa, as specified by ISA. For example
> -march=rv32ima.
> >> +@cindex @samp{-march=ISA/Profiles/Profies+ISA} option, RISC-V
> >> +@item -march=ISA/Profiles/Profiles+ISA
> >> +Select the base isa, as specified by ISA or Profiles or
> Profies+ISA.
> >> +For example -march=rv32ima -march=RVI20U64 -march=RVI20U64+d.
> >> If this option and the architecture attributes aren't set,
> then assembler
> >> will check the default configure setting --with-arch=ISA.
> >>
> >> @@ -720,7 +721,12 @@ to be recorded in the attribute as
> @code{RV32I2P0} in which @code{2P0} stands
> >> for the default version of its base ISA. On the other hand,
> the architecture
> >> @code{RV32G} has to be presented as
> @code{RV32I2P0_M2P0_A2P0_F2P0_D2P0} in
> >> which the abbreviation @code{G} is expanded to the
> @code{IMAFD} combination
> >> -with default versions of the standard extensions.
> >> +with default versions of the standard extensions. All Profiles
> are expanded
> >> + to the mandatory extensions it includes then processing. For
> example,
> >> +@code{RVI20U32} is expanded to @code{RV32I2P0} for processing,
> which contains
> >> +the mandatory extensions @code{I} as it defined. And you can
> also combine
> >> +Profiles with ISA use +, like @code{RVI20U32_D} is expanded to the
> >> +@code{RV32I2P0_F2P0_D2P0}.
> >>
> >> @item Tag_RISCV_unaligned_access (6)
> >> Tag_RISCV_unaligned_access is 0 for files that do not allow
> any unaligned
> >> diff --git a/gas/testsuite/gas/riscv/attribute-15.d
> b/gas/testsuite/gas/riscv/attribute-15.d
> >> new file mode 100644
> >> index 00000000000..8cdf3767c85
> >> --- /dev/null
> >> +++ b/gas/testsuite/gas/riscv/attribute-15.d
> >> @@ -0,0 +1,6 @@
> >> +#as: -march=rva20u64
> >> +#readelf: -A
> >> +#source: empty.s
> >> +Attribute Section: riscv
> >> +File Attributes
> >> + Tag_RISCV_arch:
> "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zmmul1p0_za128rs1p0_zaamo1p0_zalrsc1p0"
> >> diff --git a/gas/testsuite/gas/riscv/attribute-16.d
> b/gas/testsuite/gas/riscv/attribute-16.d
> >> new file mode 100644
> >> index 00000000000..c4acb6b4a07
> >> --- /dev/null
> >> +++ b/gas/testsuite/gas/riscv/attribute-16.d
> >> @@ -0,0 +1,6 @@
> >> +#as: -march=rvi20u32_d
> >> +#readelf: -A
> >> +#source: empty.s
> >> +Attribute Section: riscv
> >> +File Attributes
> >> + Tag_RISCV_arch: "rv32i2p1_f2p2_d2p2_zicsr2p0"
> >> --
> >> 2.43.0
> >>
>
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