[PATCH] aarch64: Fix sve2p1 gating and add missing instructions
Andrew Carlotti
andrew.carlotti@arm.com
Fri Jan 17 16:18:30 GMT 2025
On Fri, Jan 17, 2025 at 12:50:27PM +0000, Andrew Carlotti wrote:
> On Fri, Jan 17, 2025 at 11:20:30AM +0000, Richard Sandiford wrote:
> > Thanks for doing this. The patch LGTM, but some suggestions:
> >
> > - It would be good if the tests for the new scalar-plus-scalar
> > instructions covered attempts to use xzr as an index register.
> > OPD_F_NO_ZR is well established, so it's probably a bit redundant,
> > but still...
>
> I forgot xzr existed when considering ways of referring to register '11111'.
I committed the following - the only change was to add xzr tests.
---
Many FEAT_SVE2p1 instructions need to be enabled by either of two
different features (one for streaming mode, and one for non-streaming
mode). This patch adds correct gating conditions for these
instructions.
There were also a few sve2p1 instructions missing altogether, so add
those as well.
The testsuite is modified to check for all alternative enablement
conditions. In many cases this is done by adding an alternative
assembler commands to existing test files. For some SME/SME2 tests,
only some of the instructions are enabled by +sve2p1, so these are
copied into a separate test. For original SVE2p1 tests, the non-SME2p1
instructions have been moved to a separate test file.
There are also new tests for the newly added instructions. These
include a couple of fixme comments relating to bad error reporting,
which should be investigated later.
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index fc8fcb07a787306800142b4268f5cb23e90ed04d..8b074ff22dd6870fb1cc7d796015832860c37293 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -10786,6 +10786,11 @@ static const struct aarch64_virtual_dependency_table aarch64_dependencies[] = {
{AARCH64_FEATURE (SSVE_FP8DOT2), AARCH64_FEATURE (FP8DOT2_SVE)},
{AARCH64_FEATURE (SME_F16F16), AARCH64_FEATURE (SME_F16F16_F8F16)},
{AARCH64_FEATURE (SME_F8F16), AARCH64_FEATURE (SME_F16F16_F8F16)},
+ {AARCH64_FEATURE (SVE2p1), AARCH64_FEATURES (3, SVE2p1_SME, SVE2p1_SME2,
+ SVE2p1_SME2p1)},
+ {AARCH64_FEATURE (SME), AARCH64_FEATURE (SVE2p1_SME)},
+ {AARCH64_FEATURE (SME2), AARCH64_FEATURE (SVE2p1_SME2)},
+ {AARCH64_FEATURE (SME2p1), AARCH64_FEATURE (SVE2p1_SME2p1)},
};
static aarch64_feature_set
diff --git a/gas/testsuite/gas/aarch64/sme-9.d b/gas/testsuite/gas/aarch64/sme-9.d
index 69b27020d01be8131ce9e9a2c1c1bd728dbb0115..ffc61940a4e590d09461203fd7214b0c1a7f7b85 100644
--- a/gas/testsuite/gas/aarch64/sme-9.d
+++ b/gas/testsuite/gas/aarch64/sme-9.d
@@ -1,5 +1,6 @@
#name: SVE2 instructions added to support SME
#as: -march=armv8-a+sme
+#as: -march=armv8-a+sve2p1
#objdump: -dr
.*: file format .*
diff --git a/gas/testsuite/gas/aarch64/sme2-2-sve2p1.d b/gas/testsuite/gas/aarch64/sme2-2-sve2p1.d
new file mode 100644
index 0000000000000000000000000000000000000000..a406a8518e20052785fcfb2e547c749ee2f47dce
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-2-sve2p1.d
@@ -0,0 +1,169 @@
+#as: -march=armv8-a+sve2p1
+#objdump: -dr
+
+[^:]+: file format .*
+
+
+[^:]+:
+
+[^:]+:
+[^:]+: a0400000 ld1b {z0\.b-z1\.b}, pn8/z, \[x0\]
+[^:]+: a0400000 ld1b {z0\.b-z1\.b}, pn8/z, \[x0\]
+[^:]+: a0400000 ld1b {z0\.b-z1\.b}, pn8/z, \[x0\]
+[^:]+: a040001e ld1b {z30\.b-z31\.b}, pn8/z, \[x0\]
+[^:]+: a0401c00 ld1b {z0\.b-z1\.b}, pn15/z, \[x0\]
+[^:]+: a04003c0 ld1b {z0\.b-z1\.b}, pn8/z, \[x30\]
+[^:]+: a04003e0 ld1b {z0\.b-z1\.b}, pn8/z, \[sp\]
+[^:]+: a0480000 ld1b {z0\.b-z1\.b}, pn8/z, \[x0, #-16, mul vl\]
+[^:]+: a0470000 ld1b {z0\.b-z1\.b}, pn8/z, \[x0, #14, mul vl\]
+[^:]+: a04b156c ld1b {z12\.b-z13\.b}, pn13/z, \[x11, #-10, mul vl\]
+[^:]+: a0408000 ld1b {z0\.b-z3\.b}, pn8/z, \[x0\]
+[^:]+: a0408000 ld1b {z0\.b-z3\.b}, pn8/z, \[x0\]
+[^:]+: a0408000 ld1b {z0\.b-z3\.b}, pn8/z, \[x0\]
+[^:]+: a040801c ld1b {z28\.b-z31\.b}, pn8/z, \[x0\]
+[^:]+: a0409c00 ld1b {z0\.b-z3\.b}, pn15/z, \[x0\]
+[^:]+: a04083c0 ld1b {z0\.b-z3\.b}, pn8/z, \[x30\]
+[^:]+: a04083e0 ld1b {z0\.b-z3\.b}, pn8/z, \[sp\]
+[^:]+: a0488000 ld1b {z0\.b-z3\.b}, pn8/z, \[x0, #-32, mul vl\]
+[^:]+: a0478000 ld1b {z0\.b-z3\.b}, pn8/z, \[x0, #28, mul vl\]
+[^:]+: a0458e28 ld1b {z8\.b-z11\.b}, pn11/z, \[x17, #20, mul vl\]
+[^:]+: a0010000 ld1b {z0\.b-z1\.b}, pn8/z, \[x0, x1\]
+[^:]+: a0010000 ld1b {z0\.b-z1\.b}, pn8/z, \[x0, x1\]
+[^:]+: a0010000 ld1b {z0\.b-z1\.b}, pn8/z, \[x0, x1\]
+[^:]+: a001001e ld1b {z30\.b-z31\.b}, pn8/z, \[x0, x1\]
+[^:]+: a0011c00 ld1b {z0\.b-z1\.b}, pn15/z, \[x0, x1\]
+[^:]+: a00103c0 ld1b {z0\.b-z1\.b}, pn8/z, \[x30, x1\]
+[^:]+: a00103e0 ld1b {z0\.b-z1\.b}, pn8/z, \[sp, x1\]
+[^:]+: a01e0000 ld1b {z0\.b-z1\.b}, pn8/z, \[x0, x30\]
+[^:]+: a01f0000 ld1b {z0\.b-z1\.b}, pn8/z, \[x0, xzr\]
+[^:]+: a003074e ld1b {z14\.b-z15\.b}, pn9/z, \[x26, x3\]
+[^:]+: a0018000 ld1b {z0\.b-z3\.b}, pn8/z, \[x0, x1\]
+[^:]+: a0018000 ld1b {z0\.b-z3\.b}, pn8/z, \[x0, x1\]
+[^:]+: a0018000 ld1b {z0\.b-z3\.b}, pn8/z, \[x0, x1\]
+[^:]+: a001801c ld1b {z28\.b-z31\.b}, pn8/z, \[x0, x1\]
+[^:]+: a0019c00 ld1b {z0\.b-z3\.b}, pn15/z, \[x0, x1\]
+[^:]+: a00183c0 ld1b {z0\.b-z3\.b}, pn8/z, \[x30, x1\]
+[^:]+: a00183e0 ld1b {z0\.b-z3\.b}, pn8/z, \[sp, x1\]
+[^:]+: a01e8000 ld1b {z0\.b-z3\.b}, pn8/z, \[x0, x30\]
+[^:]+: a01f8000 ld1b {z0\.b-z3\.b}, pn8/z, \[x0, xzr\]
+[^:]+: a0018f68 ld1b {z8\.b-z11\.b}, pn11/z, \[x27, x1\]
+[^:]+: a0400001 ldnt1b {z0\.b-z1\.b}, pn8/z, \[x0\]
+[^:]+: a0400001 ldnt1b {z0\.b-z1\.b}, pn8/z, \[x0\]
+[^:]+: a0400001 ldnt1b {z0\.b-z1\.b}, pn8/z, \[x0\]
+[^:]+: a040001f ldnt1b {z30\.b-z31\.b}, pn8/z, \[x0\]
+[^:]+: a0401c01 ldnt1b {z0\.b-z1\.b}, pn15/z, \[x0\]
+[^:]+: a04003c1 ldnt1b {z0\.b-z1\.b}, pn8/z, \[x30\]
+[^:]+: a04003e1 ldnt1b {z0\.b-z1\.b}, pn8/z, \[sp\]
+[^:]+: a0480001 ldnt1b {z0\.b-z1\.b}, pn8/z, \[x0, #-16, mul vl\]
+[^:]+: a0470001 ldnt1b {z0\.b-z1\.b}, pn8/z, \[x0, #14, mul vl\]
+[^:]+: a04b156d ldnt1b {z12\.b-z13\.b}, pn13/z, \[x11, #-10, mul vl\]
+[^:]+: a0408001 ldnt1b {z0\.b-z3\.b}, pn8/z, \[x0\]
+[^:]+: a0408001 ldnt1b {z0\.b-z3\.b}, pn8/z, \[x0\]
+[^:]+: a0408001 ldnt1b {z0\.b-z3\.b}, pn8/z, \[x0\]
+[^:]+: a040801d ldnt1b {z28\.b-z31\.b}, pn8/z, \[x0\]
+[^:]+: a0409c01 ldnt1b {z0\.b-z3\.b}, pn15/z, \[x0\]
+[^:]+: a04083c1 ldnt1b {z0\.b-z3\.b}, pn8/z, \[x30\]
+[^:]+: a04083e1 ldnt1b {z0\.b-z3\.b}, pn8/z, \[sp\]
+[^:]+: a0488001 ldnt1b {z0\.b-z3\.b}, pn8/z, \[x0, #-32, mul vl\]
+[^:]+: a0478001 ldnt1b {z0\.b-z3\.b}, pn8/z, \[x0, #28, mul vl\]
+[^:]+: a0458e29 ldnt1b {z8\.b-z11\.b}, pn11/z, \[x17, #20, mul vl\]
+[^:]+: a0010001 ldnt1b {z0\.b-z1\.b}, pn8/z, \[x0, x1\]
+[^:]+: a0010001 ldnt1b {z0\.b-z1\.b}, pn8/z, \[x0, x1\]
+[^:]+: a0010001 ldnt1b {z0\.b-z1\.b}, pn8/z, \[x0, x1\]
+[^:]+: a001001f ldnt1b {z30\.b-z31\.b}, pn8/z, \[x0, x1\]
+[^:]+: a0011c01 ldnt1b {z0\.b-z1\.b}, pn15/z, \[x0, x1\]
+[^:]+: a00103c1 ldnt1b {z0\.b-z1\.b}, pn8/z, \[x30, x1\]
+[^:]+: a00103e1 ldnt1b {z0\.b-z1\.b}, pn8/z, \[sp, x1\]
+[^:]+: a01e0001 ldnt1b {z0\.b-z1\.b}, pn8/z, \[x0, x30\]
+[^:]+: a01f0001 ldnt1b {z0\.b-z1\.b}, pn8/z, \[x0, xzr\]
+[^:]+: a003074f ldnt1b {z14\.b-z15\.b}, pn9/z, \[x26, x3\]
+[^:]+: a0018001 ldnt1b {z0\.b-z3\.b}, pn8/z, \[x0, x1\]
+[^:]+: a0018001 ldnt1b {z0\.b-z3\.b}, pn8/z, \[x0, x1\]
+[^:]+: a0018001 ldnt1b {z0\.b-z3\.b}, pn8/z, \[x0, x1\]
+[^:]+: a001801d ldnt1b {z28\.b-z31\.b}, pn8/z, \[x0, x1\]
+[^:]+: a0019c01 ldnt1b {z0\.b-z3\.b}, pn15/z, \[x0, x1\]
+[^:]+: a00183c1 ldnt1b {z0\.b-z3\.b}, pn8/z, \[x30, x1\]
+[^:]+: a00183e1 ldnt1b {z0\.b-z3\.b}, pn8/z, \[sp, x1\]
+[^:]+: a01e8001 ldnt1b {z0\.b-z3\.b}, pn8/z, \[x0, x30\]
+[^:]+: a01f8001 ldnt1b {z0\.b-z3\.b}, pn8/z, \[x0, xzr\]
+[^:]+: a0018f69 ldnt1b {z8\.b-z11\.b}, pn11/z, \[x27, x1\]
+[^:]+: a0600000 st1b {z0\.b-z1\.b}, pn8, \[x0\]
+[^:]+: a0600000 st1b {z0\.b-z1\.b}, pn8, \[x0\]
+[^:]+: a0600000 st1b {z0\.b-z1\.b}, pn8, \[x0\]
+[^:]+: a060001e st1b {z30\.b-z31\.b}, pn8, \[x0\]
+[^:]+: a0601c00 st1b {z0\.b-z1\.b}, pn15, \[x0\]
+[^:]+: a06003c0 st1b {z0\.b-z1\.b}, pn8, \[x30\]
+[^:]+: a06003e0 st1b {z0\.b-z1\.b}, pn8, \[sp\]
+[^:]+: a0680000 st1b {z0\.b-z1\.b}, pn8, \[x0, #-16, mul vl\]
+[^:]+: a0670000 st1b {z0\.b-z1\.b}, pn8, \[x0, #14, mul vl\]
+[^:]+: a06b156c st1b {z12\.b-z13\.b}, pn13, \[x11, #-10, mul vl\]
+[^:]+: a0608000 st1b {z0\.b-z3\.b}, pn8, \[x0\]
+[^:]+: a0608000 st1b {z0\.b-z3\.b}, pn8, \[x0\]
+[^:]+: a0608000 st1b {z0\.b-z3\.b}, pn8, \[x0\]
+[^:]+: a060801c st1b {z28\.b-z31\.b}, pn8, \[x0\]
+[^:]+: a0609c00 st1b {z0\.b-z3\.b}, pn15, \[x0\]
+[^:]+: a06083c0 st1b {z0\.b-z3\.b}, pn8, \[x30\]
+[^:]+: a06083e0 st1b {z0\.b-z3\.b}, pn8, \[sp\]
+[^:]+: a0688000 st1b {z0\.b-z3\.b}, pn8, \[x0, #-32, mul vl\]
+[^:]+: a0678000 st1b {z0\.b-z3\.b}, pn8, \[x0, #28, mul vl\]
+[^:]+: a0658e28 st1b {z8\.b-z11\.b}, pn11, \[x17, #20, mul vl\]
+[^:]+: a0210000 st1b {z0\.b-z1\.b}, pn8, \[x0, x1\]
+[^:]+: a0210000 st1b {z0\.b-z1\.b}, pn8, \[x0, x1\]
+[^:]+: a0210000 st1b {z0\.b-z1\.b}, pn8, \[x0, x1\]
+[^:]+: a021001e st1b {z30\.b-z31\.b}, pn8, \[x0, x1\]
+[^:]+: a0211c00 st1b {z0\.b-z1\.b}, pn15, \[x0, x1\]
+[^:]+: a02103c0 st1b {z0\.b-z1\.b}, pn8, \[x30, x1\]
+[^:]+: a02103e0 st1b {z0\.b-z1\.b}, pn8, \[sp, x1\]
+[^:]+: a03e0000 st1b {z0\.b-z1\.b}, pn8, \[x0, x30\]
+[^:]+: a03f0000 st1b {z0\.b-z1\.b}, pn8, \[x0, xzr\]
+[^:]+: a023074e st1b {z14\.b-z15\.b}, pn9, \[x26, x3\]
+[^:]+: a0218000 st1b {z0\.b-z3\.b}, pn8, \[x0, x1\]
+[^:]+: a0218000 st1b {z0\.b-z3\.b}, pn8, \[x0, x1\]
+[^:]+: a0218000 st1b {z0\.b-z3\.b}, pn8, \[x0, x1\]
+[^:]+: a021801c st1b {z28\.b-z31\.b}, pn8, \[x0, x1\]
+[^:]+: a0219c00 st1b {z0\.b-z3\.b}, pn15, \[x0, x1\]
+[^:]+: a02183c0 st1b {z0\.b-z3\.b}, pn8, \[x30, x1\]
+[^:]+: a02183e0 st1b {z0\.b-z3\.b}, pn8, \[sp, x1\]
+[^:]+: a03e8000 st1b {z0\.b-z3\.b}, pn8, \[x0, x30\]
+[^:]+: a03f8000 st1b {z0\.b-z3\.b}, pn8, \[x0, xzr\]
+[^:]+: a0218f68 st1b {z8\.b-z11\.b}, pn11, \[x27, x1\]
+[^:]+: a0600001 stnt1b {z0\.b-z1\.b}, pn8, \[x0\]
+[^:]+: a0600001 stnt1b {z0\.b-z1\.b}, pn8, \[x0\]
+[^:]+: a0600001 stnt1b {z0\.b-z1\.b}, pn8, \[x0\]
+[^:]+: a060001f stnt1b {z30\.b-z31\.b}, pn8, \[x0\]
+[^:]+: a0601c01 stnt1b {z0\.b-z1\.b}, pn15, \[x0\]
+[^:]+: a06003c1 stnt1b {z0\.b-z1\.b}, pn8, \[x30\]
+[^:]+: a06003e1 stnt1b {z0\.b-z1\.b}, pn8, \[sp\]
+[^:]+: a0680001 stnt1b {z0\.b-z1\.b}, pn8, \[x0, #-16, mul vl\]
+[^:]+: a0670001 stnt1b {z0\.b-z1\.b}, pn8, \[x0, #14, mul vl\]
+[^:]+: a06b156d stnt1b {z12\.b-z13\.b}, pn13, \[x11, #-10, mul vl\]
+[^:]+: a0608001 stnt1b {z0\.b-z3\.b}, pn8, \[x0\]
+[^:]+: a0608001 stnt1b {z0\.b-z3\.b}, pn8, \[x0\]
+[^:]+: a0608001 stnt1b {z0\.b-z3\.b}, pn8, \[x0\]
+[^:]+: a060801d stnt1b {z28\.b-z31\.b}, pn8, \[x0\]
+[^:]+: a0609c01 stnt1b {z0\.b-z3\.b}, pn15, \[x0\]
+[^:]+: a06083c1 stnt1b {z0\.b-z3\.b}, pn8, \[x30\]
+[^:]+: a06083e1 stnt1b {z0\.b-z3\.b}, pn8, \[sp\]
+[^:]+: a0688001 stnt1b {z0\.b-z3\.b}, pn8, \[x0, #-32, mul vl\]
+[^:]+: a0678001 stnt1b {z0\.b-z3\.b}, pn8, \[x0, #28, mul vl\]
+[^:]+: a0658e29 stnt1b {z8\.b-z11\.b}, pn11, \[x17, #20, mul vl\]
+[^:]+: a0210001 stnt1b {z0\.b-z1\.b}, pn8, \[x0, x1\]
+[^:]+: a0210001 stnt1b {z0\.b-z1\.b}, pn8, \[x0, x1\]
+[^:]+: a0210001 stnt1b {z0\.b-z1\.b}, pn8, \[x0, x1\]
+[^:]+: a021001f stnt1b {z30\.b-z31\.b}, pn8, \[x0, x1\]
+[^:]+: a0211c01 stnt1b {z0\.b-z1\.b}, pn15, \[x0, x1\]
+[^:]+: a02103c1 stnt1b {z0\.b-z1\.b}, pn8, \[x30, x1\]
+[^:]+: a02103e1 stnt1b {z0\.b-z1\.b}, pn8, \[sp, x1\]
+[^:]+: a03e0001 stnt1b {z0\.b-z1\.b}, pn8, \[x0, x30\]
+[^:]+: a03f0001 stnt1b {z0\.b-z1\.b}, pn8, \[x0, xzr\]
+[^:]+: a023074f stnt1b {z14\.b-z15\.b}, pn9, \[x26, x3\]
+[^:]+: a0218001 stnt1b {z0\.b-z3\.b}, pn8, \[x0, x1\]
+[^:]+: a0218001 stnt1b {z0\.b-z3\.b}, pn8, \[x0, x1\]
+[^:]+: a0218001 stnt1b {z0\.b-z3\.b}, pn8, \[x0, x1\]
+[^:]+: a021801d stnt1b {z28\.b-z31\.b}, pn8, \[x0, x1\]
+[^:]+: a0219c01 stnt1b {z0\.b-z3\.b}, pn15, \[x0, x1\]
+[^:]+: a02183c1 stnt1b {z0\.b-z3\.b}, pn8, \[x30, x1\]
+[^:]+: a02183e1 stnt1b {z0\.b-z3\.b}, pn8, \[sp, x1\]
+[^:]+: a03e8001 stnt1b {z0\.b-z3\.b}, pn8, \[x0, x30\]
+[^:]+: a03f8001 stnt1b {z0\.b-z3\.b}, pn8, \[x0, xzr\]
+[^:]+: a0218f69 stnt1b {z8\.b-z11\.b}, pn11, \[x27, x1\]
diff --git a/gas/testsuite/gas/aarch64/sme2-2-sve2p1.s b/gas/testsuite/gas/aarch64/sme2-2-sve2p1.s
new file mode 100644
index 0000000000000000000000000000000000000000..8c90a67bf7c2192ffa9e88619628155e184fb741
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-2-sve2p1.s
@@ -0,0 +1,175 @@
+ ld1b { z0.b - z1.b }, pn8/z, [x0]
+ ld1b { z0.b - z1.b }, pn8/z, [x0, #0, mul vl]
+ LD1B { Z0.B - Z1.B }, PN8/Z, [X0]
+ ld1b { z30.b - z31.b }, pn8/z, [x0]
+ ld1b { z0.b - z1.b }, pn15/z, [x0]
+ ld1b { z0.b - z1.b }, pn8/z, [x30]
+ ld1b { z0.b - z1.b }, pn8/z, [sp]
+ ld1b { z0.b - z1.b }, pn8/z, [x0, #-16, mul vl]
+ ld1b { z0.b - z1.b }, pn8/z, [x0, #14, mul vl]
+ ld1b { z12.b - z13.b }, pn13/z, [x11, #-10, mul vl]
+
+ ld1b { z0.b - z3.b }, pn8/z, [x0]
+ ld1b { z0.b - z3.b }, pn8/z, [x0, #0, mul vl]
+ LD1B { Z0.B - Z3.B }, PN8/Z, [X0]
+ ld1b { z28.b - z31.b }, pn8/z, [x0]
+ ld1b { z0.b - z3.b }, pn15/z, [x0]
+ ld1b { z0.b - z3.b }, pn8/z, [x30]
+ ld1b { z0.b - z3.b }, pn8/z, [sp]
+ ld1b { z0.b - z3.b }, pn8/z, [x0, #-32, mul vl]
+ ld1b { z0.b - z3.b }, pn8/z, [x0, #28, mul vl]
+ ld1b { z8.b - z11.b }, pn11/z, [x17, #20, mul vl]
+
+ ld1b { z0.b - z1.b }, pn8/z, [x0, x1]
+ ld1b { z0.b - z1.b }, pn8/z, [x0, x1, lsl #0]
+ LD1B { Z0.B - Z1.B }, PN8/Z, [X0, X1]
+ ld1b { z30.b - z31.b }, pn8/z, [x0, x1]
+ ld1b { z0.b - z1.b }, pn15/z, [x0, x1]
+ ld1b { z0.b - z1.b }, pn8/z, [x30, x1]
+ ld1b { z0.b - z1.b }, pn8/z, [sp, x1]
+ ld1b { z0.b - z1.b }, pn8/z, [x0, x30]
+ ld1b { z0.b - z1.b }, pn8/z, [x0, xzr]
+ ld1b { z14.b - z15.b }, pn9/z, [x26, x3]
+
+ ld1b { z0.b - z3.b }, pn8/z, [x0, x1]
+ ld1b { z0.b - z3.b }, pn8/z, [x0, x1, lsl #0]
+ LD1B { Z0.B - Z3.B }, PN8/Z, [X0, X1]
+ ld1b { z28.b - z31.b }, pn8/z, [x0, x1]
+ ld1b { z0.b - z3.b }, pn15/z, [x0, x1]
+ ld1b { z0.b - z3.b }, pn8/z, [x30, x1]
+ ld1b { z0.b - z3.b }, pn8/z, [sp, x1]
+ ld1b { z0.b - z3.b }, pn8/z, [x0, x30]
+ ld1b { z0.b - z3.b }, pn8/z, [x0, xzr]
+ ld1b { z8.b - z11.b }, pn11/z, [x27, x1]
+
+ ldnt1b { z0.b - z1.b }, pn8/z, [x0]
+ ldnt1b { z0.b - z1.b }, pn8/z, [x0, #0, mul vl]
+ LDNT1B { Z0.B - Z1.B }, PN8/Z, [X0]
+ ldnt1b { z30.b - z31.b }, pn8/z, [x0]
+ ldnt1b { z0.b - z1.b }, pn15/z, [x0]
+ ldnt1b { z0.b - z1.b }, pn8/z, [x30]
+ ldnt1b { z0.b - z1.b }, pn8/z, [sp]
+ ldnt1b { z0.b - z1.b }, pn8/z, [x0, #-16, mul vl]
+ ldnt1b { z0.b - z1.b }, pn8/z, [x0, #14, mul vl]
+ ldnt1b { z12.b - z13.b }, pn13/z, [x11, #-10, mul vl]
+
+ ldnt1b { z0.b - z3.b }, pn8/z, [x0]
+ ldnt1b { z0.b - z3.b }, pn8/z, [x0, #0, mul vl]
+ LDNT1B { Z0.B - Z3.B }, PN8/Z, [X0]
+ ldnt1b { z28.b - z31.b }, pn8/z, [x0]
+ ldnt1b { z0.b - z3.b }, pn15/z, [x0]
+ ldnt1b { z0.b - z3.b }, pn8/z, [x30]
+ ldnt1b { z0.b - z3.b }, pn8/z, [sp]
+ ldnt1b { z0.b - z3.b }, pn8/z, [x0, #-32, mul vl]
+ ldnt1b { z0.b - z3.b }, pn8/z, [x0, #28, mul vl]
+ ldnt1b { z8.b - z11.b }, pn11/z, [x17, #20, mul vl]
+
+ ldnt1b { z0.b - z1.b }, pn8/z, [x0, x1]
+ ldnt1b { z0.b - z1.b }, pn8/z, [x0, x1, lsl #0]
+ LDNT1B { Z0.B - Z1.B }, PN8/Z, [X0, X1]
+ ldnt1b { z30.b - z31.b }, pn8/z, [x0, x1]
+ ldnt1b { z0.b - z1.b }, pn15/z, [x0, x1]
+ ldnt1b { z0.b - z1.b }, pn8/z, [x30, x1]
+ ldnt1b { z0.b - z1.b }, pn8/z, [sp, x1]
+ ldnt1b { z0.b - z1.b }, pn8/z, [x0, x30]
+ ldnt1b { z0.b - z1.b }, pn8/z, [x0, xzr]
+ ldnt1b { z14.b - z15.b }, pn9/z, [x26, x3]
+
+ ldnt1b { z0.b - z3.b }, pn8/z, [x0, x1]
+ ldnt1b { z0.b - z3.b }, pn8/z, [x0, x1, lsl #0]
+ LDNT1B { Z0.B - Z3.B }, PN8/Z, [X0, X1]
+ ldnt1b { z28.b - z31.b }, pn8/z, [x0, x1]
+ ldnt1b { z0.b - z3.b }, pn15/z, [x0, x1]
+ ldnt1b { z0.b - z3.b }, pn8/z, [x30, x1]
+ ldnt1b { z0.b - z3.b }, pn8/z, [sp, x1]
+ ldnt1b { z0.b - z3.b }, pn8/z, [x0, x30]
+ ldnt1b { z0.b - z3.b }, pn8/z, [x0, xzr]
+ ldnt1b { z8.b - z11.b }, pn11/z, [x27, x1]
+
+ st1b { z0.b - z1.b }, pn8, [x0]
+ st1b { z0.b - z1.b }, pn8, [x0, #0, mul vl]
+ ST1B { Z0.B - Z1.B }, PN8, [X0]
+ st1b { z30.b - z31.b }, pn8, [x0]
+ st1b { z0.b - z1.b }, pn15, [x0]
+ st1b { z0.b - z1.b }, pn8, [x30]
+ st1b { z0.b - z1.b }, pn8, [sp]
+ st1b { z0.b - z1.b }, pn8, [x0, #-16, mul vl]
+ st1b { z0.b - z1.b }, pn8, [x0, #14, mul vl]
+ st1b { z12.b - z13.b }, pn13, [x11, #-10, mul vl]
+
+ st1b { z0.b - z3.b }, pn8, [x0]
+ st1b { z0.b - z3.b }, pn8, [x0, #0, mul vl]
+ ST1B { Z0.B - Z3.B }, PN8, [X0]
+ st1b { z28.b - z31.b }, pn8, [x0]
+ st1b { z0.b - z3.b }, pn15, [x0]
+ st1b { z0.b - z3.b }, pn8, [x30]
+ st1b { z0.b - z3.b }, pn8, [sp]
+ st1b { z0.b - z3.b }, pn8, [x0, #-32, mul vl]
+ st1b { z0.b - z3.b }, pn8, [x0, #28, mul vl]
+ st1b { z8.b - z11.b }, pn11, [x17, #20, mul vl]
+
+ st1b { z0.b - z1.b }, pn8, [x0, x1]
+ st1b { z0.b - z1.b }, pn8, [x0, x1, lsl #0]
+ ST1B { Z0.B - Z1.B }, PN8, [X0, X1]
+ st1b { z30.b - z31.b }, pn8, [x0, x1]
+ st1b { z0.b - z1.b }, pn15, [x0, x1]
+ st1b { z0.b - z1.b }, pn8, [x30, x1]
+ st1b { z0.b - z1.b }, pn8, [sp, x1]
+ st1b { z0.b - z1.b }, pn8, [x0, x30]
+ st1b { z0.b - z1.b }, pn8, [x0, xzr]
+ st1b { z14.b - z15.b }, pn9, [x26, x3]
+
+ st1b { z0.b - z3.b }, pn8, [x0, x1]
+ st1b { z0.b - z3.b }, pn8, [x0, x1, lsl #0]
+ ST1B { Z0.B - Z3.B }, PN8, [X0, X1]
+ st1b { z28.b - z31.b }, pn8, [x0, x1]
+ st1b { z0.b - z3.b }, pn15, [x0, x1]
+ st1b { z0.b - z3.b }, pn8, [x30, x1]
+ st1b { z0.b - z3.b }, pn8, [sp, x1]
+ st1b { z0.b - z3.b }, pn8, [x0, x30]
+ st1b { z0.b - z3.b }, pn8, [x0, xzr]
+ st1b { z8.b - z11.b }, pn11, [x27, x1]
+
+ stnt1b { z0.b - z1.b }, pn8, [x0]
+ stnt1b { z0.b - z1.b }, pn8, [x0, #0, mul vl]
+ STNT1B { Z0.B - Z1.B }, PN8, [X0]
+ stnt1b { z30.b - z31.b }, pn8, [x0]
+ stnt1b { z0.b - z1.b }, pn15, [x0]
+ stnt1b { z0.b - z1.b }, pn8, [x30]
+ stnt1b { z0.b - z1.b }, pn8, [sp]
+ stnt1b { z0.b - z1.b }, pn8, [x0, #-16, mul vl]
+ stnt1b { z0.b - z1.b }, pn8, [x0, #14, mul vl]
+ stnt1b { z12.b - z13.b }, pn13, [x11, #-10, mul vl]
+
+ stnt1b { z0.b - z3.b }, pn8, [x0]
+ stnt1b { z0.b - z3.b }, pn8, [x0, #0, mul vl]
+ STNT1B { Z0.B - Z3.B }, PN8, [X0]
+ stnt1b { z28.b - z31.b }, pn8, [x0]
+ stnt1b { z0.b - z3.b }, pn15, [x0]
+ stnt1b { z0.b - z3.b }, pn8, [x30]
+ stnt1b { z0.b - z3.b }, pn8, [sp]
+ stnt1b { z0.b - z3.b }, pn8, [x0, #-32, mul vl]
+ stnt1b { z0.b - z3.b }, pn8, [x0, #28, mul vl]
+ stnt1b { z8.b - z11.b }, pn11, [x17, #20, mul vl]
+
+ stnt1b { z0.b - z1.b }, pn8, [x0, x1]
+ stnt1b { z0.b - z1.b }, pn8, [x0, x1, lsl #0]
+ STNT1B { Z0.B - Z1.B }, PN8, [X0, X1]
+ stnt1b { z30.b - z31.b }, pn8, [x0, x1]
+ stnt1b { z0.b - z1.b }, pn15, [x0, x1]
+ stnt1b { z0.b - z1.b }, pn8, [x30, x1]
+ stnt1b { z0.b - z1.b }, pn8, [sp, x1]
+ stnt1b { z0.b - z1.b }, pn8, [x0, x30]
+ stnt1b { z0.b - z1.b }, pn8, [x0, xzr]
+ stnt1b { z14.b - z15.b }, pn9, [x26, x3]
+
+ stnt1b { z0.b - z3.b }, pn8, [x0, x1]
+ stnt1b { z0.b - z3.b }, pn8, [x0, x1, lsl #0]
+ STNT1B { Z0.B - Z3.B }, PN8, [X0, X1]
+ stnt1b { z28.b - z31.b }, pn8, [x0, x1]
+ stnt1b { z0.b - z3.b }, pn15, [x0, x1]
+ stnt1b { z0.b - z3.b }, pn8, [x30, x1]
+ stnt1b { z0.b - z3.b }, pn8, [sp, x1]
+ stnt1b { z0.b - z3.b }, pn8, [x0, x30]
+ stnt1b { z0.b - z3.b }, pn8, [x0, xzr]
+ stnt1b { z8.b - z11.b }, pn11, [x27, x1]
diff --git a/gas/testsuite/gas/aarch64/sme2-3-sve2p1.d b/gas/testsuite/gas/aarch64/sme2-3-sve2p1.d
new file mode 100644
index 0000000000000000000000000000000000000000..4e39bddcfbc58af28cd75a3f0d23f33259815069
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-3-sve2p1.d
@@ -0,0 +1,169 @@
+#as: -march=armv8-a+sve2p1
+#objdump: -dr
+
+[^:]+: file format .*
+
+
+[^:]+:
+
+[^:]+:
+[^:]+: a0406000 ld1d {z0\.d-z1\.d}, pn8/z, \[x0\]
+[^:]+: a0406000 ld1d {z0\.d-z1\.d}, pn8/z, \[x0\]
+[^:]+: a0406000 ld1d {z0\.d-z1\.d}, pn8/z, \[x0\]
+[^:]+: a040601e ld1d {z30\.d-z31\.d}, pn8/z, \[x0\]
+[^:]+: a0407c00 ld1d {z0\.d-z1\.d}, pn15/z, \[x0\]
+[^:]+: a04063c0 ld1d {z0\.d-z1\.d}, pn8/z, \[x30\]
+[^:]+: a04063e0 ld1d {z0\.d-z1\.d}, pn8/z, \[sp\]
+[^:]+: a0486000 ld1d {z0\.d-z1\.d}, pn8/z, \[x0, #-16, mul vl\]
+[^:]+: a0476000 ld1d {z0\.d-z1\.d}, pn8/z, \[x0, #14, mul vl\]
+[^:]+: a04b756c ld1d {z12\.d-z13\.d}, pn13/z, \[x11, #-10, mul vl\]
+[^:]+: a040e000 ld1d {z0\.d-z3\.d}, pn8/z, \[x0\]
+[^:]+: a040e000 ld1d {z0\.d-z3\.d}, pn8/z, \[x0\]
+[^:]+: a040e000 ld1d {z0\.d-z3\.d}, pn8/z, \[x0\]
+[^:]+: a040e01c ld1d {z28\.d-z31\.d}, pn8/z, \[x0\]
+[^:]+: a040fc00 ld1d {z0\.d-z3\.d}, pn15/z, \[x0\]
+[^:]+: a040e3c0 ld1d {z0\.d-z3\.d}, pn8/z, \[x30\]
+[^:]+: a040e3e0 ld1d {z0\.d-z3\.d}, pn8/z, \[sp\]
+[^:]+: a048e000 ld1d {z0\.d-z3\.d}, pn8/z, \[x0, #-32, mul vl\]
+[^:]+: a047e000 ld1d {z0\.d-z3\.d}, pn8/z, \[x0, #28, mul vl\]
+[^:]+: a045ee28 ld1d {z8\.d-z11\.d}, pn11/z, \[x17, #20, mul vl\]
+[^:]+: a0016000 ld1d {z0\.d-z1\.d}, pn8/z, \[x0, x1, lsl #3\]
+[^:]+: a0016000 ld1d {z0\.d-z1\.d}, pn8/z, \[x0, x1, lsl #3\]
+[^:]+: a0016000 ld1d {z0\.d-z1\.d}, pn8/z, \[x0, x1, lsl #3\]
+[^:]+: a001601e ld1d {z30\.d-z31\.d}, pn8/z, \[x0, x1, lsl #3\]
+[^:]+: a0017c00 ld1d {z0\.d-z1\.d}, pn15/z, \[x0, x1, lsl #3\]
+[^:]+: a00163c0 ld1d {z0\.d-z1\.d}, pn8/z, \[x30, x1, lsl #3\]
+[^:]+: a00163e0 ld1d {z0\.d-z1\.d}, pn8/z, \[sp, x1, lsl #3\]
+[^:]+: a01e6000 ld1d {z0\.d-z1\.d}, pn8/z, \[x0, x30, lsl #3\]
+[^:]+: a01f6000 ld1d {z0\.d-z1\.d}, pn8/z, \[x0, xzr, lsl #3\]
+[^:]+: a003674e ld1d {z14\.d-z15\.d}, pn9/z, \[x26, x3, lsl #3\]
+[^:]+: a001e000 ld1d {z0\.d-z3\.d}, pn8/z, \[x0, x1, lsl #3\]
+[^:]+: a001e000 ld1d {z0\.d-z3\.d}, pn8/z, \[x0, x1, lsl #3\]
+[^:]+: a001e000 ld1d {z0\.d-z3\.d}, pn8/z, \[x0, x1, lsl #3\]
+[^:]+: a001e01c ld1d {z28\.d-z31\.d}, pn8/z, \[x0, x1, lsl #3\]
+[^:]+: a001fc00 ld1d {z0\.d-z3\.d}, pn15/z, \[x0, x1, lsl #3\]
+[^:]+: a001e3c0 ld1d {z0\.d-z3\.d}, pn8/z, \[x30, x1, lsl #3\]
+[^:]+: a001e3e0 ld1d {z0\.d-z3\.d}, pn8/z, \[sp, x1, lsl #3\]
+[^:]+: a01ee000 ld1d {z0\.d-z3\.d}, pn8/z, \[x0, x30, lsl #3\]
+[^:]+: a01fe000 ld1d {z0\.d-z3\.d}, pn8/z, \[x0, xzr, lsl #3\]
+[^:]+: a001ef68 ld1d {z8\.d-z11\.d}, pn11/z, \[x27, x1, lsl #3\]
+[^:]+: a0406001 ldnt1d {z0\.d-z1\.d}, pn8/z, \[x0\]
+[^:]+: a0406001 ldnt1d {z0\.d-z1\.d}, pn8/z, \[x0\]
+[^:]+: a0406001 ldnt1d {z0\.d-z1\.d}, pn8/z, \[x0\]
+[^:]+: a040601f ldnt1d {z30\.d-z31\.d}, pn8/z, \[x0\]
+[^:]+: a0407c01 ldnt1d {z0\.d-z1\.d}, pn15/z, \[x0\]
+[^:]+: a04063c1 ldnt1d {z0\.d-z1\.d}, pn8/z, \[x30\]
+[^:]+: a04063e1 ldnt1d {z0\.d-z1\.d}, pn8/z, \[sp\]
+[^:]+: a0486001 ldnt1d {z0\.d-z1\.d}, pn8/z, \[x0, #-16, mul vl\]
+[^:]+: a0476001 ldnt1d {z0\.d-z1\.d}, pn8/z, \[x0, #14, mul vl\]
+[^:]+: a04b756d ldnt1d {z12\.d-z13\.d}, pn13/z, \[x11, #-10, mul vl\]
+[^:]+: a040e001 ldnt1d {z0\.d-z3\.d}, pn8/z, \[x0\]
+[^:]+: a040e001 ldnt1d {z0\.d-z3\.d}, pn8/z, \[x0\]
+[^:]+: a040e001 ldnt1d {z0\.d-z3\.d}, pn8/z, \[x0\]
+[^:]+: a040e01d ldnt1d {z28\.d-z31\.d}, pn8/z, \[x0\]
+[^:]+: a040fc01 ldnt1d {z0\.d-z3\.d}, pn15/z, \[x0\]
+[^:]+: a040e3c1 ldnt1d {z0\.d-z3\.d}, pn8/z, \[x30\]
+[^:]+: a040e3e1 ldnt1d {z0\.d-z3\.d}, pn8/z, \[sp\]
+[^:]+: a048e001 ldnt1d {z0\.d-z3\.d}, pn8/z, \[x0, #-32, mul vl\]
+[^:]+: a047e001 ldnt1d {z0\.d-z3\.d}, pn8/z, \[x0, #28, mul vl\]
+[^:]+: a045ee29 ldnt1d {z8\.d-z11\.d}, pn11/z, \[x17, #20, mul vl\]
+[^:]+: a0016001 ldnt1d {z0\.d-z1\.d}, pn8/z, \[x0, x1, lsl #3\]
+[^:]+: a0016001 ldnt1d {z0\.d-z1\.d}, pn8/z, \[x0, x1, lsl #3\]
+[^:]+: a0016001 ldnt1d {z0\.d-z1\.d}, pn8/z, \[x0, x1, lsl #3\]
+[^:]+: a001601f ldnt1d {z30\.d-z31\.d}, pn8/z, \[x0, x1, lsl #3\]
+[^:]+: a0017c01 ldnt1d {z0\.d-z1\.d}, pn15/z, \[x0, x1, lsl #3\]
+[^:]+: a00163c1 ldnt1d {z0\.d-z1\.d}, pn8/z, \[x30, x1, lsl #3\]
+[^:]+: a00163e1 ldnt1d {z0\.d-z1\.d}, pn8/z, \[sp, x1, lsl #3\]
+[^:]+: a01e6001 ldnt1d {z0\.d-z1\.d}, pn8/z, \[x0, x30, lsl #3\]
+[^:]+: a01f6001 ldnt1d {z0\.d-z1\.d}, pn8/z, \[x0, xzr, lsl #3\]
+[^:]+: a003674f ldnt1d {z14\.d-z15\.d}, pn9/z, \[x26, x3, lsl #3\]
+[^:]+: a001e001 ldnt1d {z0\.d-z3\.d}, pn8/z, \[x0, x1, lsl #3\]
+[^:]+: a001e001 ldnt1d {z0\.d-z3\.d}, pn8/z, \[x0, x1, lsl #3\]
+[^:]+: a001e001 ldnt1d {z0\.d-z3\.d}, pn8/z, \[x0, x1, lsl #3\]
+[^:]+: a001e01d ldnt1d {z28\.d-z31\.d}, pn8/z, \[x0, x1, lsl #3\]
+[^:]+: a001fc01 ldnt1d {z0\.d-z3\.d}, pn15/z, \[x0, x1, lsl #3\]
+[^:]+: a001e3c1 ldnt1d {z0\.d-z3\.d}, pn8/z, \[x30, x1, lsl #3\]
+[^:]+: a001e3e1 ldnt1d {z0\.d-z3\.d}, pn8/z, \[sp, x1, lsl #3\]
+[^:]+: a01ee001 ldnt1d {z0\.d-z3\.d}, pn8/z, \[x0, x30, lsl #3\]
+[^:]+: a01fe001 ldnt1d {z0\.d-z3\.d}, pn8/z, \[x0, xzr, lsl #3\]
+[^:]+: a001ef69 ldnt1d {z8\.d-z11\.d}, pn11/z, \[x27, x1, lsl #3\]
+[^:]+: a0606000 st1d {z0\.d-z1\.d}, pn8, \[x0\]
+[^:]+: a0606000 st1d {z0\.d-z1\.d}, pn8, \[x0\]
+[^:]+: a0606000 st1d {z0\.d-z1\.d}, pn8, \[x0\]
+[^:]+: a060601e st1d {z30\.d-z31\.d}, pn8, \[x0\]
+[^:]+: a0607c00 st1d {z0\.d-z1\.d}, pn15, \[x0\]
+[^:]+: a06063c0 st1d {z0\.d-z1\.d}, pn8, \[x30\]
+[^:]+: a06063e0 st1d {z0\.d-z1\.d}, pn8, \[sp\]
+[^:]+: a0686000 st1d {z0\.d-z1\.d}, pn8, \[x0, #-16, mul vl\]
+[^:]+: a0676000 st1d {z0\.d-z1\.d}, pn8, \[x0, #14, mul vl\]
+[^:]+: a06b756c st1d {z12\.d-z13\.d}, pn13, \[x11, #-10, mul vl\]
+[^:]+: a060e000 st1d {z0\.d-z3\.d}, pn8, \[x0\]
+[^:]+: a060e000 st1d {z0\.d-z3\.d}, pn8, \[x0\]
+[^:]+: a060e000 st1d {z0\.d-z3\.d}, pn8, \[x0\]
+[^:]+: a060e01c st1d {z28\.d-z31\.d}, pn8, \[x0\]
+[^:]+: a060fc00 st1d {z0\.d-z3\.d}, pn15, \[x0\]
+[^:]+: a060e3c0 st1d {z0\.d-z3\.d}, pn8, \[x30\]
+[^:]+: a060e3e0 st1d {z0\.d-z3\.d}, pn8, \[sp\]
+[^:]+: a068e000 st1d {z0\.d-z3\.d}, pn8, \[x0, #-32, mul vl\]
+[^:]+: a067e000 st1d {z0\.d-z3\.d}, pn8, \[x0, #28, mul vl\]
+[^:]+: a065ee28 st1d {z8\.d-z11\.d}, pn11, \[x17, #20, mul vl\]
+[^:]+: a0216000 st1d {z0\.d-z1\.d}, pn8, \[x0, x1, lsl #3\]
+[^:]+: a0216000 st1d {z0\.d-z1\.d}, pn8, \[x0, x1, lsl #3\]
+[^:]+: a0216000 st1d {z0\.d-z1\.d}, pn8, \[x0, x1, lsl #3\]
+[^:]+: a021601e st1d {z30\.d-z31\.d}, pn8, \[x0, x1, lsl #3\]
+[^:]+: a0217c00 st1d {z0\.d-z1\.d}, pn15, \[x0, x1, lsl #3\]
+[^:]+: a02163c0 st1d {z0\.d-z1\.d}, pn8, \[x30, x1, lsl #3\]
+[^:]+: a02163e0 st1d {z0\.d-z1\.d}, pn8, \[sp, x1, lsl #3\]
+[^:]+: a03e6000 st1d {z0\.d-z1\.d}, pn8, \[x0, x30, lsl #3\]
+[^:]+: a03f6000 st1d {z0\.d-z1\.d}, pn8, \[x0, xzr, lsl #3\]
+[^:]+: a023674e st1d {z14\.d-z15\.d}, pn9, \[x26, x3, lsl #3\]
+[^:]+: a021e000 st1d {z0\.d-z3\.d}, pn8, \[x0, x1, lsl #3\]
+[^:]+: a021e000 st1d {z0\.d-z3\.d}, pn8, \[x0, x1, lsl #3\]
+[^:]+: a021e000 st1d {z0\.d-z3\.d}, pn8, \[x0, x1, lsl #3\]
+[^:]+: a021e01c st1d {z28\.d-z31\.d}, pn8, \[x0, x1, lsl #3\]
+[^:]+: a021fc00 st1d {z0\.d-z3\.d}, pn15, \[x0, x1, lsl #3\]
+[^:]+: a021e3c0 st1d {z0\.d-z3\.d}, pn8, \[x30, x1, lsl #3\]
+[^:]+: a021e3e0 st1d {z0\.d-z3\.d}, pn8, \[sp, x1, lsl #3\]
+[^:]+: a03ee000 st1d {z0\.d-z3\.d}, pn8, \[x0, x30, lsl #3\]
+[^:]+: a03fe000 st1d {z0\.d-z3\.d}, pn8, \[x0, xzr, lsl #3\]
+[^:]+: a021ef68 st1d {z8\.d-z11\.d}, pn11, \[x27, x1, lsl #3\]
+[^:]+: a0606001 stnt1d {z0\.d-z1\.d}, pn8, \[x0\]
+[^:]+: a0606001 stnt1d {z0\.d-z1\.d}, pn8, \[x0\]
+[^:]+: a0606001 stnt1d {z0\.d-z1\.d}, pn8, \[x0\]
+[^:]+: a060601f stnt1d {z30\.d-z31\.d}, pn8, \[x0\]
+[^:]+: a0607c01 stnt1d {z0\.d-z1\.d}, pn15, \[x0\]
+[^:]+: a06063c1 stnt1d {z0\.d-z1\.d}, pn8, \[x30\]
+[^:]+: a06063e1 stnt1d {z0\.d-z1\.d}, pn8, \[sp\]
+[^:]+: a0686001 stnt1d {z0\.d-z1\.d}, pn8, \[x0, #-16, mul vl\]
+[^:]+: a0676001 stnt1d {z0\.d-z1\.d}, pn8, \[x0, #14, mul vl\]
+[^:]+: a06b756d stnt1d {z12\.d-z13\.d}, pn13, \[x11, #-10, mul vl\]
+[^:]+: a060e001 stnt1d {z0\.d-z3\.d}, pn8, \[x0\]
+[^:]+: a060e001 stnt1d {z0\.d-z3\.d}, pn8, \[x0\]
+[^:]+: a060e001 stnt1d {z0\.d-z3\.d}, pn8, \[x0\]
+[^:]+: a060e01d stnt1d {z28\.d-z31\.d}, pn8, \[x0\]
+[^:]+: a060fc01 stnt1d {z0\.d-z3\.d}, pn15, \[x0\]
+[^:]+: a060e3c1 stnt1d {z0\.d-z3\.d}, pn8, \[x30\]
+[^:]+: a060e3e1 stnt1d {z0\.d-z3\.d}, pn8, \[sp\]
+[^:]+: a068e001 stnt1d {z0\.d-z3\.d}, pn8, \[x0, #-32, mul vl\]
+[^:]+: a067e001 stnt1d {z0\.d-z3\.d}, pn8, \[x0, #28, mul vl\]
+[^:]+: a065ee29 stnt1d {z8\.d-z11\.d}, pn11, \[x17, #20, mul vl\]
+[^:]+: a0216001 stnt1d {z0\.d-z1\.d}, pn8, \[x0, x1, lsl #3\]
+[^:]+: a0216001 stnt1d {z0\.d-z1\.d}, pn8, \[x0, x1, lsl #3\]
+[^:]+: a0216001 stnt1d {z0\.d-z1\.d}, pn8, \[x0, x1, lsl #3\]
+[^:]+: a021601f stnt1d {z30\.d-z31\.d}, pn8, \[x0, x1, lsl #3\]
+[^:]+: a0217c01 stnt1d {z0\.d-z1\.d}, pn15, \[x0, x1, lsl #3\]
+[^:]+: a02163c1 stnt1d {z0\.d-z1\.d}, pn8, \[x30, x1, lsl #3\]
+[^:]+: a02163e1 stnt1d {z0\.d-z1\.d}, pn8, \[sp, x1, lsl #3\]
+[^:]+: a03e6001 stnt1d {z0\.d-z1\.d}, pn8, \[x0, x30, lsl #3\]
+[^:]+: a03f6001 stnt1d {z0\.d-z1\.d}, pn8, \[x0, xzr, lsl #3\]
+[^:]+: a023674f stnt1d {z14\.d-z15\.d}, pn9, \[x26, x3, lsl #3\]
+[^:]+: a021e001 stnt1d {z0\.d-z3\.d}, pn8, \[x0, x1, lsl #3\]
+[^:]+: a021e001 stnt1d {z0\.d-z3\.d}, pn8, \[x0, x1, lsl #3\]
+[^:]+: a021e001 stnt1d {z0\.d-z3\.d}, pn8, \[x0, x1, lsl #3\]
+[^:]+: a021e01d stnt1d {z28\.d-z31\.d}, pn8, \[x0, x1, lsl #3\]
+[^:]+: a021fc01 stnt1d {z0\.d-z3\.d}, pn15, \[x0, x1, lsl #3\]
+[^:]+: a021e3c1 stnt1d {z0\.d-z3\.d}, pn8, \[x30, x1, lsl #3\]
+[^:]+: a021e3e1 stnt1d {z0\.d-z3\.d}, pn8, \[sp, x1, lsl #3\]
+[^:]+: a03ee001 stnt1d {z0\.d-z3\.d}, pn8, \[x0, x30, lsl #3\]
+[^:]+: a03fe001 stnt1d {z0\.d-z3\.d}, pn8, \[x0, xzr, lsl #3\]
+[^:]+: a021ef69 stnt1d {z8\.d-z11\.d}, pn11, \[x27, x1, lsl #3\]
diff --git a/gas/testsuite/gas/aarch64/sme2-3-sve2p1.s b/gas/testsuite/gas/aarch64/sme2-3-sve2p1.s
new file mode 100644
index 0000000000000000000000000000000000000000..42c56b46a7bbab4a7d5092a1a1ba8e628cb7e477
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-3-sve2p1.s
@@ -0,0 +1,175 @@
+ ld1d { z0.d - z1.d }, pn8/z, [x0]
+ ld1d { z0.d - z1.d }, pn8/z, [x0, #0, mul vl]
+ LD1D { Z0.D - Z1.D }, PN8/Z, [X0]
+ ld1d { z30.d - z31.d }, pn8/z, [x0]
+ ld1d { z0.d - z1.d }, pn15/z, [x0]
+ ld1d { z0.d - z1.d }, pn8/z, [x30]
+ ld1d { z0.d - z1.d }, pn8/z, [sp]
+ ld1d { z0.d - z1.d }, pn8/z, [x0, #-16, mul vl]
+ ld1d { z0.d - z1.d }, pn8/z, [x0, #14, mul vl]
+ ld1d { z12.d - z13.d }, pn13/z, [x11, #-10, mul vl]
+
+ ld1d { z0.d - z3.d }, pn8/z, [x0]
+ ld1d { z0.d - z3.d }, pn8/z, [x0, #0, mul vl]
+ LD1D { Z0.D - Z3.D }, PN8/Z, [X0]
+ ld1d { z28.d - z31.d }, pn8/z, [x0]
+ ld1d { z0.d - z3.d }, pn15/z, [x0]
+ ld1d { z0.d - z3.d }, pn8/z, [x30]
+ ld1d { z0.d - z3.d }, pn8/z, [sp]
+ ld1d { z0.d - z3.d }, pn8/z, [x0, #-32, mul vl]
+ ld1d { z0.d - z3.d }, pn8/z, [x0, #28, mul vl]
+ ld1d { z8.d - z11.d }, pn11/z, [x17, #20, mul vl]
+
+ ld1d { z0.d - z1.d }, pn8/z, [x0, x1, lsl 3]
+ ld1d { z0.d - z1.d }, pn8/z, [x0, x1, lsl #3]
+ LD1D { Z0.D - Z1.D }, PN8/Z, [X0, X1, LSL #3]
+ ld1d { z30.d - z31.d }, pn8/z, [x0, x1, lsl #3]
+ ld1d { z0.d - z1.d }, pn15/z, [x0, x1, lsl #3]
+ ld1d { z0.d - z1.d }, pn8/z, [x30, x1, lsl #3]
+ ld1d { z0.d - z1.d }, pn8/z, [sp, x1, lsl #3]
+ ld1d { z0.d - z1.d }, pn8/z, [x0, x30, lsl #3]
+ ld1d { z0.d - z1.d }, pn8/z, [x0, xzr, lsl #3]
+ ld1d { z14.d - z15.d }, pn9/z, [x26, x3, lsl #3]
+
+ ld1d { z0.d - z3.d }, pn8/z, [x0, x1, lsl 3]
+ ld1d { z0.d - z3.d }, pn8/z, [x0, x1, lsl #3]
+ LD1D { Z0.D - Z3.D }, PN8/Z, [X0, X1, LSL #3]
+ ld1d { z28.d - z31.d }, pn8/z, [x0, x1, lsl #3]
+ ld1d { z0.d - z3.d }, pn15/z, [x0, x1, lsl #3]
+ ld1d { z0.d - z3.d }, pn8/z, [x30, x1, lsl #3]
+ ld1d { z0.d - z3.d }, pn8/z, [sp, x1, lsl #3]
+ ld1d { z0.d - z3.d }, pn8/z, [x0, x30, lsl #3]
+ ld1d { z0.d - z3.d }, pn8/z, [x0, xzr, lsl #3]
+ ld1d { z8.d - z11.d }, pn11/z, [x27, x1, lsl #3]
+
+ ldnt1d { z0.d - z1.d }, pn8/z, [x0]
+ ldnt1d { z0.d - z1.d }, pn8/z, [x0, #0, mul vl]
+ LDNT1D { Z0.D - Z1.D }, PN8/Z, [X0]
+ ldnt1d { z30.d - z31.d }, pn8/z, [x0]
+ ldnt1d { z0.d - z1.d }, pn15/z, [x0]
+ ldnt1d { z0.d - z1.d }, pn8/z, [x30]
+ ldnt1d { z0.d - z1.d }, pn8/z, [sp]
+ ldnt1d { z0.d - z1.d }, pn8/z, [x0, #-16, mul vl]
+ ldnt1d { z0.d - z1.d }, pn8/z, [x0, #14, mul vl]
+ ldnt1d { z12.d - z13.d }, pn13/z, [x11, #-10, mul vl]
+
+ ldnt1d { z0.d - z3.d }, pn8/z, [x0]
+ ldnt1d { z0.d - z3.d }, pn8/z, [x0, #0, mul vl]
+ LDNT1D { Z0.D - Z3.D }, PN8/Z, [X0]
+ ldnt1d { z28.d - z31.d }, pn8/z, [x0]
+ ldnt1d { z0.d - z3.d }, pn15/z, [x0]
+ ldnt1d { z0.d - z3.d }, pn8/z, [x30]
+ ldnt1d { z0.d - z3.d }, pn8/z, [sp]
+ ldnt1d { z0.d - z3.d }, pn8/z, [x0, #-32, mul vl]
+ ldnt1d { z0.d - z3.d }, pn8/z, [x0, #28, mul vl]
+ ldnt1d { z8.d - z11.d }, pn11/z, [x17, #20, mul vl]
+
+ ldnt1d { z0.d - z1.d }, pn8/z, [x0, x1, lsl 3]
+ ldnt1d { z0.d - z1.d }, pn8/z, [x0, x1, lsl #3]
+ LDNT1D { Z0.D - Z1.D }, PN8/Z, [X0, X1, LSL #3]
+ ldnt1d { z30.d - z31.d }, pn8/z, [x0, x1, lsl #3]
+ ldnt1d { z0.d - z1.d }, pn15/z, [x0, x1, lsl #3]
+ ldnt1d { z0.d - z1.d }, pn8/z, [x30, x1, lsl #3]
+ ldnt1d { z0.d - z1.d }, pn8/z, [sp, x1, lsl #3]
+ ldnt1d { z0.d - z1.d }, pn8/z, [x0, x30, lsl #3]
+ ldnt1d { z0.d - z1.d }, pn8/z, [x0, xzr, lsl #3]
+ ldnt1d { z14.d - z15.d }, pn9/z, [x26, x3, lsl #3]
+
+ ldnt1d { z0.d - z3.d }, pn8/z, [x0, x1, lsl 3]
+ ldnt1d { z0.d - z3.d }, pn8/z, [x0, x1, lsl #3]
+ LDNT1D { Z0.D - Z3.D }, PN8/Z, [X0, X1, LSL #3]
+ ldnt1d { z28.d - z31.d }, pn8/z, [x0, x1, lsl #3]
+ ldnt1d { z0.d - z3.d }, pn15/z, [x0, x1, lsl #3]
+ ldnt1d { z0.d - z3.d }, pn8/z, [x30, x1, lsl #3]
+ ldnt1d { z0.d - z3.d }, pn8/z, [sp, x1, lsl #3]
+ ldnt1d { z0.d - z3.d }, pn8/z, [x0, x30, lsl #3]
+ ldnt1d { z0.d - z3.d }, pn8/z, [x0, xzr, lsl #3]
+ ldnt1d { z8.d - z11.d }, pn11/z, [x27, x1, lsl #3]
+
+ st1d { z0.d - z1.d }, pn8, [x0]
+ st1d { z0.d - z1.d }, pn8, [x0, #0, mul vl]
+ ST1D { Z0.D - Z1.D }, PN8, [X0]
+ st1d { z30.d - z31.d }, pn8, [x0]
+ st1d { z0.d - z1.d }, pn15, [x0]
+ st1d { z0.d - z1.d }, pn8, [x30]
+ st1d { z0.d - z1.d }, pn8, [sp]
+ st1d { z0.d - z1.d }, pn8, [x0, #-16, mul vl]
+ st1d { z0.d - z1.d }, pn8, [x0, #14, mul vl]
+ st1d { z12.d - z13.d }, pn13, [x11, #-10, mul vl]
+
+ st1d { z0.d - z3.d }, pn8, [x0]
+ st1d { z0.d - z3.d }, pn8, [x0, #0, mul vl]
+ ST1D { Z0.D - Z3.D }, PN8, [X0]
+ st1d { z28.d - z31.d }, pn8, [x0]
+ st1d { z0.d - z3.d }, pn15, [x0]
+ st1d { z0.d - z3.d }, pn8, [x30]
+ st1d { z0.d - z3.d }, pn8, [sp]
+ st1d { z0.d - z3.d }, pn8, [x0, #-32, mul vl]
+ st1d { z0.d - z3.d }, pn8, [x0, #28, mul vl]
+ st1d { z8.d - z11.d }, pn11, [x17, #20, mul vl]
+
+ st1d { z0.d - z1.d }, pn8, [x0, x1, lsl 3]
+ st1d { z0.d - z1.d }, pn8, [x0, x1, lsl #3]
+ ST1D { Z0.D - Z1.D }, PN8, [X0, X1, LSL #3]
+ st1d { z30.d - z31.d }, pn8, [x0, x1, lsl #3]
+ st1d { z0.d - z1.d }, pn15, [x0, x1, lsl #3]
+ st1d { z0.d - z1.d }, pn8, [x30, x1, lsl #3]
+ st1d { z0.d - z1.d }, pn8, [sp, x1, lsl #3]
+ st1d { z0.d - z1.d }, pn8, [x0, x30, lsl #3]
+ st1d { z0.d - z1.d }, pn8, [x0, xzr, lsl #3]
+ st1d { z14.d - z15.d }, pn9, [x26, x3, lsl #3]
+
+ st1d { z0.d - z3.d }, pn8, [x0, x1, lsl 3]
+ st1d { z0.d - z3.d }, pn8, [x0, x1, lsl #3]
+ ST1D { Z0.D - Z3.D }, PN8, [X0, X1, LSL #3]
+ st1d { z28.d - z31.d }, pn8, [x0, x1, lsl #3]
+ st1d { z0.d - z3.d }, pn15, [x0, x1, lsl #3]
+ st1d { z0.d - z3.d }, pn8, [x30, x1, lsl #3]
+ st1d { z0.d - z3.d }, pn8, [sp, x1, lsl #3]
+ st1d { z0.d - z3.d }, pn8, [x0, x30, lsl #3]
+ st1d { z0.d - z3.d }, pn8, [x0, xzr, lsl #3]
+ st1d { z8.d - z11.d }, pn11, [x27, x1, lsl #3]
+
+ stnt1d { z0.d - z1.d }, pn8, [x0]
+ stnt1d { z0.d - z1.d }, pn8, [x0, #0, mul vl]
+ STNT1D { Z0.D - Z1.D }, PN8, [X0]
+ stnt1d { z30.d - z31.d }, pn8, [x0]
+ stnt1d { z0.d - z1.d }, pn15, [x0]
+ stnt1d { z0.d - z1.d }, pn8, [x30]
+ stnt1d { z0.d - z1.d }, pn8, [sp]
+ stnt1d { z0.d - z1.d }, pn8, [x0, #-16, mul vl]
+ stnt1d { z0.d - z1.d }, pn8, [x0, #14, mul vl]
+ stnt1d { z12.d - z13.d }, pn13, [x11, #-10, mul vl]
+
+ stnt1d { z0.d - z3.d }, pn8, [x0]
+ stnt1d { z0.d - z3.d }, pn8, [x0, #0, mul vl]
+ STNT1D { Z0.D - Z3.D }, PN8, [X0]
+ stnt1d { z28.d - z31.d }, pn8, [x0]
+ stnt1d { z0.d - z3.d }, pn15, [x0]
+ stnt1d { z0.d - z3.d }, pn8, [x30]
+ stnt1d { z0.d - z3.d }, pn8, [sp]
+ stnt1d { z0.d - z3.d }, pn8, [x0, #-32, mul vl]
+ stnt1d { z0.d - z3.d }, pn8, [x0, #28, mul vl]
+ stnt1d { z8.d - z11.d }, pn11, [x17, #20, mul vl]
+
+ stnt1d { z0.d - z1.d }, pn8, [x0, x1, lsl 3]
+ stnt1d { z0.d - z1.d }, pn8, [x0, x1, lsl #3]
+ STNT1D { Z0.D - Z1.D }, PN8, [X0, X1, LSL #3]
+ stnt1d { z30.d - z31.d }, pn8, [x0, x1, lsl #3]
+ stnt1d { z0.d - z1.d }, pn15, [x0, x1, lsl #3]
+ stnt1d { z0.d - z1.d }, pn8, [x30, x1, lsl #3]
+ stnt1d { z0.d - z1.d }, pn8, [sp, x1, lsl #3]
+ stnt1d { z0.d - z1.d }, pn8, [x0, x30, lsl #3]
+ stnt1d { z0.d - z1.d }, pn8, [x0, xzr, lsl #3]
+ stnt1d { z14.d - z15.d }, pn9, [x26, x3, lsl #3]
+
+ stnt1d { z0.d - z3.d }, pn8, [x0, x1, lsl 3]
+ stnt1d { z0.d - z3.d }, pn8, [x0, x1, lsl #3]
+ STNT1D { Z0.D - Z3.D }, PN8, [X0, X1, LSL #3]
+ stnt1d { z28.d - z31.d }, pn8, [x0, x1, lsl #3]
+ stnt1d { z0.d - z3.d }, pn15, [x0, x1, lsl #3]
+ stnt1d { z0.d - z3.d }, pn8, [x30, x1, lsl #3]
+ stnt1d { z0.d - z3.d }, pn8, [sp, x1, lsl #3]
+ stnt1d { z0.d - z3.d }, pn8, [x0, x30, lsl #3]
+ stnt1d { z0.d - z3.d }, pn8, [x0, xzr, lsl #3]
+ stnt1d { z8.d - z11.d }, pn11, [x27, x1, lsl #3]
diff --git a/gas/testsuite/gas/aarch64/sme2-4-sve2p1.d b/gas/testsuite/gas/aarch64/sme2-4-sve2p1.d
new file mode 100644
index 0000000000000000000000000000000000000000..83baa5d4f3b879fb7b714948860443dd9cf8e8c7
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-4-sve2p1.d
@@ -0,0 +1,169 @@
+#as: -march=armv8-a+sve2p1
+#objdump: -dr
+
+[^:]+: file format .*
+
+
+[^:]+:
+
+[^:]+:
+[^:]+: a0402000 ld1h {z0\.h-z1\.h}, pn8/z, \[x0\]
+[^:]+: a0402000 ld1h {z0\.h-z1\.h}, pn8/z, \[x0\]
+[^:]+: a0402000 ld1h {z0\.h-z1\.h}, pn8/z, \[x0\]
+[^:]+: a040201e ld1h {z30\.h-z31\.h}, pn8/z, \[x0\]
+[^:]+: a0403c00 ld1h {z0\.h-z1\.h}, pn15/z, \[x0\]
+[^:]+: a04023c0 ld1h {z0\.h-z1\.h}, pn8/z, \[x30\]
+[^:]+: a04023e0 ld1h {z0\.h-z1\.h}, pn8/z, \[sp\]
+[^:]+: a0482000 ld1h {z0\.h-z1\.h}, pn8/z, \[x0, #-16, mul vl\]
+[^:]+: a0472000 ld1h {z0\.h-z1\.h}, pn8/z, \[x0, #14, mul vl\]
+[^:]+: a04b356c ld1h {z12\.h-z13\.h}, pn13/z, \[x11, #-10, mul vl\]
+[^:]+: a040a000 ld1h {z0\.h-z3\.h}, pn8/z, \[x0\]
+[^:]+: a040a000 ld1h {z0\.h-z3\.h}, pn8/z, \[x0\]
+[^:]+: a040a000 ld1h {z0\.h-z3\.h}, pn8/z, \[x0\]
+[^:]+: a040a01c ld1h {z28\.h-z31\.h}, pn8/z, \[x0\]
+[^:]+: a040bc00 ld1h {z0\.h-z3\.h}, pn15/z, \[x0\]
+[^:]+: a040a3c0 ld1h {z0\.h-z3\.h}, pn8/z, \[x30\]
+[^:]+: a040a3e0 ld1h {z0\.h-z3\.h}, pn8/z, \[sp\]
+[^:]+: a048a000 ld1h {z0\.h-z3\.h}, pn8/z, \[x0, #-32, mul vl\]
+[^:]+: a047a000 ld1h {z0\.h-z3\.h}, pn8/z, \[x0, #28, mul vl\]
+[^:]+: a045ae28 ld1h {z8\.h-z11\.h}, pn11/z, \[x17, #20, mul vl\]
+[^:]+: a0012000 ld1h {z0\.h-z1\.h}, pn8/z, \[x0, x1, lsl #1\]
+[^:]+: a0012000 ld1h {z0\.h-z1\.h}, pn8/z, \[x0, x1, lsl #1\]
+[^:]+: a0012000 ld1h {z0\.h-z1\.h}, pn8/z, \[x0, x1, lsl #1\]
+[^:]+: a001201e ld1h {z30\.h-z31\.h}, pn8/z, \[x0, x1, lsl #1\]
+[^:]+: a0013c00 ld1h {z0\.h-z1\.h}, pn15/z, \[x0, x1, lsl #1\]
+[^:]+: a00123c0 ld1h {z0\.h-z1\.h}, pn8/z, \[x30, x1, lsl #1\]
+[^:]+: a00123e0 ld1h {z0\.h-z1\.h}, pn8/z, \[sp, x1, lsl #1\]
+[^:]+: a01e2000 ld1h {z0\.h-z1\.h}, pn8/z, \[x0, x30, lsl #1\]
+[^:]+: a01f2000 ld1h {z0\.h-z1\.h}, pn8/z, \[x0, xzr, lsl #1\]
+[^:]+: a003274e ld1h {z14\.h-z15\.h}, pn9/z, \[x26, x3, lsl #1\]
+[^:]+: a001a000 ld1h {z0\.h-z3\.h}, pn8/z, \[x0, x1, lsl #1\]
+[^:]+: a001a000 ld1h {z0\.h-z3\.h}, pn8/z, \[x0, x1, lsl #1\]
+[^:]+: a001a000 ld1h {z0\.h-z3\.h}, pn8/z, \[x0, x1, lsl #1\]
+[^:]+: a001a01c ld1h {z28\.h-z31\.h}, pn8/z, \[x0, x1, lsl #1\]
+[^:]+: a001bc00 ld1h {z0\.h-z3\.h}, pn15/z, \[x0, x1, lsl #1\]
+[^:]+: a001a3c0 ld1h {z0\.h-z3\.h}, pn8/z, \[x30, x1, lsl #1\]
+[^:]+: a001a3e0 ld1h {z0\.h-z3\.h}, pn8/z, \[sp, x1, lsl #1\]
+[^:]+: a01ea000 ld1h {z0\.h-z3\.h}, pn8/z, \[x0, x30, lsl #1\]
+[^:]+: a01fa000 ld1h {z0\.h-z3\.h}, pn8/z, \[x0, xzr, lsl #1\]
+[^:]+: a001af68 ld1h {z8\.h-z11\.h}, pn11/z, \[x27, x1, lsl #1\]
+[^:]+: a0402001 ldnt1h {z0\.h-z1\.h}, pn8/z, \[x0\]
+[^:]+: a0402001 ldnt1h {z0\.h-z1\.h}, pn8/z, \[x0\]
+[^:]+: a0402001 ldnt1h {z0\.h-z1\.h}, pn8/z, \[x0\]
+[^:]+: a040201f ldnt1h {z30\.h-z31\.h}, pn8/z, \[x0\]
+[^:]+: a0403c01 ldnt1h {z0\.h-z1\.h}, pn15/z, \[x0\]
+[^:]+: a04023c1 ldnt1h {z0\.h-z1\.h}, pn8/z, \[x30\]
+[^:]+: a04023e1 ldnt1h {z0\.h-z1\.h}, pn8/z, \[sp\]
+[^:]+: a0482001 ldnt1h {z0\.h-z1\.h}, pn8/z, \[x0, #-16, mul vl\]
+[^:]+: a0472001 ldnt1h {z0\.h-z1\.h}, pn8/z, \[x0, #14, mul vl\]
+[^:]+: a04b356d ldnt1h {z12\.h-z13\.h}, pn13/z, \[x11, #-10, mul vl\]
+[^:]+: a040a001 ldnt1h {z0\.h-z3\.h}, pn8/z, \[x0\]
+[^:]+: a040a001 ldnt1h {z0\.h-z3\.h}, pn8/z, \[x0\]
+[^:]+: a040a001 ldnt1h {z0\.h-z3\.h}, pn8/z, \[x0\]
+[^:]+: a040a01d ldnt1h {z28\.h-z31\.h}, pn8/z, \[x0\]
+[^:]+: a040bc01 ldnt1h {z0\.h-z3\.h}, pn15/z, \[x0\]
+[^:]+: a040a3c1 ldnt1h {z0\.h-z3\.h}, pn8/z, \[x30\]
+[^:]+: a040a3e1 ldnt1h {z0\.h-z3\.h}, pn8/z, \[sp\]
+[^:]+: a048a001 ldnt1h {z0\.h-z3\.h}, pn8/z, \[x0, #-32, mul vl\]
+[^:]+: a047a001 ldnt1h {z0\.h-z3\.h}, pn8/z, \[x0, #28, mul vl\]
+[^:]+: a045ae29 ldnt1h {z8\.h-z11\.h}, pn11/z, \[x17, #20, mul vl\]
+[^:]+: a0012001 ldnt1h {z0\.h-z1\.h}, pn8/z, \[x0, x1, lsl #1\]
+[^:]+: a0012001 ldnt1h {z0\.h-z1\.h}, pn8/z, \[x0, x1, lsl #1\]
+[^:]+: a0012001 ldnt1h {z0\.h-z1\.h}, pn8/z, \[x0, x1, lsl #1\]
+[^:]+: a001201f ldnt1h {z30\.h-z31\.h}, pn8/z, \[x0, x1, lsl #1\]
+[^:]+: a0013c01 ldnt1h {z0\.h-z1\.h}, pn15/z, \[x0, x1, lsl #1\]
+[^:]+: a00123c1 ldnt1h {z0\.h-z1\.h}, pn8/z, \[x30, x1, lsl #1\]
+[^:]+: a00123e1 ldnt1h {z0\.h-z1\.h}, pn8/z, \[sp, x1, lsl #1\]
+[^:]+: a01e2001 ldnt1h {z0\.h-z1\.h}, pn8/z, \[x0, x30, lsl #1\]
+[^:]+: a01f2001 ldnt1h {z0\.h-z1\.h}, pn8/z, \[x0, xzr, lsl #1\]
+[^:]+: a003274f ldnt1h {z14\.h-z15\.h}, pn9/z, \[x26, x3, lsl #1\]
+[^:]+: a001a001 ldnt1h {z0\.h-z3\.h}, pn8/z, \[x0, x1, lsl #1\]
+[^:]+: a001a001 ldnt1h {z0\.h-z3\.h}, pn8/z, \[x0, x1, lsl #1\]
+[^:]+: a001a001 ldnt1h {z0\.h-z3\.h}, pn8/z, \[x0, x1, lsl #1\]
+[^:]+: a001a01d ldnt1h {z28\.h-z31\.h}, pn8/z, \[x0, x1, lsl #1\]
+[^:]+: a001bc01 ldnt1h {z0\.h-z3\.h}, pn15/z, \[x0, x1, lsl #1\]
+[^:]+: a001a3c1 ldnt1h {z0\.h-z3\.h}, pn8/z, \[x30, x1, lsl #1\]
+[^:]+: a001a3e1 ldnt1h {z0\.h-z3\.h}, pn8/z, \[sp, x1, lsl #1\]
+[^:]+: a01ea001 ldnt1h {z0\.h-z3\.h}, pn8/z, \[x0, x30, lsl #1\]
+[^:]+: a01fa001 ldnt1h {z0\.h-z3\.h}, pn8/z, \[x0, xzr, lsl #1\]
+[^:]+: a001af69 ldnt1h {z8\.h-z11\.h}, pn11/z, \[x27, x1, lsl #1\]
+[^:]+: a0602000 st1h {z0\.h-z1\.h}, pn8, \[x0\]
+[^:]+: a0602000 st1h {z0\.h-z1\.h}, pn8, \[x0\]
+[^:]+: a0602000 st1h {z0\.h-z1\.h}, pn8, \[x0\]
+[^:]+: a060201e st1h {z30\.h-z31\.h}, pn8, \[x0\]
+[^:]+: a0603c00 st1h {z0\.h-z1\.h}, pn15, \[x0\]
+[^:]+: a06023c0 st1h {z0\.h-z1\.h}, pn8, \[x30\]
+[^:]+: a06023e0 st1h {z0\.h-z1\.h}, pn8, \[sp\]
+[^:]+: a0682000 st1h {z0\.h-z1\.h}, pn8, \[x0, #-16, mul vl\]
+[^:]+: a0672000 st1h {z0\.h-z1\.h}, pn8, \[x0, #14, mul vl\]
+[^:]+: a06b356c st1h {z12\.h-z13\.h}, pn13, \[x11, #-10, mul vl\]
+[^:]+: a060a000 st1h {z0\.h-z3\.h}, pn8, \[x0\]
+[^:]+: a060a000 st1h {z0\.h-z3\.h}, pn8, \[x0\]
+[^:]+: a060a000 st1h {z0\.h-z3\.h}, pn8, \[x0\]
+[^:]+: a060a01c st1h {z28\.h-z31\.h}, pn8, \[x0\]
+[^:]+: a060bc00 st1h {z0\.h-z3\.h}, pn15, \[x0\]
+[^:]+: a060a3c0 st1h {z0\.h-z3\.h}, pn8, \[x30\]
+[^:]+: a060a3e0 st1h {z0\.h-z3\.h}, pn8, \[sp\]
+[^:]+: a068a000 st1h {z0\.h-z3\.h}, pn8, \[x0, #-32, mul vl\]
+[^:]+: a067a000 st1h {z0\.h-z3\.h}, pn8, \[x0, #28, mul vl\]
+[^:]+: a065ae28 st1h {z8\.h-z11\.h}, pn11, \[x17, #20, mul vl\]
+[^:]+: a0212000 st1h {z0\.h-z1\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a0212000 st1h {z0\.h-z1\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a0212000 st1h {z0\.h-z1\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a021201e st1h {z30\.h-z31\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a0213c00 st1h {z0\.h-z1\.h}, pn15, \[x0, x1, lsl #1\]
+[^:]+: a02123c0 st1h {z0\.h-z1\.h}, pn8, \[x30, x1, lsl #1\]
+[^:]+: a02123e0 st1h {z0\.h-z1\.h}, pn8, \[sp, x1, lsl #1\]
+[^:]+: a03e2000 st1h {z0\.h-z1\.h}, pn8, \[x0, x30, lsl #1\]
+[^:]+: a03f2000 st1h {z0\.h-z1\.h}, pn8, \[x0, xzr, lsl #1\]
+[^:]+: a023274e st1h {z14\.h-z15\.h}, pn9, \[x26, x3, lsl #1\]
+[^:]+: a021a000 st1h {z0\.h-z3\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a021a000 st1h {z0\.h-z3\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a021a000 st1h {z0\.h-z3\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a021a01c st1h {z28\.h-z31\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a021bc00 st1h {z0\.h-z3\.h}, pn15, \[x0, x1, lsl #1\]
+[^:]+: a021a3c0 st1h {z0\.h-z3\.h}, pn8, \[x30, x1, lsl #1\]
+[^:]+: a021a3e0 st1h {z0\.h-z3\.h}, pn8, \[sp, x1, lsl #1\]
+[^:]+: a03ea000 st1h {z0\.h-z3\.h}, pn8, \[x0, x30, lsl #1\]
+[^:]+: a03fa000 st1h {z0\.h-z3\.h}, pn8, \[x0, xzr, lsl #1\]
+[^:]+: a021af68 st1h {z8\.h-z11\.h}, pn11, \[x27, x1, lsl #1\]
+[^:]+: a0602001 stnt1h {z0\.h-z1\.h}, pn8, \[x0\]
+[^:]+: a0602001 stnt1h {z0\.h-z1\.h}, pn8, \[x0\]
+[^:]+: a0602001 stnt1h {z0\.h-z1\.h}, pn8, \[x0\]
+[^:]+: a060201f stnt1h {z30\.h-z31\.h}, pn8, \[x0\]
+[^:]+: a0603c01 stnt1h {z0\.h-z1\.h}, pn15, \[x0\]
+[^:]+: a06023c1 stnt1h {z0\.h-z1\.h}, pn8, \[x30\]
+[^:]+: a06023e1 stnt1h {z0\.h-z1\.h}, pn8, \[sp\]
+[^:]+: a0682001 stnt1h {z0\.h-z1\.h}, pn8, \[x0, #-16, mul vl\]
+[^:]+: a0672001 stnt1h {z0\.h-z1\.h}, pn8, \[x0, #14, mul vl\]
+[^:]+: a06b356d stnt1h {z12\.h-z13\.h}, pn13, \[x11, #-10, mul vl\]
+[^:]+: a060a001 stnt1h {z0\.h-z3\.h}, pn8, \[x0\]
+[^:]+: a060a001 stnt1h {z0\.h-z3\.h}, pn8, \[x0\]
+[^:]+: a060a001 stnt1h {z0\.h-z3\.h}, pn8, \[x0\]
+[^:]+: a060a01d stnt1h {z28\.h-z31\.h}, pn8, \[x0\]
+[^:]+: a060bc01 stnt1h {z0\.h-z3\.h}, pn15, \[x0\]
+[^:]+: a060a3c1 stnt1h {z0\.h-z3\.h}, pn8, \[x30\]
+[^:]+: a060a3e1 stnt1h {z0\.h-z3\.h}, pn8, \[sp\]
+[^:]+: a068a001 stnt1h {z0\.h-z3\.h}, pn8, \[x0, #-32, mul vl\]
+[^:]+: a067a001 stnt1h {z0\.h-z3\.h}, pn8, \[x0, #28, mul vl\]
+[^:]+: a065ae29 stnt1h {z8\.h-z11\.h}, pn11, \[x17, #20, mul vl\]
+[^:]+: a0212001 stnt1h {z0\.h-z1\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a0212001 stnt1h {z0\.h-z1\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a0212001 stnt1h {z0\.h-z1\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a021201f stnt1h {z30\.h-z31\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a0213c01 stnt1h {z0\.h-z1\.h}, pn15, \[x0, x1, lsl #1\]
+[^:]+: a02123c1 stnt1h {z0\.h-z1\.h}, pn8, \[x30, x1, lsl #1\]
+[^:]+: a02123e1 stnt1h {z0\.h-z1\.h}, pn8, \[sp, x1, lsl #1\]
+[^:]+: a03e2001 stnt1h {z0\.h-z1\.h}, pn8, \[x0, x30, lsl #1\]
+[^:]+: a03f2001 stnt1h {z0\.h-z1\.h}, pn8, \[x0, xzr, lsl #1\]
+[^:]+: a023274f stnt1h {z14\.h-z15\.h}, pn9, \[x26, x3, lsl #1\]
+[^:]+: a021a001 stnt1h {z0\.h-z3\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a021a001 stnt1h {z0\.h-z3\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a021a001 stnt1h {z0\.h-z3\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a021a01d stnt1h {z28\.h-z31\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a021bc01 stnt1h {z0\.h-z3\.h}, pn15, \[x0, x1, lsl #1\]
+[^:]+: a021a3c1 stnt1h {z0\.h-z3\.h}, pn8, \[x30, x1, lsl #1\]
+[^:]+: a021a3e1 stnt1h {z0\.h-z3\.h}, pn8, \[sp, x1, lsl #1\]
+[^:]+: a03ea001 stnt1h {z0\.h-z3\.h}, pn8, \[x0, x30, lsl #1\]
+[^:]+: a03fa001 stnt1h {z0\.h-z3\.h}, pn8, \[x0, xzr, lsl #1\]
+[^:]+: a021af69 stnt1h {z8\.h-z11\.h}, pn11, \[x27, x1, lsl #1\]
diff --git a/gas/testsuite/gas/aarch64/sme2-4-sve2p1.s b/gas/testsuite/gas/aarch64/sme2-4-sve2p1.s
new file mode 100644
index 0000000000000000000000000000000000000000..ec92bbf8207cde973268a8e9312c9458f704e262
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-4-sve2p1.s
@@ -0,0 +1,175 @@
+ ld1h { z0.h - z1.h }, pn8/z, [x0]
+ ld1h { z0.h - z1.h }, pn8/z, [x0, #0, mul vl]
+ LD1H { Z0.H - Z1.H }, PN8/Z, [X0]
+ ld1h { z30.h - z31.h }, pn8/z, [x0]
+ ld1h { z0.h - z1.h }, pn15/z, [x0]
+ ld1h { z0.h - z1.h }, pn8/z, [x30]
+ ld1h { z0.h - z1.h }, pn8/z, [sp]
+ ld1h { z0.h - z1.h }, pn8/z, [x0, #-16, mul vl]
+ ld1h { z0.h - z1.h }, pn8/z, [x0, #14, mul vl]
+ ld1h { z12.h - z13.h }, pn13/z, [x11, #-10, mul vl]
+
+ ld1h { z0.h - z3.h }, pn8/z, [x0]
+ ld1h { z0.h - z3.h }, pn8/z, [x0, #0, mul vl]
+ LD1H { Z0.H - Z3.H }, PN8/Z, [X0]
+ ld1h { z28.h - z31.h }, pn8/z, [x0]
+ ld1h { z0.h - z3.h }, pn15/z, [x0]
+ ld1h { z0.h - z3.h }, pn8/z, [x30]
+ ld1h { z0.h - z3.h }, pn8/z, [sp]
+ ld1h { z0.h - z3.h }, pn8/z, [x0, #-32, mul vl]
+ ld1h { z0.h - z3.h }, pn8/z, [x0, #28, mul vl]
+ ld1h { z8.h - z11.h }, pn11/z, [x17, #20, mul vl]
+
+ ld1h { z0.h - z1.h }, pn8/z, [x0, x1, lsl 1]
+ ld1h { z0.h - z1.h }, pn8/z, [x0, x1, lsl #1]
+ LD1H { Z0.H - Z1.H }, PN8/Z, [X0, X1, LSL #1]
+ ld1h { z30.h - z31.h }, pn8/z, [x0, x1, lsl #1]
+ ld1h { z0.h - z1.h }, pn15/z, [x0, x1, lsl #1]
+ ld1h { z0.h - z1.h }, pn8/z, [x30, x1, lsl #1]
+ ld1h { z0.h - z1.h }, pn8/z, [sp, x1, lsl #1]
+ ld1h { z0.h - z1.h }, pn8/z, [x0, x30, lsl #1]
+ ld1h { z0.h - z1.h }, pn8/z, [x0, xzr, lsl #1]
+ ld1h { z14.h - z15.h }, pn9/z, [x26, x3, lsl #1]
+
+ ld1h { z0.h - z3.h }, pn8/z, [x0, x1, lsl 1]
+ ld1h { z0.h - z3.h }, pn8/z, [x0, x1, lsl #1]
+ LD1H { Z0.H - Z3.H }, PN8/Z, [X0, X1, LSL #1]
+ ld1h { z28.h - z31.h }, pn8/z, [x0, x1, lsl #1]
+ ld1h { z0.h - z3.h }, pn15/z, [x0, x1, lsl #1]
+ ld1h { z0.h - z3.h }, pn8/z, [x30, x1, lsl #1]
+ ld1h { z0.h - z3.h }, pn8/z, [sp, x1, lsl #1]
+ ld1h { z0.h - z3.h }, pn8/z, [x0, x30, lsl #1]
+ ld1h { z0.h - z3.h }, pn8/z, [x0, xzr, lsl #1]
+ ld1h { z8.h - z11.h }, pn11/z, [x27, x1, lsl #1]
+
+ ldnt1h { z0.h - z1.h }, pn8/z, [x0]
+ ldnt1h { z0.h - z1.h }, pn8/z, [x0, #0, mul vl]
+ LDNT1H { Z0.H - Z1.H }, PN8/Z, [X0]
+ ldnt1h { z30.h - z31.h }, pn8/z, [x0]
+ ldnt1h { z0.h - z1.h }, pn15/z, [x0]
+ ldnt1h { z0.h - z1.h }, pn8/z, [x30]
+ ldnt1h { z0.h - z1.h }, pn8/z, [sp]
+ ldnt1h { z0.h - z1.h }, pn8/z, [x0, #-16, mul vl]
+ ldnt1h { z0.h - z1.h }, pn8/z, [x0, #14, mul vl]
+ ldnt1h { z12.h - z13.h }, pn13/z, [x11, #-10, mul vl]
+
+ ldnt1h { z0.h - z3.h }, pn8/z, [x0]
+ ldnt1h { z0.h - z3.h }, pn8/z, [x0, #0, mul vl]
+ LDNT1H { Z0.H - Z3.H }, PN8/Z, [X0]
+ ldnt1h { z28.h - z31.h }, pn8/z, [x0]
+ ldnt1h { z0.h - z3.h }, pn15/z, [x0]
+ ldnt1h { z0.h - z3.h }, pn8/z, [x30]
+ ldnt1h { z0.h - z3.h }, pn8/z, [sp]
+ ldnt1h { z0.h - z3.h }, pn8/z, [x0, #-32, mul vl]
+ ldnt1h { z0.h - z3.h }, pn8/z, [x0, #28, mul vl]
+ ldnt1h { z8.h - z11.h }, pn11/z, [x17, #20, mul vl]
+
+ ldnt1h { z0.h - z1.h }, pn8/z, [x0, x1, lsl 1]
+ ldnt1h { z0.h - z1.h }, pn8/z, [x0, x1, lsl #1]
+ LDNT1H { Z0.H - Z1.H }, PN8/Z, [X0, X1, LSL #1]
+ ldnt1h { z30.h - z31.h }, pn8/z, [x0, x1, lsl #1]
+ ldnt1h { z0.h - z1.h }, pn15/z, [x0, x1, lsl #1]
+ ldnt1h { z0.h - z1.h }, pn8/z, [x30, x1, lsl #1]
+ ldnt1h { z0.h - z1.h }, pn8/z, [sp, x1, lsl #1]
+ ldnt1h { z0.h - z1.h }, pn8/z, [x0, x30, lsl #1]
+ ldnt1h { z0.h - z1.h }, pn8/z, [x0, xzr, lsl #1]
+ ldnt1h { z14.h - z15.h }, pn9/z, [x26, x3, lsl #1]
+
+ ldnt1h { z0.h - z3.h }, pn8/z, [x0, x1, lsl 1]
+ ldnt1h { z0.h - z3.h }, pn8/z, [x0, x1, lsl #1]
+ LDNT1H { Z0.H - Z3.H }, PN8/Z, [X0, X1, LSL #1]
+ ldnt1h { z28.h - z31.h }, pn8/z, [x0, x1, lsl #1]
+ ldnt1h { z0.h - z3.h }, pn15/z, [x0, x1, lsl #1]
+ ldnt1h { z0.h - z3.h }, pn8/z, [x30, x1, lsl #1]
+ ldnt1h { z0.h - z3.h }, pn8/z, [sp, x1, lsl #1]
+ ldnt1h { z0.h - z3.h }, pn8/z, [x0, x30, lsl #1]
+ ldnt1h { z0.h - z3.h }, pn8/z, [x0, xzr, lsl #1]
+ ldnt1h { z8.h - z11.h }, pn11/z, [x27, x1, lsl #1]
+
+ st1h { z0.h - z1.h }, pn8, [x0]
+ st1h { z0.h - z1.h }, pn8, [x0, #0, mul vl]
+ ST1H { Z0.H - Z1.H }, PN8, [X0]
+ st1h { z30.h - z31.h }, pn8, [x0]
+ st1h { z0.h - z1.h }, pn15, [x0]
+ st1h { z0.h - z1.h }, pn8, [x30]
+ st1h { z0.h - z1.h }, pn8, [sp]
+ st1h { z0.h - z1.h }, pn8, [x0, #-16, mul vl]
+ st1h { z0.h - z1.h }, pn8, [x0, #14, mul vl]
+ st1h { z12.h - z13.h }, pn13, [x11, #-10, mul vl]
+
+ st1h { z0.h - z3.h }, pn8, [x0]
+ st1h { z0.h - z3.h }, pn8, [x0, #0, mul vl]
+ ST1H { Z0.H - Z3.H }, PN8, [X0]
+ st1h { z28.h - z31.h }, pn8, [x0]
+ st1h { z0.h - z3.h }, pn15, [x0]
+ st1h { z0.h - z3.h }, pn8, [x30]
+ st1h { z0.h - z3.h }, pn8, [sp]
+ st1h { z0.h - z3.h }, pn8, [x0, #-32, mul vl]
+ st1h { z0.h - z3.h }, pn8, [x0, #28, mul vl]
+ st1h { z8.h - z11.h }, pn11, [x17, #20, mul vl]
+
+ st1h { z0.h - z1.h }, pn8, [x0, x1, lsl 1]
+ st1h { z0.h - z1.h }, pn8, [x0, x1, lsl #1]
+ ST1H { Z0.H - Z1.H }, PN8, [X0, X1, LSL #1]
+ st1h { z30.h - z31.h }, pn8, [x0, x1, lsl #1]
+ st1h { z0.h - z1.h }, pn15, [x0, x1, lsl #1]
+ st1h { z0.h - z1.h }, pn8, [x30, x1, lsl #1]
+ st1h { z0.h - z1.h }, pn8, [sp, x1, lsl #1]
+ st1h { z0.h - z1.h }, pn8, [x0, x30, lsl #1]
+ st1h { z0.h - z1.h }, pn8, [x0, xzr, lsl #1]
+ st1h { z14.h - z15.h }, pn9, [x26, x3, lsl #1]
+
+ st1h { z0.h - z3.h }, pn8, [x0, x1, lsl 1]
+ st1h { z0.h - z3.h }, pn8, [x0, x1, lsl #1]
+ ST1H { Z0.H - Z3.H }, PN8, [X0, X1, LSL #1]
+ st1h { z28.h - z31.h }, pn8, [x0, x1, lsl #1]
+ st1h { z0.h - z3.h }, pn15, [x0, x1, lsl #1]
+ st1h { z0.h - z3.h }, pn8, [x30, x1, lsl #1]
+ st1h { z0.h - z3.h }, pn8, [sp, x1, lsl #1]
+ st1h { z0.h - z3.h }, pn8, [x0, x30, lsl #1]
+ st1h { z0.h - z3.h }, pn8, [x0, xzr, lsl #1]
+ st1h { z8.h - z11.h }, pn11, [x27, x1, lsl #1]
+
+ stnt1h { z0.h - z1.h }, pn8, [x0]
+ stnt1h { z0.h - z1.h }, pn8, [x0, #0, mul vl]
+ STNT1H { Z0.H - Z1.H }, PN8, [X0]
+ stnt1h { z30.h - z31.h }, pn8, [x0]
+ stnt1h { z0.h - z1.h }, pn15, [x0]
+ stnt1h { z0.h - z1.h }, pn8, [x30]
+ stnt1h { z0.h - z1.h }, pn8, [sp]
+ stnt1h { z0.h - z1.h }, pn8, [x0, #-16, mul vl]
+ stnt1h { z0.h - z1.h }, pn8, [x0, #14, mul vl]
+ stnt1h { z12.h - z13.h }, pn13, [x11, #-10, mul vl]
+
+ stnt1h { z0.h - z3.h }, pn8, [x0]
+ stnt1h { z0.h - z3.h }, pn8, [x0, #0, mul vl]
+ STNT1H { Z0.H - Z3.H }, PN8, [X0]
+ stnt1h { z28.h - z31.h }, pn8, [x0]
+ stnt1h { z0.h - z3.h }, pn15, [x0]
+ stnt1h { z0.h - z3.h }, pn8, [x30]
+ stnt1h { z0.h - z3.h }, pn8, [sp]
+ stnt1h { z0.h - z3.h }, pn8, [x0, #-32, mul vl]
+ stnt1h { z0.h - z3.h }, pn8, [x0, #28, mul vl]
+ stnt1h { z8.h - z11.h }, pn11, [x17, #20, mul vl]
+
+ stnt1h { z0.h - z1.h }, pn8, [x0, x1, lsl 1]
+ stnt1h { z0.h - z1.h }, pn8, [x0, x1, lsl #1]
+ STNT1H { Z0.H - Z1.H }, PN8, [X0, X1, LSL #1]
+ stnt1h { z30.h - z31.h }, pn8, [x0, x1, lsl #1]
+ stnt1h { z0.h - z1.h }, pn15, [x0, x1, lsl #1]
+ stnt1h { z0.h - z1.h }, pn8, [x30, x1, lsl #1]
+ stnt1h { z0.h - z1.h }, pn8, [sp, x1, lsl #1]
+ stnt1h { z0.h - z1.h }, pn8, [x0, x30, lsl #1]
+ stnt1h { z0.h - z1.h }, pn8, [x0, xzr, lsl #1]
+ stnt1h { z14.h - z15.h }, pn9, [x26, x3, lsl #1]
+
+ stnt1h { z0.h - z3.h }, pn8, [x0, x1, lsl 1]
+ stnt1h { z0.h - z3.h }, pn8, [x0, x1, lsl #1]
+ STNT1H { Z0.H - Z3.H }, PN8, [X0, X1, LSL #1]
+ stnt1h { z28.h - z31.h }, pn8, [x0, x1, lsl #1]
+ stnt1h { z0.h - z3.h }, pn15, [x0, x1, lsl #1]
+ stnt1h { z0.h - z3.h }, pn8, [x30, x1, lsl #1]
+ stnt1h { z0.h - z3.h }, pn8, [sp, x1, lsl #1]
+ stnt1h { z0.h - z3.h }, pn8, [x0, x30, lsl #1]
+ stnt1h { z0.h - z3.h }, pn8, [x0, xzr, lsl #1]
+ stnt1h { z8.h - z11.h }, pn11, [x27, x1, lsl #1]
diff --git a/gas/testsuite/gas/aarch64/sme2-5-sve2p1.d b/gas/testsuite/gas/aarch64/sme2-5-sve2p1.d
new file mode 100644
index 0000000000000000000000000000000000000000..e9cb7f296b34341d5b056b3d3c93949bf6fd08b8
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-5-sve2p1.d
@@ -0,0 +1,169 @@
+#as: -march=armv8-a+sve2p1
+#objdump: -dr
+
+[^:]+: file format .*
+
+
+[^:]+:
+
+[^:]+:
+[^:]+: a0404000 ld1w {z0\.s-z1\.s}, pn8/z, \[x0\]
+[^:]+: a0404000 ld1w {z0\.s-z1\.s}, pn8/z, \[x0\]
+[^:]+: a0404000 ld1w {z0\.s-z1\.s}, pn8/z, \[x0\]
+[^:]+: a040401e ld1w {z30\.s-z31\.s}, pn8/z, \[x0\]
+[^:]+: a0405c00 ld1w {z0\.s-z1\.s}, pn15/z, \[x0\]
+[^:]+: a04043c0 ld1w {z0\.s-z1\.s}, pn8/z, \[x30\]
+[^:]+: a04043e0 ld1w {z0\.s-z1\.s}, pn8/z, \[sp\]
+[^:]+: a0484000 ld1w {z0\.s-z1\.s}, pn8/z, \[x0, #-16, mul vl\]
+[^:]+: a0474000 ld1w {z0\.s-z1\.s}, pn8/z, \[x0, #14, mul vl\]
+[^:]+: a04b556c ld1w {z12\.s-z13\.s}, pn13/z, \[x11, #-10, mul vl\]
+[^:]+: a040c000 ld1w {z0\.s-z3\.s}, pn8/z, \[x0\]
+[^:]+: a040c000 ld1w {z0\.s-z3\.s}, pn8/z, \[x0\]
+[^:]+: a040c000 ld1w {z0\.s-z3\.s}, pn8/z, \[x0\]
+[^:]+: a040c01c ld1w {z28\.s-z31\.s}, pn8/z, \[x0\]
+[^:]+: a040dc00 ld1w {z0\.s-z3\.s}, pn15/z, \[x0\]
+[^:]+: a040c3c0 ld1w {z0\.s-z3\.s}, pn8/z, \[x30\]
+[^:]+: a040c3e0 ld1w {z0\.s-z3\.s}, pn8/z, \[sp\]
+[^:]+: a048c000 ld1w {z0\.s-z3\.s}, pn8/z, \[x0, #-32, mul vl\]
+[^:]+: a047c000 ld1w {z0\.s-z3\.s}, pn8/z, \[x0, #28, mul vl\]
+[^:]+: a045ce28 ld1w {z8\.s-z11\.s}, pn11/z, \[x17, #20, mul vl\]
+[^:]+: a0014000 ld1w {z0\.s-z1\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a0014000 ld1w {z0\.s-z1\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a0014000 ld1w {z0\.s-z1\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a001401e ld1w {z30\.s-z31\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a0015c00 ld1w {z0\.s-z1\.s}, pn15/z, \[x0, x1, lsl #2\]
+[^:]+: a00143c0 ld1w {z0\.s-z1\.s}, pn8/z, \[x30, x1, lsl #2\]
+[^:]+: a00143e0 ld1w {z0\.s-z1\.s}, pn8/z, \[sp, x1, lsl #2\]
+[^:]+: a01e4000 ld1w {z0\.s-z1\.s}, pn8/z, \[x0, x30, lsl #2\]
+[^:]+: a01f4000 ld1w {z0\.s-z1\.s}, pn8/z, \[x0, xzr, lsl #2\]
+[^:]+: a003474e ld1w {z14\.s-z15\.s}, pn9/z, \[x26, x3, lsl #2\]
+[^:]+: a001c000 ld1w {z0\.s-z3\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a001c000 ld1w {z0\.s-z3\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a001c000 ld1w {z0\.s-z3\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a001c01c ld1w {z28\.s-z31\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a001dc00 ld1w {z0\.s-z3\.s}, pn15/z, \[x0, x1, lsl #2\]
+[^:]+: a001c3c0 ld1w {z0\.s-z3\.s}, pn8/z, \[x30, x1, lsl #2\]
+[^:]+: a001c3e0 ld1w {z0\.s-z3\.s}, pn8/z, \[sp, x1, lsl #2\]
+[^:]+: a01ec000 ld1w {z0\.s-z3\.s}, pn8/z, \[x0, x30, lsl #2\]
+[^:]+: a01fc000 ld1w {z0\.s-z3\.s}, pn8/z, \[x0, xzr, lsl #2\]
+[^:]+: a001cf68 ld1w {z8\.s-z11\.s}, pn11/z, \[x27, x1, lsl #2\]
+[^:]+: a0404001 ldnt1w {z0\.s-z1\.s}, pn8/z, \[x0\]
+[^:]+: a0404001 ldnt1w {z0\.s-z1\.s}, pn8/z, \[x0\]
+[^:]+: a0404001 ldnt1w {z0\.s-z1\.s}, pn8/z, \[x0\]
+[^:]+: a040401f ldnt1w {z30\.s-z31\.s}, pn8/z, \[x0\]
+[^:]+: a0405c01 ldnt1w {z0\.s-z1\.s}, pn15/z, \[x0\]
+[^:]+: a04043c1 ldnt1w {z0\.s-z1\.s}, pn8/z, \[x30\]
+[^:]+: a04043e1 ldnt1w {z0\.s-z1\.s}, pn8/z, \[sp\]
+[^:]+: a0484001 ldnt1w {z0\.s-z1\.s}, pn8/z, \[x0, #-16, mul vl\]
+[^:]+: a0474001 ldnt1w {z0\.s-z1\.s}, pn8/z, \[x0, #14, mul vl\]
+[^:]+: a04b556d ldnt1w {z12\.s-z13\.s}, pn13/z, \[x11, #-10, mul vl\]
+[^:]+: a040c001 ldnt1w {z0\.s-z3\.s}, pn8/z, \[x0\]
+[^:]+: a040c001 ldnt1w {z0\.s-z3\.s}, pn8/z, \[x0\]
+[^:]+: a040c001 ldnt1w {z0\.s-z3\.s}, pn8/z, \[x0\]
+[^:]+: a040c01d ldnt1w {z28\.s-z31\.s}, pn8/z, \[x0\]
+[^:]+: a040dc01 ldnt1w {z0\.s-z3\.s}, pn15/z, \[x0\]
+[^:]+: a040c3c1 ldnt1w {z0\.s-z3\.s}, pn8/z, \[x30\]
+[^:]+: a040c3e1 ldnt1w {z0\.s-z3\.s}, pn8/z, \[sp\]
+[^:]+: a048c001 ldnt1w {z0\.s-z3\.s}, pn8/z, \[x0, #-32, mul vl\]
+[^:]+: a047c001 ldnt1w {z0\.s-z3\.s}, pn8/z, \[x0, #28, mul vl\]
+[^:]+: a045ce29 ldnt1w {z8\.s-z11\.s}, pn11/z, \[x17, #20, mul vl\]
+[^:]+: a0014001 ldnt1w {z0\.s-z1\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a0014001 ldnt1w {z0\.s-z1\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a0014001 ldnt1w {z0\.s-z1\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a001401f ldnt1w {z30\.s-z31\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a0015c01 ldnt1w {z0\.s-z1\.s}, pn15/z, \[x0, x1, lsl #2\]
+[^:]+: a00143c1 ldnt1w {z0\.s-z1\.s}, pn8/z, \[x30, x1, lsl #2\]
+[^:]+: a00143e1 ldnt1w {z0\.s-z1\.s}, pn8/z, \[sp, x1, lsl #2\]
+[^:]+: a01e4001 ldnt1w {z0\.s-z1\.s}, pn8/z, \[x0, x30, lsl #2\]
+[^:]+: a01f4001 ldnt1w {z0\.s-z1\.s}, pn8/z, \[x0, xzr, lsl #2\]
+[^:]+: a003474f ldnt1w {z14\.s-z15\.s}, pn9/z, \[x26, x3, lsl #2\]
+[^:]+: a001c001 ldnt1w {z0\.s-z3\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a001c001 ldnt1w {z0\.s-z3\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a001c001 ldnt1w {z0\.s-z3\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a001c01d ldnt1w {z28\.s-z31\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a001dc01 ldnt1w {z0\.s-z3\.s}, pn15/z, \[x0, x1, lsl #2\]
+[^:]+: a001c3c1 ldnt1w {z0\.s-z3\.s}, pn8/z, \[x30, x1, lsl #2\]
+[^:]+: a001c3e1 ldnt1w {z0\.s-z3\.s}, pn8/z, \[sp, x1, lsl #2\]
+[^:]+: a01ec001 ldnt1w {z0\.s-z3\.s}, pn8/z, \[x0, x30, lsl #2\]
+[^:]+: a01fc001 ldnt1w {z0\.s-z3\.s}, pn8/z, \[x0, xzr, lsl #2\]
+[^:]+: a001cf69 ldnt1w {z8\.s-z11\.s}, pn11/z, \[x27, x1, lsl #2\]
+[^:]+: a0604000 st1w {z0\.s-z1\.s}, pn8, \[x0\]
+[^:]+: a0604000 st1w {z0\.s-z1\.s}, pn8, \[x0\]
+[^:]+: a0604000 st1w {z0\.s-z1\.s}, pn8, \[x0\]
+[^:]+: a060401e st1w {z30\.s-z31\.s}, pn8, \[x0\]
+[^:]+: a0605c00 st1w {z0\.s-z1\.s}, pn15, \[x0\]
+[^:]+: a06043c0 st1w {z0\.s-z1\.s}, pn8, \[x30\]
+[^:]+: a06043e0 st1w {z0\.s-z1\.s}, pn8, \[sp\]
+[^:]+: a0684000 st1w {z0\.s-z1\.s}, pn8, \[x0, #-16, mul vl\]
+[^:]+: a0674000 st1w {z0\.s-z1\.s}, pn8, \[x0, #14, mul vl\]
+[^:]+: a06b556c st1w {z12\.s-z13\.s}, pn13, \[x11, #-10, mul vl\]
+[^:]+: a060c000 st1w {z0\.s-z3\.s}, pn8, \[x0\]
+[^:]+: a060c000 st1w {z0\.s-z3\.s}, pn8, \[x0\]
+[^:]+: a060c000 st1w {z0\.s-z3\.s}, pn8, \[x0\]
+[^:]+: a060c01c st1w {z28\.s-z31\.s}, pn8, \[x0\]
+[^:]+: a060dc00 st1w {z0\.s-z3\.s}, pn15, \[x0\]
+[^:]+: a060c3c0 st1w {z0\.s-z3\.s}, pn8, \[x30\]
+[^:]+: a060c3e0 st1w {z0\.s-z3\.s}, pn8, \[sp\]
+[^:]+: a068c000 st1w {z0\.s-z3\.s}, pn8, \[x0, #-32, mul vl\]
+[^:]+: a067c000 st1w {z0\.s-z3\.s}, pn8, \[x0, #28, mul vl\]
+[^:]+: a065ce28 st1w {z8\.s-z11\.s}, pn11, \[x17, #20, mul vl\]
+[^:]+: a0214000 st1w {z0\.s-z1\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a0214000 st1w {z0\.s-z1\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a0214000 st1w {z0\.s-z1\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a021401e st1w {z30\.s-z31\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a0215c00 st1w {z0\.s-z1\.s}, pn15, \[x0, x1, lsl #2\]
+[^:]+: a02143c0 st1w {z0\.s-z1\.s}, pn8, \[x30, x1, lsl #2\]
+[^:]+: a02143e0 st1w {z0\.s-z1\.s}, pn8, \[sp, x1, lsl #2\]
+[^:]+: a03e4000 st1w {z0\.s-z1\.s}, pn8, \[x0, x30, lsl #2\]
+[^:]+: a03f4000 st1w {z0\.s-z1\.s}, pn8, \[x0, xzr, lsl #2\]
+[^:]+: a023474e st1w {z14\.s-z15\.s}, pn9, \[x26, x3, lsl #2\]
+[^:]+: a021c000 st1w {z0\.s-z3\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a021c000 st1w {z0\.s-z3\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a021c000 st1w {z0\.s-z3\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a021c01c st1w {z28\.s-z31\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a021dc00 st1w {z0\.s-z3\.s}, pn15, \[x0, x1, lsl #2\]
+[^:]+: a021c3c0 st1w {z0\.s-z3\.s}, pn8, \[x30, x1, lsl #2\]
+[^:]+: a021c3e0 st1w {z0\.s-z3\.s}, pn8, \[sp, x1, lsl #2\]
+[^:]+: a03ec000 st1w {z0\.s-z3\.s}, pn8, \[x0, x30, lsl #2\]
+[^:]+: a03fc000 st1w {z0\.s-z3\.s}, pn8, \[x0, xzr, lsl #2\]
+[^:]+: a021cf68 st1w {z8\.s-z11\.s}, pn11, \[x27, x1, lsl #2\]
+[^:]+: a0604001 stnt1w {z0\.s-z1\.s}, pn8, \[x0\]
+[^:]+: a0604001 stnt1w {z0\.s-z1\.s}, pn8, \[x0\]
+[^:]+: a0604001 stnt1w {z0\.s-z1\.s}, pn8, \[x0\]
+[^:]+: a060401f stnt1w {z30\.s-z31\.s}, pn8, \[x0\]
+[^:]+: a0605c01 stnt1w {z0\.s-z1\.s}, pn15, \[x0\]
+[^:]+: a06043c1 stnt1w {z0\.s-z1\.s}, pn8, \[x30\]
+[^:]+: a06043e1 stnt1w {z0\.s-z1\.s}, pn8, \[sp\]
+[^:]+: a0684001 stnt1w {z0\.s-z1\.s}, pn8, \[x0, #-16, mul vl\]
+[^:]+: a0674001 stnt1w {z0\.s-z1\.s}, pn8, \[x0, #14, mul vl\]
+[^:]+: a06b556d stnt1w {z12\.s-z13\.s}, pn13, \[x11, #-10, mul vl\]
+[^:]+: a060c001 stnt1w {z0\.s-z3\.s}, pn8, \[x0\]
+[^:]+: a060c001 stnt1w {z0\.s-z3\.s}, pn8, \[x0\]
+[^:]+: a060c001 stnt1w {z0\.s-z3\.s}, pn8, \[x0\]
+[^:]+: a060c01d stnt1w {z28\.s-z31\.s}, pn8, \[x0\]
+[^:]+: a060dc01 stnt1w {z0\.s-z3\.s}, pn15, \[x0\]
+[^:]+: a060c3c1 stnt1w {z0\.s-z3\.s}, pn8, \[x30\]
+[^:]+: a060c3e1 stnt1w {z0\.s-z3\.s}, pn8, \[sp\]
+[^:]+: a068c001 stnt1w {z0\.s-z3\.s}, pn8, \[x0, #-32, mul vl\]
+[^:]+: a067c001 stnt1w {z0\.s-z3\.s}, pn8, \[x0, #28, mul vl\]
+[^:]+: a065ce29 stnt1w {z8\.s-z11\.s}, pn11, \[x17, #20, mul vl\]
+[^:]+: a0214001 stnt1w {z0\.s-z1\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a0214001 stnt1w {z0\.s-z1\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a0214001 stnt1w {z0\.s-z1\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a021401f stnt1w {z30\.s-z31\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a0215c01 stnt1w {z0\.s-z1\.s}, pn15, \[x0, x1, lsl #2\]
+[^:]+: a02143c1 stnt1w {z0\.s-z1\.s}, pn8, \[x30, x1, lsl #2\]
+[^:]+: a02143e1 stnt1w {z0\.s-z1\.s}, pn8, \[sp, x1, lsl #2\]
+[^:]+: a03e4001 stnt1w {z0\.s-z1\.s}, pn8, \[x0, x30, lsl #2\]
+[^:]+: a03f4001 stnt1w {z0\.s-z1\.s}, pn8, \[x0, xzr, lsl #2\]
+[^:]+: a023474f stnt1w {z14\.s-z15\.s}, pn9, \[x26, x3, lsl #2\]
+[^:]+: a021c001 stnt1w {z0\.s-z3\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a021c001 stnt1w {z0\.s-z3\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a021c001 stnt1w {z0\.s-z3\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a021c01d stnt1w {z28\.s-z31\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a021dc01 stnt1w {z0\.s-z3\.s}, pn15, \[x0, x1, lsl #2\]
+[^:]+: a021c3c1 stnt1w {z0\.s-z3\.s}, pn8, \[x30, x1, lsl #2\]
+[^:]+: a021c3e1 stnt1w {z0\.s-z3\.s}, pn8, \[sp, x1, lsl #2\]
+[^:]+: a03ec001 stnt1w {z0\.s-z3\.s}, pn8, \[x0, x30, lsl #2\]
+[^:]+: a03fc001 stnt1w {z0\.s-z3\.s}, pn8, \[x0, xzr, lsl #2\]
+[^:]+: a021cf69 stnt1w {z8\.s-z11\.s}, pn11, \[x27, x1, lsl #2\]
diff --git a/gas/testsuite/gas/aarch64/sme2-5-sve2p1.s b/gas/testsuite/gas/aarch64/sme2-5-sve2p1.s
new file mode 100644
index 0000000000000000000000000000000000000000..0dda4b0c15b0f06a5346e43647cfd3f5c9081850
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-5-sve2p1.s
@@ -0,0 +1,175 @@
+ ld1w { z0.s - z1.s }, pn8/z, [x0]
+ ld1w { z0.s - z1.s }, pn8/z, [x0, #0, mul vl]
+ LD1W { Z0.S - Z1.S }, PN8/Z, [X0]
+ ld1w { z30.s - z31.s }, pn8/z, [x0]
+ ld1w { z0.s - z1.s }, pn15/z, [x0]
+ ld1w { z0.s - z1.s }, pn8/z, [x30]
+ ld1w { z0.s - z1.s }, pn8/z, [sp]
+ ld1w { z0.s - z1.s }, pn8/z, [x0, #-16, mul vl]
+ ld1w { z0.s - z1.s }, pn8/z, [x0, #14, mul vl]
+ ld1w { z12.s - z13.s }, pn13/z, [x11, #-10, mul vl]
+
+ ld1w { z0.s - z3.s }, pn8/z, [x0]
+ ld1w { z0.s - z3.s }, pn8/z, [x0, #0, mul vl]
+ LD1W { Z0.S - Z3.S }, PN8/Z, [X0]
+ ld1w { z28.s - z31.s }, pn8/z, [x0]
+ ld1w { z0.s - z3.s }, pn15/z, [x0]
+ ld1w { z0.s - z3.s }, pn8/z, [x30]
+ ld1w { z0.s - z3.s }, pn8/z, [sp]
+ ld1w { z0.s - z3.s }, pn8/z, [x0, #-32, mul vl]
+ ld1w { z0.s - z3.s }, pn8/z, [x0, #28, mul vl]
+ ld1w { z8.s - z11.s }, pn11/z, [x17, #20, mul vl]
+
+ ld1w { z0.s - z1.s }, pn8/z, [x0, x1, lsl 2]
+ ld1w { z0.s - z1.s }, pn8/z, [x0, x1, lsl #2]
+ LD1W { Z0.S - Z1.S }, PN8/Z, [X0, X1, LSL #2]
+ ld1w { z30.s - z31.s }, pn8/z, [x0, x1, lsl #2]
+ ld1w { z0.s - z1.s }, pn15/z, [x0, x1, lsl #2]
+ ld1w { z0.s - z1.s }, pn8/z, [x30, x1, lsl #2]
+ ld1w { z0.s - z1.s }, pn8/z, [sp, x1, lsl #2]
+ ld1w { z0.s - z1.s }, pn8/z, [x0, x30, lsl #2]
+ ld1w { z0.s - z1.s }, pn8/z, [x0, xzr, lsl #2]
+ ld1w { z14.s - z15.s }, pn9/z, [x26, x3, lsl #2]
+
+ ld1w { z0.s - z3.s }, pn8/z, [x0, x1, lsl 2]
+ ld1w { z0.s - z3.s }, pn8/z, [x0, x1, lsl #2]
+ LD1W { Z0.S - Z3.S }, PN8/Z, [X0, X1, LSL #2]
+ ld1w { z28.s - z31.s }, pn8/z, [x0, x1, lsl #2]
+ ld1w { z0.s - z3.s }, pn15/z, [x0, x1, lsl #2]
+ ld1w { z0.s - z3.s }, pn8/z, [x30, x1, lsl #2]
+ ld1w { z0.s - z3.s }, pn8/z, [sp, x1, lsl #2]
+ ld1w { z0.s - z3.s }, pn8/z, [x0, x30, lsl #2]
+ ld1w { z0.s - z3.s }, pn8/z, [x0, xzr, lsl #2]
+ ld1w { z8.s - z11.s }, pn11/z, [x27, x1, lsl #2]
+
+ ldnt1w { z0.s - z1.s }, pn8/z, [x0]
+ ldnt1w { z0.s - z1.s }, pn8/z, [x0, #0, mul vl]
+ LDNT1W { Z0.S - Z1.S }, PN8/Z, [X0]
+ ldnt1w { z30.s - z31.s }, pn8/z, [x0]
+ ldnt1w { z0.s - z1.s }, pn15/z, [x0]
+ ldnt1w { z0.s - z1.s }, pn8/z, [x30]
+ ldnt1w { z0.s - z1.s }, pn8/z, [sp]
+ ldnt1w { z0.s - z1.s }, pn8/z, [x0, #-16, mul vl]
+ ldnt1w { z0.s - z1.s }, pn8/z, [x0, #14, mul vl]
+ ldnt1w { z12.s - z13.s }, pn13/z, [x11, #-10, mul vl]
+
+ ldnt1w { z0.s - z3.s }, pn8/z, [x0]
+ ldnt1w { z0.s - z3.s }, pn8/z, [x0, #0, mul vl]
+ LDNT1W { Z0.S - Z3.S }, PN8/Z, [X0]
+ ldnt1w { z28.s - z31.s }, pn8/z, [x0]
+ ldnt1w { z0.s - z3.s }, pn15/z, [x0]
+ ldnt1w { z0.s - z3.s }, pn8/z, [x30]
+ ldnt1w { z0.s - z3.s }, pn8/z, [sp]
+ ldnt1w { z0.s - z3.s }, pn8/z, [x0, #-32, mul vl]
+ ldnt1w { z0.s - z3.s }, pn8/z, [x0, #28, mul vl]
+ ldnt1w { z8.s - z11.s }, pn11/z, [x17, #20, mul vl]
+
+ ldnt1w { z0.s - z1.s }, pn8/z, [x0, x1, lsl 2]
+ ldnt1w { z0.s - z1.s }, pn8/z, [x0, x1, lsl #2]
+ LDNT1W { Z0.S - Z1.S }, PN8/Z, [X0, X1, LSL #2]
+ ldnt1w { z30.s - z31.s }, pn8/z, [x0, x1, lsl #2]
+ ldnt1w { z0.s - z1.s }, pn15/z, [x0, x1, lsl #2]
+ ldnt1w { z0.s - z1.s }, pn8/z, [x30, x1, lsl #2]
+ ldnt1w { z0.s - z1.s }, pn8/z, [sp, x1, lsl #2]
+ ldnt1w { z0.s - z1.s }, pn8/z, [x0, x30, lsl #2]
+ ldnt1w { z0.s - z1.s }, pn8/z, [x0, xzr, lsl #2]
+ ldnt1w { z14.s - z15.s }, pn9/z, [x26, x3, lsl #2]
+
+ ldnt1w { z0.s - z3.s }, pn8/z, [x0, x1, lsl 2]
+ ldnt1w { z0.s - z3.s }, pn8/z, [x0, x1, lsl #2]
+ LDNT1W { Z0.S - Z3.S }, PN8/Z, [X0, X1, LSL #2]
+ ldnt1w { z28.s - z31.s }, pn8/z, [x0, x1, lsl #2]
+ ldnt1w { z0.s - z3.s }, pn15/z, [x0, x1, lsl #2]
+ ldnt1w { z0.s - z3.s }, pn8/z, [x30, x1, lsl #2]
+ ldnt1w { z0.s - z3.s }, pn8/z, [sp, x1, lsl #2]
+ ldnt1w { z0.s - z3.s }, pn8/z, [x0, x30, lsl #2]
+ ldnt1w { z0.s - z3.s }, pn8/z, [x0, xzr, lsl #2]
+ ldnt1w { z8.s - z11.s }, pn11/z, [x27, x1, lsl #2]
+
+ st1w { z0.s - z1.s }, pn8, [x0]
+ st1w { z0.s - z1.s }, pn8, [x0, #0, mul vl]
+ ST1W { Z0.S - Z1.S }, PN8, [X0]
+ st1w { z30.s - z31.s }, pn8, [x0]
+ st1w { z0.s - z1.s }, pn15, [x0]
+ st1w { z0.s - z1.s }, pn8, [x30]
+ st1w { z0.s - z1.s }, pn8, [sp]
+ st1w { z0.s - z1.s }, pn8, [x0, #-16, mul vl]
+ st1w { z0.s - z1.s }, pn8, [x0, #14, mul vl]
+ st1w { z12.s - z13.s }, pn13, [x11, #-10, mul vl]
+
+ st1w { z0.s - z3.s }, pn8, [x0]
+ st1w { z0.s - z3.s }, pn8, [x0, #0, mul vl]
+ ST1W { Z0.S - Z3.S }, PN8, [X0]
+ st1w { z28.s - z31.s }, pn8, [x0]
+ st1w { z0.s - z3.s }, pn15, [x0]
+ st1w { z0.s - z3.s }, pn8, [x30]
+ st1w { z0.s - z3.s }, pn8, [sp]
+ st1w { z0.s - z3.s }, pn8, [x0, #-32, mul vl]
+ st1w { z0.s - z3.s }, pn8, [x0, #28, mul vl]
+ st1w { z8.s - z11.s }, pn11, [x17, #20, mul vl]
+
+ st1w { z0.s - z1.s }, pn8, [x0, x1, lsl 2]
+ st1w { z0.s - z1.s }, pn8, [x0, x1, lsl #2]
+ ST1W { Z0.S - Z1.S }, PN8, [X0, X1, LSL #2]
+ st1w { z30.s - z31.s }, pn8, [x0, x1, lsl #2]
+ st1w { z0.s - z1.s }, pn15, [x0, x1, lsl #2]
+ st1w { z0.s - z1.s }, pn8, [x30, x1, lsl #2]
+ st1w { z0.s - z1.s }, pn8, [sp, x1, lsl #2]
+ st1w { z0.s - z1.s }, pn8, [x0, x30, lsl #2]
+ st1w { z0.s - z1.s }, pn8, [x0, xzr, lsl #2]
+ st1w { z14.s - z15.s }, pn9, [x26, x3, lsl #2]
+
+ st1w { z0.s - z3.s }, pn8, [x0, x1, lsl 2]
+ st1w { z0.s - z3.s }, pn8, [x0, x1, lsl #2]
+ ST1W { Z0.S - Z3.S }, PN8, [X0, X1, LSL #2]
+ st1w { z28.s - z31.s }, pn8, [x0, x1, lsl #2]
+ st1w { z0.s - z3.s }, pn15, [x0, x1, lsl #2]
+ st1w { z0.s - z3.s }, pn8, [x30, x1, lsl #2]
+ st1w { z0.s - z3.s }, pn8, [sp, x1, lsl #2]
+ st1w { z0.s - z3.s }, pn8, [x0, x30, lsl #2]
+ st1w { z0.s - z3.s }, pn8, [x0, xzr, lsl #2]
+ st1w { z8.s - z11.s }, pn11, [x27, x1, lsl #2]
+
+ stnt1w { z0.s - z1.s }, pn8, [x0]
+ stnt1w { z0.s - z1.s }, pn8, [x0, #0, mul vl]
+ STNT1W { Z0.S - Z1.S }, PN8, [X0]
+ stnt1w { z30.s - z31.s }, pn8, [x0]
+ stnt1w { z0.s - z1.s }, pn15, [x0]
+ stnt1w { z0.s - z1.s }, pn8, [x30]
+ stnt1w { z0.s - z1.s }, pn8, [sp]
+ stnt1w { z0.s - z1.s }, pn8, [x0, #-16, mul vl]
+ stnt1w { z0.s - z1.s }, pn8, [x0, #14, mul vl]
+ stnt1w { z12.s - z13.s }, pn13, [x11, #-10, mul vl]
+
+ stnt1w { z0.s - z3.s }, pn8, [x0]
+ stnt1w { z0.s - z3.s }, pn8, [x0, #0, mul vl]
+ STNT1W { Z0.S - Z3.S }, PN8, [X0]
+ stnt1w { z28.s - z31.s }, pn8, [x0]
+ stnt1w { z0.s - z3.s }, pn15, [x0]
+ stnt1w { z0.s - z3.s }, pn8, [x30]
+ stnt1w { z0.s - z3.s }, pn8, [sp]
+ stnt1w { z0.s - z3.s }, pn8, [x0, #-32, mul vl]
+ stnt1w { z0.s - z3.s }, pn8, [x0, #28, mul vl]
+ stnt1w { z8.s - z11.s }, pn11, [x17, #20, mul vl]
+
+ stnt1w { z0.s - z1.s }, pn8, [x0, x1, lsl 2]
+ stnt1w { z0.s - z1.s }, pn8, [x0, x1, lsl #2]
+ STNT1W { Z0.S - Z1.S }, PN8, [X0, X1, LSL #2]
+ stnt1w { z30.s - z31.s }, pn8, [x0, x1, lsl #2]
+ stnt1w { z0.s - z1.s }, pn15, [x0, x1, lsl #2]
+ stnt1w { z0.s - z1.s }, pn8, [x30, x1, lsl #2]
+ stnt1w { z0.s - z1.s }, pn8, [sp, x1, lsl #2]
+ stnt1w { z0.s - z1.s }, pn8, [x0, x30, lsl #2]
+ stnt1w { z0.s - z1.s }, pn8, [x0, xzr, lsl #2]
+ stnt1w { z14.s - z15.s }, pn9, [x26, x3, lsl #2]
+
+ stnt1w { z0.s - z3.s }, pn8, [x0, x1, lsl 2]
+ stnt1w { z0.s - z3.s }, pn8, [x0, x1, lsl #2]
+ STNT1W { Z0.S - Z3.S }, PN8, [X0, X1, LSL #2]
+ stnt1w { z28.s - z31.s }, pn8, [x0, x1, lsl #2]
+ stnt1w { z0.s - z3.s }, pn15, [x0, x1, lsl #2]
+ stnt1w { z0.s - z3.s }, pn8, [x30, x1, lsl #2]
+ stnt1w { z0.s - z3.s }, pn8, [sp, x1, lsl #2]
+ stnt1w { z0.s - z3.s }, pn8, [x0, x30, lsl #2]
+ stnt1w { z0.s - z3.s }, pn8, [x0, xzr, lsl #2]
+ stnt1w { z8.s - z11.s }, pn11, [x27, x1, lsl #2]
diff --git a/gas/testsuite/gas/aarch64/sme2-6-sve2p1.d b/gas/testsuite/gas/aarch64/sme2-6-sve2p1.d
new file mode 100644
index 0000000000000000000000000000000000000000..a71d7845dc1cd02b8e505fec0460ad914cd20867
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-6-sve2p1.d
@@ -0,0 +1,109 @@
+#as: -march=armv8-a+sme2
+#objdump: -dr
+
+[^:]+: file format .*
+
+
+[^:]+:
+
+[^:]+:
+[^:]+: 25208200 cntp x0, pn0\.b, vlx2
+[^:]+: 25208200 cntp x0, pn0\.b, vlx2
+[^:]+: 2520821e cntp x30, pn0\.b, vlx2
+[^:]+: 2520821f cntp xzr, pn0\.b, vlx2
+[^:]+: 252083e0 cntp x0, pn15\.b, vlx2
+[^:]+: 25208600 cntp x0, pn0\.b, vlx4
+[^:]+: 252087ab cntp x11, pn13\.b, vlx4
+[^:]+: 25608200 cntp x0, pn0\.h, vlx2
+[^:]+: 25608200 cntp x0, pn0\.h, vlx2
+[^:]+: 2560821e cntp x30, pn0\.h, vlx2
+[^:]+: 2560821f cntp xzr, pn0\.h, vlx2
+[^:]+: 256083e0 cntp x0, pn15\.h, vlx2
+[^:]+: 25608600 cntp x0, pn0\.h, vlx4
+[^:]+: 25608334 cntp x20, pn9\.h, vlx2
+[^:]+: 25a08200 cntp x0, pn0\.s, vlx2
+[^:]+: 25a08200 cntp x0, pn0\.s, vlx2
+[^:]+: 25a0821e cntp x30, pn0\.s, vlx2
+[^:]+: 25a0821f cntp xzr, pn0\.s, vlx2
+[^:]+: 25a083e0 cntp x0, pn15\.s, vlx2
+[^:]+: 25a08600 cntp x0, pn0\.s, vlx4
+[^:]+: 25a0870f cntp x15, pn8\.s, vlx4
+[^:]+: 25e08200 cntp x0, pn0\.d, vlx2
+[^:]+: 25e08200 cntp x0, pn0\.d, vlx2
+[^:]+: 25e0821e cntp x30, pn0\.d, vlx2
+[^:]+: 25e0821f cntp xzr, pn0\.d, vlx2
+[^:]+: 25e083e0 cntp x0, pn15\.d, vlx2
+[^:]+: 25e08600 cntp x0, pn0\.d, vlx4
+[^:]+: 25e082a4 cntp x4, pn5\.d, vlx2
+[^:]+: 25207010 pext p0\.b, pn8\[0\]
+[^:]+: 25207010 pext p0\.b, pn8\[0\]
+[^:]+: 2520701f pext p15\.b, pn8\[0\]
+[^:]+: 252070f0 pext p0\.b, pn15\[0\]
+[^:]+: 25207310 pext p0\.b, pn8\[3\]
+[^:]+: 25207274 pext p4\.b, pn11\[2\]
+[^:]+: 25607010 pext p0\.h, pn8\[0\]
+[^:]+: 25607010 pext p0\.h, pn8\[0\]
+[^:]+: 2560701f pext p15\.h, pn8\[0\]
+[^:]+: 256070f0 pext p0\.h, pn15\[0\]
+[^:]+: 25607310 pext p0\.h, pn8\[3\]
+[^:]+: 256071d5 pext p5\.h, pn14\[1\]
+[^:]+: 25a07010 pext p0\.s, pn8\[0\]
+[^:]+: 25a07010 pext p0\.s, pn8\[0\]
+[^:]+: 25a0701f pext p15\.s, pn8\[0\]
+[^:]+: 25a070f0 pext p0\.s, pn15\[0\]
+[^:]+: 25a07310 pext p0\.s, pn8\[3\]
+[^:]+: 25a07256 pext p6\.s, pn10\[2\]
+[^:]+: 25e07010 pext p0\.d, pn8\[0\]
+[^:]+: 25e07010 pext p0\.d, pn8\[0\]
+[^:]+: 25e0701f pext p15\.d, pn8\[0\]
+[^:]+: 25e070f0 pext p0\.d, pn15\[0\]
+[^:]+: 25e07310 pext p0\.d, pn8\[3\]
+[^:]+: 25e07137 pext p7\.d, pn9\[1\]
+[^:]+: 25207410 pext {p0\.b-p1\.b}, pn8\[0\]
+[^:]+: 25207410 pext {p0\.b-p1\.b}, pn8\[0\]
+[^:]+: 25207410 pext {p0\.b-p1\.b}, pn8\[0\]
+[^:]+: 2520741e pext {p14\.b-p15\.b}, pn8\[0\]
+[^:]+: 2520741f pext {p15\.b-p0\.b}, pn8\[0\]
+[^:]+: 2520741f pext {p15\.b-p0\.b}, pn8\[0\]
+[^:]+: 252074f0 pext {p0\.b-p1\.b}, pn15\[0\]
+[^:]+: 25207510 pext {p0\.b-p1\.b}, pn8\[1\]
+[^:]+: 25207497 pext {p7\.b-p8\.b}, pn12\[0\]
+[^:]+: 25607410 pext {p0\.h-p1\.h}, pn8\[0\]
+[^:]+: 25607410 pext {p0\.h-p1\.h}, pn8\[0\]
+[^:]+: 25607410 pext {p0\.h-p1\.h}, pn8\[0\]
+[^:]+: 2560741e pext {p14\.h-p15\.h}, pn8\[0\]
+[^:]+: 2560741f pext {p15\.h-p0\.h}, pn8\[0\]
+[^:]+: 2560741f pext {p15\.h-p0\.h}, pn8\[0\]
+[^:]+: 256074f0 pext {p0\.h-p1\.h}, pn15\[0\]
+[^:]+: 25607510 pext {p0\.h-p1\.h}, pn8\[1\]
+[^:]+: 256074d2 pext {p2\.h-p3\.h}, pn14\[0\]
+[^:]+: 25a07410 pext {p0\.s-p1\.s}, pn8\[0\]
+[^:]+: 25a07410 pext {p0\.s-p1\.s}, pn8\[0\]
+[^:]+: 25a07410 pext {p0\.s-p1\.s}, pn8\[0\]
+[^:]+: 25a0741e pext {p14\.s-p15\.s}, pn8\[0\]
+[^:]+: 25a0741f pext {p15\.s-p0\.s}, pn8\[0\]
+[^:]+: 25a0741f pext {p15\.s-p0\.s}, pn8\[0\]
+[^:]+: 25a074f0 pext {p0\.s-p1\.s}, pn15\[0\]
+[^:]+: 25a07510 pext {p0\.s-p1\.s}, pn8\[1\]
+[^:]+: 25a074b5 pext {p5\.s-p6\.s}, pn13\[0\]
+[^:]+: 25e07410 pext {p0\.d-p1\.d}, pn8\[0\]
+[^:]+: 25e07410 pext {p0\.d-p1\.d}, pn8\[0\]
+[^:]+: 25e07410 pext {p0\.d-p1\.d}, pn8\[0\]
+[^:]+: 25e0741e pext {p14\.d-p15\.d}, pn8\[0\]
+[^:]+: 25e0741f pext {p15\.d-p0\.d}, pn8\[0\]
+[^:]+: 25e0741f pext {p15\.d-p0\.d}, pn8\[0\]
+[^:]+: 25e074f0 pext {p0\.d-p1\.d}, pn15\[0\]
+[^:]+: 25e07510 pext {p0\.d-p1\.d}, pn8\[1\]
+[^:]+: 25e0743c pext {p12\.d-p13\.d}, pn9\[0\]
+[^:]+: 25207810 ptrue pn8\.b
+[^:]+: 25207813 ptrue pn11\.b
+[^:]+: 25207817 ptrue pn15\.b
+[^:]+: 25607810 ptrue pn8\.h
+[^:]+: 25607811 ptrue pn9\.h
+[^:]+: 25607817 ptrue pn15\.h
+[^:]+: 25a07810 ptrue pn8\.s
+[^:]+: 25a07816 ptrue pn14\.s
+[^:]+: 25a07817 ptrue pn15\.s
+[^:]+: 25e07810 ptrue pn8\.d
+[^:]+: 25e07814 ptrue pn12\.d
+[^:]+: 25e07817 ptrue pn15\.d
diff --git a/gas/testsuite/gas/aarch64/sme2-6-sve2p1.s b/gas/testsuite/gas/aarch64/sme2-6-sve2p1.s
new file mode 100644
index 0000000000000000000000000000000000000000..5fad1252e0cdb5dcd2e93f8d5b10d505657dffaa
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-6-sve2p1.s
@@ -0,0 +1,112 @@
+ cntp x0, pn0.b, vlx2
+ CNTP X0, PN0.B, VLx2
+ cntp x30, pn0.b, vlx2
+ cntp xzr, pn0.b, vlx2
+ cntp x0, pn15.b, vlx2
+ cntp x0, pn0.b, vlx4
+ CNTP X11, PN13.b, VLx4
+
+ cntp x0, pn0.h, vlx2
+ CNTP X0, PN0.H, VLx2
+ cntp x30, pn0.h, vlx2
+ cntp xzr, pn0.h, vlx2
+ cntp x0, pn15.h, vlx2
+ cntp x0, pn0.h, vlx4
+ CNTP X20, PN9.h, VLx2
+
+ cntp x0, pn0.s, vlx2
+ CNTP X0, PN0.s, VLx2
+ cntp x30, pn0.s, vlx2
+ cntp xzr, pn0.s, vlx2
+ cntp x0, pn15.s, vlx2
+ cntp x0, pn0.s, vlx4
+ CNTP X15, PN8.s, VLx4
+
+ cntp x0, pn0.d, vlx2
+ CNTP X0, PN0.d, VLx2
+ cntp x30, pn0.d, vlx2
+ cntp xzr, pn0.d, vlx2
+ cntp x0, pn15.d, vlx2
+ cntp x0, pn0.d, vlx4
+ CNTP X4, PN5.d, VLx2
+
+ pext p0.b, pn8[0]
+ PEXT P0.B, PN8[0]
+ pext p15.b, pn8[0]
+ pext p0.b, pn15[0]
+ pext p0.b, pn8[3]
+ pext p4.b, pn11[2]
+
+ pext p0.h, pn8[0]
+ PEXT P0.H, PN8[0]
+ pext p15.h, pn8[0]
+ pext p0.h, pn15[0]
+ pext p0.h, pn8[3]
+ pext p5.h, pn14[1]
+
+ pext p0.s, pn8[0]
+ PEXT P0.S, PN8[0]
+ pext p15.s, pn8[0]
+ pext p0.s, pn15[0]
+ pext p0.s, pn8[3]
+ pext p6.s, pn10[2]
+
+ pext p0.d, pn8[0]
+ PEXT P0.D, PN8[0]
+ pext p15.d, pn8[0]
+ pext p0.d, pn15[0]
+ pext p0.d, pn8[3]
+ pext p7.d, pn9[1]
+
+ pext { p0.b, p1.b }, pn8[0]
+ pext { p0.b - p1.b }, pn8[0]
+ PEXT { P0.B - P1.B }, PN8[0]
+ pext { p14.b - p15.b }, pn8[0]
+ pext { p15.b, p0.b }, pn8[0]
+ pext { p15.b - p0.b }, pn8[0]
+ pext { p0.b - p1.b }, pn15[0]
+ pext { p0.b - p1.b }, pn8[1]
+ pext { p7.b - p8.b }, pn12[0]
+
+ pext { p0.h, p1.h }, pn8[0]
+ pext { p0.h - p1.h }, pn8[0]
+ PEXT { P0.H - P1.H }, PN8[0]
+ pext { p14.h - p15.h }, pn8[0]
+ pext { p15.h, p0.h }, pn8[0]
+ pext { p15.h - p0.h }, pn8[0]
+ pext { p0.h - p1.h }, pn15[0]
+ pext { p0.h - p1.h }, pn8[1]
+ pext { p2.h - p3.h }, pn14[0]
+
+ pext { p0.s, p1.s }, pn8[0]
+ pext { p0.s - p1.s }, pn8[0]
+ PEXT { P0.S - P1.S }, PN8[0]
+ pext { p14.s - p15.s }, pn8[0]
+ pext { p15.s, p0.s }, pn8[0]
+ pext { p15.s - p0.s }, pn8[0]
+ pext { p0.s - p1.s }, pn15[0]
+ pext { p0.s - p1.s }, pn8[1]
+ pext { p5.s - p6.s }, pn13[0]
+
+ pext { p0.d, p1.d }, pn8[0]
+ pext { p0.d - p1.d }, pn8[0]
+ PEXT { P0.D - P1.D }, PN8[0]
+ pext { p14.d - p15.d }, pn8[0]
+ pext { p15.d, p0.d }, pn8[0]
+ pext { p15.d - p0.d }, pn8[0]
+ pext { p0.d - p1.d }, pn15[0]
+ pext { p0.d - p1.d }, pn8[1]
+ pext { p12.d - p13.d }, pn9[0]
+
+ ptrue pn8.b
+ ptrue pn11.b
+ ptrue pn15.b
+ ptrue pn8.h
+ ptrue pn9.h
+ ptrue pn15.h
+ ptrue pn8.s
+ ptrue pn14.s
+ ptrue pn15.s
+ ptrue pn8.d
+ ptrue pn12.d
+ ptrue pn15.d
diff --git a/gas/testsuite/gas/aarch64/sme2-7.d b/gas/testsuite/gas/aarch64/sme2-7.d
index 8c6fdc5d508d15b85917fba20f247ce70e508b85..3fcad5d84089bd2684558bfd39c3ffd8dc6790c1 100644
--- a/gas/testsuite/gas/aarch64/sme2-7.d
+++ b/gas/testsuite/gas/aarch64/sme2-7.d
@@ -1,4 +1,5 @@
#as: -march=armv8-a+sme2
+#as: -march=armv8-a+sve2p1
#objdump: -dr
[^:]+: file format .*
diff --git a/gas/testsuite/gas/aarch64/sve2-sme2-2.d b/gas/testsuite/gas/aarch64/sve2-sme2-2.d
index 9e60d1fd9b04cdc8ffce1838a3ec569e4f6add8e..6e9df901975d514707ecaa802f9890a0c7cdd478 100644
--- a/gas/testsuite/gas/aarch64/sve2-sme2-2.d
+++ b/gas/testsuite/gas/aarch64/sve2-sme2-2.d
@@ -1,4 +1,5 @@
#as: -march=armv8-a+sme2
+#as: -march=armv8-a+sve2p1
#objdump: -dr
[^:]+: file format .*
diff --git a/gas/testsuite/gas/aarch64/sve2-sme2-3.d b/gas/testsuite/gas/aarch64/sve2-sme2-3.d
index 2095aba0e659bcc9b7db8d7f81942e8196202739..1305d41ba33f2b86b621629e784ff137457521be 100644
--- a/gas/testsuite/gas/aarch64/sve2-sme2-3.d
+++ b/gas/testsuite/gas/aarch64/sve2-sme2-3.d
@@ -1,4 +1,5 @@
#as: -march=armv8-a+sme2
+#as: -march=armv8-a+sve2p1
#objdump: -dr
[^:]+: file format .*
diff --git a/gas/testsuite/gas/aarch64/sve2-sme2-4.d b/gas/testsuite/gas/aarch64/sve2-sme2-4.d
index b7bf3afbcad55921c39fd7412786a7c135d9d756..e3a5d16c103939dad1fb38e4445cde7f9f1ba9b6 100644
--- a/gas/testsuite/gas/aarch64/sve2-sme2-4.d
+++ b/gas/testsuite/gas/aarch64/sve2-sme2-4.d
@@ -1,4 +1,5 @@
#as: -march=armv8-a+sme2
+#as: -march=armv8-a+sve2p1
#objdump: -dr
[^:]+: file format .*
diff --git a/gas/testsuite/gas/aarch64/sve2-sme2-5.d b/gas/testsuite/gas/aarch64/sve2-sme2-5.d
index a1e5dc19a1cbce09888da4c29282215f0832954a..a73144ac21690b625a0476d2cad56b1b2dec0076 100644
--- a/gas/testsuite/gas/aarch64/sve2-sme2-5.d
+++ b/gas/testsuite/gas/aarch64/sve2-sme2-5.d
@@ -1,4 +1,5 @@
#as: -march=armv8-a+sme2
+#as: -march=armv8-a+sve2p1
#objdump: -dr
[^:]+: file format .*
diff --git a/gas/testsuite/gas/aarch64/sve2-sme2-6.d b/gas/testsuite/gas/aarch64/sve2-sme2-6.d
index 0d6f7c1eb3c7df9eede04b30983dfa5477614737..7aa5c3e9fe5719f52410c60e66ecc345da5afe64 100644
--- a/gas/testsuite/gas/aarch64/sve2-sme2-6.d
+++ b/gas/testsuite/gas/aarch64/sve2-sme2-6.d
@@ -1,4 +1,5 @@
#as: -march=armv8-a+sme2
+#as: -march=armv8-a+sve2p1
#objdump: -dr
[^:]+: file format .*
diff --git a/gas/testsuite/gas/aarch64/sve2-sme2-7.d b/gas/testsuite/gas/aarch64/sve2-sme2-7.d
index 2741ad57b04dd579d28a864fa5c8c477c6a09dd3..2c155dee41613368dec1523de5c22c7ae131056b 100644
--- a/gas/testsuite/gas/aarch64/sve2-sme2-7.d
+++ b/gas/testsuite/gas/aarch64/sve2-sme2-7.d
@@ -1,4 +1,5 @@
#as: -march=armv8-a+sme2
+#as: -march=armv8-a+sve2p1
#objdump: -dr
[^:]+: file format .*
diff --git a/gas/testsuite/gas/aarch64/sve2p1-1.d b/gas/testsuite/gas/aarch64/sve2p1-1.d
index f4c36b6551207be994834e4b8b55e976571b33ad..fa4ed8cf5326b72984f4817dcc8ff7abf2d8be49 100644
--- a/gas/testsuite/gas/aarch64/sve2p1-1.d
+++ b/gas/testsuite/gas/aarch64/sve2p1-1.d
@@ -1,5 +1,7 @@
#name: Test of SVE2.1 instructions
#as: -march=armv9.4-a
+#as: -march=armv8-a+sve2p1
+#as: -march=armv8-a+sme2p1
#objdump: -dr
[^:]+: file format .*
diff --git a/gas/testsuite/gas/aarch64/sve2p1-4.d b/gas/testsuite/gas/aarch64/sve2p1-4.d
index 390c63d8acf5352ae31c1e60dfa4228235905b13..94dbecb0927bae53e493ed3774e47e91373da8ca 100644
--- a/gas/testsuite/gas/aarch64/sve2p1-4.d
+++ b/gas/testsuite/gas/aarch64/sve2p1-4.d
@@ -1,5 +1,7 @@
#name: Test of SVE2.1 ld[1-4]q/st[1-4]q instructions.
#as: -march=armv9.4-a
+#as: -march=armv8-a+sve2p1
+#as: -march=armv8-a+sme2p1
#objdump: -dr
[^:]+: file format .*
@@ -8,15 +10,6 @@
[^:]+:
[^:]+:
-.*: c400a000 ld1q {z0.q}, p0/z, \[z0.d, x0\]
-.*: c400a01f ld1q {z31.q}, p0/z, \[z0.d, x0\]
-.*: c400bc00 ld1q {z0.q}, p7/z, \[z0.d, x0\]
-.*: c400a3e0 ld1q {z0.q}, p0/z, \[z31.d, x0\]
-.*: c41ea000 ld1q {z0.q}, p0/z, \[z0.d, x30\]
-.*: c41fa000 ld1q {z0.q}, p0/z, \[z0.d\]
-.*: c41fa000 ld1q {z0.q}, p0/z, \[z0.d\]
-.*: c41ebfff ld1q {z31.q}, p7/z, \[z31.d, x30\]
-.*: c404acef ld1q {z15.q}, p3/z, \[z7.d, x4\]
.*: a490e000 ld2q {z0.q-z1.q}, p0/z, \[x0\]
.*: a490e01f ld2q {z31.q-z0.q}, p0/z, \[x0\]
.*: a490fc00 ld2q {z0.q-z1.q}, p7/z, \[x0\]
@@ -79,15 +72,6 @@
.*: a5a4886a ld4q {z10.q-z13.q}, p2/z, \[x3, x4, lsl #4\]
.*: a5a4886a ld4q {z10.q-z13.q}, p2/z, \[x3, x4, lsl #4\]
.*: a5a48bea ld4q {z10.q-z13.q}, p2/z, \[sp, x4, lsl #4\]
-.*: e4202000 st1q {z0.q}, p0, \[z0.d, x0\]
-.*: e420201f st1q {z31.q}, p0, \[z0.d, x0\]
-.*: e4203c00 st1q {z0.q}, p7, \[z0.d, x0\]
-.*: e42023e0 st1q {z0.q}, p0, \[z31.d, x0\]
-.*: e43e2000 st1q {z0.q}, p0, \[z0.d, x30\]
-.*: e43f2000 st1q {z0.q}, p0, \[z0.d\]
-.*: e43f2000 st1q {z0.q}, p0, \[z0.d\]
-.*: e43e3fff st1q {z31.q}, p7, \[z31.d, x30\]
-.*: e4242cef st1q {z15.q}, p3, \[z7.d, x4\]
.*: e4400000 st2q {z0.q-z1.q}, p0, \[x0\]
.*: e440001f st2q {z31.q-z0.q}, p0, \[x0\]
.*: e4401c00 st2q {z0.q-z1.q}, p7, \[x0\]
diff --git a/gas/testsuite/gas/aarch64/sve2p1-4.s b/gas/testsuite/gas/aarch64/sve2p1-4.s
index 70d5044bcaa1eb56bc58b118f26745c1213ad88b..4a8f805d5dfe892dd00512927d160e9dfc967c3e 100644
--- a/gas/testsuite/gas/aarch64/sve2p1-4.s
+++ b/gas/testsuite/gas/aarch64/sve2p1-4.s
@@ -1,13 +1,3 @@
-ld1q { Z0.Q }, P0/Z, [Z0.D, x0]
-ld1q { Z31.Q }, P0/Z, [Z0.D, x0]
-ld1q { Z0.Q }, P7/Z, [Z0.D, x0]
-ld1q { Z0.Q }, P0/Z, [Z31.D, x0]
-ld1q { Z0.Q }, P0/Z, [Z0.D, x30]
-ld1q { Z0.Q }, P0/Z, [Z0.D, xzr]
-ld1q { Z0.Q }, P0/Z, [Z0.D]
-ld1q { Z31.Q }, P7/Z, [Z31.D, x30]
-ld1q { Z15.Q }, P3/Z, [Z7.D, x4]
-
ld2q {Z0.Q, Z1.Q}, p0/Z, [x0, #0, MUL VL]
ld2q {Z31.Q, Z0.Q}, p0/Z, [x0, #0, MUL VL]
ld2q {Z0.Q, Z1.Q}, p7/Z, [x0, #0, MUL VL]
@@ -76,16 +66,6 @@ ld4q {Z10.Q - Z11.Q - Z12.Q - Z13.Q}, p2/Z, [x3, x4, LSL #4]
ld4q {Z10.Q - Z13.Q}, p2/Z, [x3, x4, LSL #4]
ld4q {Z10.Q, Z11.Q, Z12.Q, Z13.Q}, p2/Z, [sp, x4, LSL #4]
-st1q { Z0.Q }, P0, [Z0.D, x0]
-st1q { Z31.Q }, P0, [Z0.D, x0]
-st1q { Z0.Q }, P7, [Z0.D, x0]
-st1q { Z0.Q }, P0, [Z31.D, x0]
-st1q { Z0.Q }, P0, [Z0.D, x30]
-st1q { Z0.Q }, P0, [Z0.D, xzr]
-st1q { Z0.Q }, P0, [Z0.D]
-st1q { Z31.Q }, P7, [Z31.D, x30]
-st1q { Z15.Q }, P3, [Z7.D, x4]
-
st2q {Z0.Q, Z1.Q}, p0, [x0, #0, MUL VL]
st2q {Z31.Q, Z0.Q}, p0, [x0, #0, MUL VL]
st2q {Z0.Q, Z1.Q}, p7, [x0, #0, MUL VL]
diff --git a/gas/testsuite/gas/aarch64/sve2p1-5.d b/gas/testsuite/gas/aarch64/sve2p1-5.d
index f581e345f58bd91c1eb4c61e15f3cfde2c209002..1c23eb0e71727fcd288415bc3bf63d46b0406ff7 100644
--- a/gas/testsuite/gas/aarch64/sve2p1-5.d
+++ b/gas/testsuite/gas/aarch64/sve2p1-5.d
@@ -1,5 +1,8 @@
#name: Test of SVE2.1 orqv instruction.
#as: -march=armv9.4-a
+#as: -march=armv8-a+sve2p1
+#as: -march=armv8-a+sme2p1
+#as: -march=armv9.4-a
#objdump: -dr
[^:]+: file format .*
diff --git a/gas/testsuite/gas/aarch64/sve2p1-6.d b/gas/testsuite/gas/aarch64/sve2p1-6.d
index 42d1ee41e9952fdc057fba71e84ed41e8bc6327c..388c33ef71158bfef256fd76d0602271e2f77b87 100644
--- a/gas/testsuite/gas/aarch64/sve2p1-6.d
+++ b/gas/testsuite/gas/aarch64/sve2p1-6.d
@@ -1,5 +1,7 @@
#name: Test of SVE2.1 tblq, tbxq, uzpq[1-2] and zipq[1-2] instruction.
#as: -march=armv9.4-a
+#as: -march=armv8-a+sve2p1
+#as: -march=armv8-a+sme2p1
#objdump: -dr
[^:]+: file format .*
diff --git a/gas/testsuite/gas/aarch64/sve2p1-7.d b/gas/testsuite/gas/aarch64/sve2p1-7.d
index 6bd1a22aaf49f337239fbcdd12b6d1104521bb39..d3358b4425a7287efea699966618de2987f24a68 100644
--- a/gas/testsuite/gas/aarch64/sve2p1-7.d
+++ b/gas/testsuite/gas/aarch64/sve2p1-7.d
@@ -1,5 +1,7 @@
#name: Test of SVE2.1 pmov instruction.
#as: -march=armv9.4-a
+#as: -march=armv8-a+sve2p1
+#as: -march=armv8-a+sme2p1
#objdump: -dr
[^:]+: file format .*
diff --git a/gas/testsuite/gas/aarch64/sve2p1-8.d b/gas/testsuite/gas/aarch64/sve2p1-8.d
new file mode 100644
index 0000000000000000000000000000000000000000..bb2ca4618ee049c5741fddb2340bcbd7d0811134
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-8.d
@@ -0,0 +1,29 @@
+#name: Test of SVE2.1 ld1q/st1q instructions.
+#as: -march=armv9.4-a
+#as: -march=armv8-a+sve2p1
+#objdump: -dr
+
+[^:]+: file format .*
+
+
+[^:]+:
+
+[^:]+:
+.*: c400a000 ld1q {z0.q}, p0/z, \[z0.d, x0\]
+.*: c400a01f ld1q {z31.q}, p0/z, \[z0.d, x0\]
+.*: c400bc00 ld1q {z0.q}, p7/z, \[z0.d, x0\]
+.*: c400a3e0 ld1q {z0.q}, p0/z, \[z31.d, x0\]
+.*: c41ea000 ld1q {z0.q}, p0/z, \[z0.d, x30\]
+.*: c41fa000 ld1q {z0.q}, p0/z, \[z0.d\]
+.*: c41fa000 ld1q {z0.q}, p0/z, \[z0.d\]
+.*: c41ebfff ld1q {z31.q}, p7/z, \[z31.d, x30\]
+.*: c404acef ld1q {z15.q}, p3/z, \[z7.d, x4\]
+.*: e4202000 st1q {z0.q}, p0, \[z0.d, x0\]
+.*: e420201f st1q {z31.q}, p0, \[z0.d, x0\]
+.*: e4203c00 st1q {z0.q}, p7, \[z0.d, x0\]
+.*: e42023e0 st1q {z0.q}, p0, \[z31.d, x0\]
+.*: e43e2000 st1q {z0.q}, p0, \[z0.d, x30\]
+.*: e43f2000 st1q {z0.q}, p0, \[z0.d\]
+.*: e43f2000 st1q {z0.q}, p0, \[z0.d\]
+.*: e43e3fff st1q {z31.q}, p7, \[z31.d, x30\]
+.*: e4242cef st1q {z15.q}, p3, \[z7.d, x4\]
diff --git a/gas/testsuite/gas/aarch64/sve2p1-8.s b/gas/testsuite/gas/aarch64/sve2p1-8.s
new file mode 100644
index 0000000000000000000000000000000000000000..0606238fb4a04a41e0ff2e630d32949afddd762b
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-8.s
@@ -0,0 +1,19 @@
+ld1q { Z0.Q }, P0/Z, [Z0.D, x0]
+ld1q { Z31.Q }, P0/Z, [Z0.D, x0]
+ld1q { Z0.Q }, P7/Z, [Z0.D, x0]
+ld1q { Z0.Q }, P0/Z, [Z31.D, x0]
+ld1q { Z0.Q }, P0/Z, [Z0.D, x30]
+ld1q { Z0.Q }, P0/Z, [Z0.D, xzr]
+ld1q { Z0.Q }, P0/Z, [Z0.D]
+ld1q { Z31.Q }, P7/Z, [Z31.D, x30]
+ld1q { Z15.Q }, P3/Z, [Z7.D, x4]
+
+st1q { Z0.Q }, P0, [Z0.D, x0]
+st1q { Z31.Q }, P0, [Z0.D, x0]
+st1q { Z0.Q }, P7, [Z0.D, x0]
+st1q { Z0.Q }, P0, [Z31.D, x0]
+st1q { Z0.Q }, P0, [Z0.D, x30]
+st1q { Z0.Q }, P0, [Z0.D, xzr]
+st1q { Z0.Q }, P0, [Z0.D]
+st1q { Z31.Q }, P7, [Z31.D, x30]
+st1q { Z15.Q }, P3, [Z7.D, x4]
diff --git a/gas/testsuite/gas/aarch64/sve2p1-9-invalid.d b/gas/testsuite/gas/aarch64/sve2p1-9-invalid.d
new file mode 100644
index 0000000000000000000000000000000000000000..ac49bc8a050de8e396d8eac13802f0903e7629c2
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-9-invalid.d
@@ -0,0 +1,2 @@
+#as: -march=armv9.4-a
+#error_output: sve2p1-9-invalid.l
diff --git a/gas/testsuite/gas/aarch64/sve2p1-9-invalid.l b/gas/testsuite/gas/aarch64/sve2p1-9-invalid.l
new file mode 100644
index 0000000000000000000000000000000000000000..d2739e7b187ee0e2951a58cc9aaf5a54362d712d
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-9-invalid.l
@@ -0,0 +1,73 @@
+.*: Assembler messages:
+.*: Error: p0-p7 expected at operand 2 -- `ld1d { ?z0.q ?},p8/z,\[x0\]'
+.*: Error: invalid base register at operand 3 -- `ld1d { ?z0.q ?},p0/z,\[x31\]'
+.*: Error: immediate offset out of range -8 to 7 at operand 3 -- `ld1d { ?z0.q ?},p0/z,\[x0,#8,mul vl\]'
+.*: Error: immediate offset out of range -8 to 7 at operand 3 -- `ld1d { ?z0.q ?},p0/z,\[x0,#-9,mul vl\]'
+.*: Error: operand mismatch -- `ld1d { ?z0.q ?},p0,\[x0\]'
+.*: Info: did you mean this\?
+.*: Info: ld1d { ?z0.q ?}, p0/z, \[x0\]
+.*: Error: p0-p7 expected at operand 2 -- `ld1d { ?z0.q ?},p8/z,\[x0,x0,LSL#3\]'
+.*: Error: invalid base register at operand 3 -- `ld1d { ?z0.q ?},p0/z,\[x31,x0,LSL#3\]'
+.*: Error: invalid base register at operand 3 -- `ld1d { ?z0.q ?},p0/z,\[xzr,x0,LSL#3\]'
+.*: Error: only 'MUL VL' is permitted at operand 3 -- `ld1d { ?z0.q ?},p0/z,\[x0,x31,LSL#3\]'
+.*: Error: index register xzr is not allowed at operand 3 -- `ld1d { ?z0.q ?},p0/z,\[x0,xzr,LSL#3\]'
+.*: Error: invalid offset register at operand 3 -- `ld1d { ?z0.q ?},p0/z,\[x0,sp,LSL#3\]'
+.*: Error: invalid addressing mode at operand 3 -- `ld1d { ?z0.q ?},p0/z,\[x0,x0\]'
+.*: Error: invalid addressing mode at operand 3 -- `ld1d { ?z0.q ?},p0/z,\[x0,x0,LSL#2\]'
+.*: Error: operand mismatch -- `ld1d { ?z0.q ?},p0,\[x0,x0,LSL#3\]'
+.*: Info: did you mean this\?
+.*: Info: ld1d { ?z0.q ?}, p0/z, \[x0, x0, lsl #3\]
+.*: Error: p0-p7 expected at operand 2 -- `ld1w { ?z0.q ?},p8/z,\[x0\]'
+.*: Error: invalid base register at operand 3 -- `ld1w { ?z0.q ?},p0/z,\[x31\]'
+.*: Error: immediate offset out of range -8 to 7 at operand 3 -- `ld1w { ?z0.q ?},p0/z,\[x0,#8,mul vl\]'
+.*: Error: immediate offset out of range -8 to 7 at operand 3 -- `ld1w { ?z0.q ?},p0/z,\[x0,#-9,mul vl\]'
+.*: Error: operand mismatch -- `ld1w { ?z0.q ?},p0,\[x0\]'
+.*: Info: did you mean this\?
+.*: Info: ld1w { ?z0.q ?}, p0/z, \[x0\]
+.*: Error: p0-p7 expected at operand 2 -- `ld1w { ?z0.q ?},p8/z,\[x0,x0,LSL#2\]'
+.*: Error: invalid base register at operand 3 -- `ld1w { ?z0.q ?},p0/z,\[x31,x0,LSL#2\]'
+.*: Error: invalid base register at operand 3 -- `ld1w { ?z0.q ?},p0/z,\[xzr,x0,LSL#2\]'
+.*: Error: only 'MUL VL' is permitted at operand 3 -- `ld1w { ?z0.q ?},p0/z,\[x0,x31,LSL#2\]'
+.*: Error: index register xzr is not allowed at operand 3 -- `ld1w { ?z0.q ?},p0/z,\[x0,xzr,LSL#2\]'
+.*: Error: invalid offset register at operand 3 -- `ld1w { ?z0.q ?},p0/z,\[x0,sp,LSL#2\]'
+.*: Error: invalid addressing mode at operand 3 -- `ld1w { ?z0.q ?},p0/z,\[x0,x0\]'
+.*: Error: invalid addressing mode at operand 3 -- `ld1w { ?z0.q ?},p0/z,\[x0,x0,LSL#3\]'
+.*: Error: operand mismatch -- `ld1w { ?z0.q ?},p0,\[x0,x0,LSL#2\]'
+.*: Info: did you mean this\?
+.*: Info: ld1w { ?z0.q ?}, p0/z, \[x0, x0, lsl #2\]
+.*: Error: p0-p7 expected at operand 2 -- `st1d { ?z0.q ?},p8,\[x0\]'
+.*: Error: invalid base register at operand 3 -- `st1d { ?z0.q ?},p0,\[x31\]'
+.*: Error: immediate offset out of range -8 to 7 at operand 3 -- `st1d { ?z0.q ?},p0,\[x0,#8,mul vl\]'
+.*: Error: immediate offset out of range -8 to 7 at operand 3 -- `st1d { ?z0.q ?},p0,\[x0,#-9,mul vl\]'
+.*: Error: operand mismatch -- `st1d { ?z0.q ?},p0/z,\[x0\]'
+.*: Info: did you mean this\?
+.*: Info: st1d { ?z0.q ?}, p0, \[x0\]
+.*: Error: p0-p7 expected at operand 2 -- `st1d { ?z0.q ?},p8,\[x0,x0,LSL#3\]'
+.*: Error: invalid base register at operand 3 -- `st1d { ?z0.q ?},p0,\[x31,x0,LSL#3\]'
+.*: Error: invalid base register at operand 3 -- `st1d { ?z0.q ?},p0,\[xzr,x0,LSL#3\]'
+.*: Error: only 'MUL VL' is permitted at operand 3 -- `st1d { ?z0.q ?},p0,\[x0,x31,LSL#3\]'
+.*: Error: index register xzr is not allowed at operand 3 -- `st1d { ?z0.q ?},p0,\[x0,xzr,LSL#3\]'
+.*: Error: invalid offset register at operand 3 -- `st1d { ?z0.q ?},p0,\[x0,sp,LSL#3\]'
+.*: Error: invalid addressing mode at operand 3 -- `st1d { ?z0.q ?},p0,\[x0,x0\]'
+.*: Error: invalid addressing mode at operand 3 -- `st1d { ?z0.q ?},p0,\[x0,x0,LSL#2\]'
+.*: Error: operand mismatch -- `st1d { ?z0.q ?},p0/z,\[x0,x0,LSL#3\]'
+.*: Info: did you mean this\?
+.*: Info: st1d { ?z0.q ?}, p0, \[x0, x0, lsl #3\]
+.*: Error: p0-p7 expected at operand 2 -- `st1w { ?z0.q ?},p8,\[x0\]'
+.*: Error: invalid base register at operand 3 -- `st1w { ?z0.q ?},p0,\[x31\]'
+.*: Error: immediate offset out of range -8 to 7 at operand 3 -- `st1w { ?z0.q ?},p0,\[x0,#8,mul vl\]'
+.*: Error: immediate offset out of range -8 to 7 at operand 3 -- `st1w { ?z0.q ?},p0,\[x0,#-9,mul vl\]'
+.*: Error: operand mismatch -- `st1w { ?z0.q ?},p0/z,\[x0\]'
+.*: Info: did you mean this\?
+.*: Info: st1w { ?z0.q ?}, p0, \[x0\]
+.*: Error: p0-p7 expected at operand 2 -- `st1w { ?z0.q ?},p8,\[x0,x0,LSL#2\]'
+.*: Error: invalid base register at operand 3 -- `st1w { ?z0.q ?},p0,\[x31,x0,LSL#2\]'
+.*: Error: invalid base register at operand 3 -- `st1w { ?z0.q ?},p0,\[xzr,x0,LSL#2\]'
+.*: Error: only 'MUL VL' is permitted at operand 3 -- `st1w { ?z0.q ?},p0,\[x0,x31,LSL#2\]'
+.*: Error: index register xzr is not allowed at operand 3 -- `st1w { ?z0.q ?},p0,\[x0,xzr,LSL#2\]'
+.*: Error: invalid offset register at operand 3 -- `st1w { ?z0.q ?},p0,\[x0,sp,LSL#2\]'
+.*: Error: invalid addressing mode at operand 3 -- `st1w { ?z0.q ?},p0,\[x0,x0\]'
+.*: Error: invalid addressing mode at operand 3 -- `st1w { ?z0.q ?},p0,\[x0,x0,LSL#3\]'
+.*: Error: operand mismatch -- `st1w { ?z0.q ?},p0/z,\[x0,x0,LSL#2\]'
+.*: Info: did you mean this\?
+.*: Info: st1w { ?z0.q ?}, p0, \[x0, x0, lsl #2\]
diff --git a/gas/testsuite/gas/aarch64/sve2p1-9-invalid.s b/gas/testsuite/gas/aarch64/sve2p1-9-invalid.s
new file mode 100644
index 0000000000000000000000000000000000000000..757d0b1b8f2d2eadcb774ce191812bc6c709cb71
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-9-invalid.s
@@ -0,0 +1,69 @@
+ld1d { z0.q }, p8/z, [x0]
+ld1d { z0.q }, p0/z, [x31]
+ld1d { z0.q }, p0/z, [x0, #8, mul vl]
+ld1d { z0.q }, p0/z, [x0, #-9, mul vl]
+// FIXME: This form is incorrectly accepted:
+ld1d { z0.q }, p0/z, [x0, #0]
+ld1d { z0.q }, p0, [x0]
+
+ld1d { z0.q }, p8/z, [x0, x0, LSL #3]
+ld1d { z0.q }, p0/z, [x31, x0, LSL #3]
+ld1d { z0.q }, p0/z, [xzr, x0, LSL #3]
+// FIXME: confusing error message:
+ld1d { z0.q }, p0/z, [x0, x31, LSL #3]
+ld1d { z0.q }, p0/z, [x0, xzr, LSL #3]
+ld1d { z0.q }, p0/z, [x0, sp, LSL #3]
+ld1d { z0.q }, p0/z, [x0, x0]
+ld1d { z0.q }, p0/z, [x0, x0, LSL #2]
+ld1d { z0.q }, p0, [x0, x0, LSL #3]
+
+ld1w { z0.q }, p8/z, [x0]
+ld1w { z0.q }, p0/z, [x31]
+ld1w { z0.q }, p0/z, [x0, #8, mul vl]
+ld1w { z0.q }, p0/z, [x0, #-9, mul vl]
+ld1w { z0.q }, p0/z, [x0, #0]
+ld1w { z0.q }, p0, [x0]
+
+ld1w { z0.q }, p8/z, [x0, x0, LSL #2]
+ld1w { z0.q }, p0/z, [x31, x0, LSL #2]
+ld1w { z0.q }, p0/z, [xzr, x0, LSL #2]
+ld1w { z0.q }, p0/z, [x0, x31, LSL #2]
+ld1w { z0.q }, p0/z, [x0, xzr, LSL #2]
+ld1w { z0.q }, p0/z, [x0, sp, LSL #2]
+ld1w { z0.q }, p0/z, [x0, x0]
+ld1w { z0.q }, p0/z, [x0, x0, LSL #3]
+ld1w { z0.q }, p0, [x0, x0, LSL #2]
+
+st1d { z0.q }, p8, [x0]
+st1d { z0.q }, p0, [x31]
+st1d { z0.q }, p0, [x0, #8, mul vl]
+st1d { z0.q }, p0, [x0, #-9, mul vl]
+st1d { z0.q }, p0, [x0, #0]
+st1d { z0.q }, p0/z, [x0]
+
+st1d { z0.q }, p8, [x0, x0, LSL #3]
+st1d { z0.q }, p0, [x31, x0, LSL #3]
+st1d { z0.q }, p0, [xzr, x0, LSL #3]
+st1d { z0.q }, p0, [x0, x31, LSL #3]
+st1d { z0.q }, p0, [x0, xzr, LSL #3]
+st1d { z0.q }, p0, [x0, sp, LSL #3]
+st1d { z0.q }, p0, [x0, x0]
+st1d { z0.q }, p0, [x0, x0, LSL #2]
+st1d { z0.q }, p0/z, [x0, x0, LSL #3]
+
+st1w { z0.q }, p8, [x0]
+st1w { z0.q }, p0, [x31]
+st1w { z0.q }, p0, [x0, #8, mul vl]
+st1w { z0.q }, p0, [x0, #-9, mul vl]
+st1w { z0.q }, p0, [x0, #0]
+st1w { z0.q }, p0/z, [x0]
+
+st1w { z0.q }, p8, [x0, x0, LSL #2]
+st1w { z0.q }, p0, [x31, x0, LSL #2]
+st1w { z0.q }, p0, [xzr, x0, LSL #2]
+st1w { z0.q }, p0, [x0, x31, LSL #2]
+st1w { z0.q }, p0, [x0, xzr, LSL #2]
+st1w { z0.q }, p0, [x0, sp, LSL #2]
+st1w { z0.q }, p0, [x0, x0]
+st1w { z0.q }, p0, [x0, x0, LSL #3]
+st1w { z0.q }, p0/z, [x0, x0, LSL #2]
diff --git a/gas/testsuite/gas/aarch64/sve2p1-9.d b/gas/testsuite/gas/aarch64/sve2p1-9.d
new file mode 100644
index 0000000000000000000000000000000000000000..9a5c0d28b19d39dc7db7c48334ebbc0aabd512cf
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-9.d
@@ -0,0 +1,75 @@
+#name: Test of SVE2.1 ld1q/st1q instructions.
+#as: -march=armv9.4-a
+#as: -march=armv8-a+sve2p1
+#objdump: -dr
+
+[^:]+: file format .*
+
+
+[^:]+:
+
+[^:]+:
+.*: a5902000 ld1d {z0.q}, p0/z, \[x0\]
+.*: a5902000 ld1d {z0.q}, p0/z, \[x0\]
+.*: a5972000 ld1d {z0.q}, p0/z, \[x0, #7, mul vl\]
+.*: a5982000 ld1d {z0.q}, p0/z, \[x0, #-8, mul vl\]
+.*: a59f2000 ld1d {z0.q}, p0/z, \[x0, #-1, mul vl\]
+.*: a590201f ld1d {z31.q}, p0/z, \[x0\]
+.*: a5903c00 ld1d {z0.q}, p7/z, \[x0\]
+.*: a59023c0 ld1d {z0.q}, p0/z, \[x30\]
+.*: a59023e0 ld1d {z0.q}, p0/z, \[sp\]
+.*: a5808000 ld1d {z0.q}, p0/z, \[x0, x0, lsl #3\]
+.*: a580801f ld1d {z31.q}, p0/z, \[x0, x0, lsl #3\]
+.*: a5809c00 ld1d {z0.q}, p7/z, \[x0, x0, lsl #3\]
+.*: a58083c0 ld1d {z0.q}, p0/z, \[x30, x0, lsl #3\]
+.*: a58083e0 ld1d {z0.q}, p0/z, \[sp, x0, lsl #3\]
+.*: a58f8000 ld1d {z0.q}, p0/z, \[x0, x15, lsl #3\]
+.*: a59e8000 ld1d {z0.q}, p0/z, \[x0, x30, lsl #3\]
+.*: a5102000 ld1w {z0.q}, p0/z, \[x0\]
+.*: a5102000 ld1w {z0.q}, p0/z, \[x0\]
+.*: a5172000 ld1w {z0.q}, p0/z, \[x0, #7, mul vl\]
+.*: a5182000 ld1w {z0.q}, p0/z, \[x0, #-8, mul vl\]
+.*: a51f2000 ld1w {z0.q}, p0/z, \[x0, #-1, mul vl\]
+.*: a510201f ld1w {z31.q}, p0/z, \[x0\]
+.*: a5103c00 ld1w {z0.q}, p7/z, \[x0\]
+.*: a51023c0 ld1w {z0.q}, p0/z, \[x30\]
+.*: a51023e0 ld1w {z0.q}, p0/z, \[sp\]
+.*: a5008000 ld1w {z0.q}, p0/z, \[x0, x0, lsl #2\]
+.*: a500801f ld1w {z31.q}, p0/z, \[x0, x0, lsl #2\]
+.*: a5009c00 ld1w {z0.q}, p7/z, \[x0, x0, lsl #2\]
+.*: a50083c0 ld1w {z0.q}, p0/z, \[x30, x0, lsl #2\]
+.*: a50083e0 ld1w {z0.q}, p0/z, \[sp, x0, lsl #2\]
+.*: a50f8000 ld1w {z0.q}, p0/z, \[x0, x15, lsl #2\]
+.*: a51e8000 ld1w {z0.q}, p0/z, \[x0, x30, lsl #2\]
+.*: e5c0e000 st1d {z0.q}, p0, \[x0\]
+.*: e5c0e000 st1d {z0.q}, p0, \[x0\]
+.*: e5c7e000 st1d {z0.q}, p0, \[x0, #7, mul vl\]
+.*: e5c8e000 st1d {z0.q}, p0, \[x0, #-8, mul vl\]
+.*: e5cfe000 st1d {z0.q}, p0, \[x0, #-1, mul vl\]
+.*: e5c0e01f st1d {z31.q}, p0, \[x0\]
+.*: e5c0fc00 st1d {z0.q}, p7, \[x0\]
+.*: e5c0e3c0 st1d {z0.q}, p0, \[x30\]
+.*: e5c0e3e0 st1d {z0.q}, p0, \[sp\]
+.*: e5c04000 st1d {z0.q}, p0, \[x0, x0, lsl #3\]
+.*: e5c0401f st1d {z31.q}, p0, \[x0, x0, lsl #3\]
+.*: e5c05c00 st1d {z0.q}, p7, \[x0, x0, lsl #3\]
+.*: e5c043c0 st1d {z0.q}, p0, \[x30, x0, lsl #3\]
+.*: e5c043e0 st1d {z0.q}, p0, \[sp, x0, lsl #3\]
+.*: e5cf4000 st1d {z0.q}, p0, \[x0, x15, lsl #3\]
+.*: e5de4000 st1d {z0.q}, p0, \[x0, x30, lsl #3\]
+.*: e500e000 st1w {z0.q}, p0, \[x0\]
+.*: e500e000 st1w {z0.q}, p0, \[x0\]
+.*: e507e000 st1w {z0.q}, p0, \[x0, #7, mul vl\]
+.*: e508e000 st1w {z0.q}, p0, \[x0, #-8, mul vl\]
+.*: e50fe000 st1w {z0.q}, p0, \[x0, #-1, mul vl\]
+.*: e500e01f st1w {z31.q}, p0, \[x0\]
+.*: e500fc00 st1w {z0.q}, p7, \[x0\]
+.*: e500e3c0 st1w {z0.q}, p0, \[x30\]
+.*: e500e3e0 st1w {z0.q}, p0, \[sp\]
+.*: e5004000 st1w {z0.q}, p0, \[x0, x0, lsl #2\]
+.*: e500401f st1w {z31.q}, p0, \[x0, x0, lsl #2\]
+.*: e5005c00 st1w {z0.q}, p7, \[x0, x0, lsl #2\]
+.*: e50043c0 st1w {z0.q}, p0, \[x30, x0, lsl #2\]
+.*: e50043e0 st1w {z0.q}, p0, \[sp, x0, lsl #2\]
+.*: e50f4000 st1w {z0.q}, p0, \[x0, x15, lsl #2\]
+.*: e51e4000 st1w {z0.q}, p0, \[x0, x30, lsl #2\]
diff --git a/gas/testsuite/gas/aarch64/sve2p1-9.s b/gas/testsuite/gas/aarch64/sve2p1-9.s
new file mode 100644
index 0000000000000000000000000000000000000000..d5ba3288d6c9d182e71dce882a70d008d622f954
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-9.s
@@ -0,0 +1,71 @@
+ld1d { z0.q }, p0/z, [x0]
+ld1d { z0.q }, p0/z, [x0, #0, mul vl]
+ld1d { z0.q }, p0/z, [x0, #7, mul vl]
+ld1d { z0.q }, p0/z, [x0, #-8, mul vl]
+ld1d { z0.q }, p0/z, [x0, #-1, mul vl]
+ld1d { z31.q }, p0/z, [x0]
+ld1d { z0.q }, p7/z, [x0]
+ld1d { z0.q }, p0/z, [x30]
+ld1d { z0.q }, p0/z, [sp]
+
+ld1d { z0.q }, p0/z, [x0, x0, LSL #3]
+ld1d { z31.q }, p0/z, [x0, x0, LSL #3]
+ld1d { z0.q }, p7/z, [x0, x0, LSL #3]
+ld1d { z0.q }, p0/z, [x30, x0, LSL #3]
+ld1d { z0.q }, p0/z, [sp, x0, LSL #3]
+ld1d { z0.q }, p0/z, [x0, x15, LSL #3]
+ld1d { z0.q }, p0/z, [x0, x30, LSL #3]
+
+ld1w { z0.q }, p0/z, [x0]
+ld1w { z0.q }, p0/z, [x0, #0, mul vl]
+ld1w { z0.q }, p0/z, [x0, #7, mul vl]
+ld1w { z0.q }, p0/z, [x0, #-8, mul vl]
+ld1w { z0.q }, p0/z, [x0, #-1, mul vl]
+ld1w { z31.q }, p0/z, [x0]
+ld1w { z0.q }, p7/z, [x0]
+ld1w { z0.q }, p0/z, [x30]
+ld1w { z0.q }, p0/z, [sp]
+
+ld1w { z0.q }, p0/z, [x0, x0, LSL #2]
+ld1w { z31.q }, p0/z, [x0, x0, LSL #2]
+ld1w { z0.q }, p7/z, [x0, x0, LSL #2]
+ld1w { z0.q }, p0/z, [x30, x0, LSL #2]
+ld1w { z0.q }, p0/z, [sp, x0, LSL #2]
+ld1w { z0.q }, p0/z, [x0, x15, LSL #2]
+ld1w { z0.q }, p0/z, [x0, x30, LSL #2]
+
+st1d { z0.q }, p0, [x0]
+st1d { z0.q }, p0, [x0, #0, mul vl]
+st1d { z0.q }, p0, [x0, #7, mul vl]
+st1d { z0.q }, p0, [x0, #-8, mul VL]
+st1d { z0.q }, p0, [x0, #-1, MUL vl]
+st1d { z31.q }, p0, [x0]
+st1d { z0.q }, p7, [x0]
+st1d { z0.q }, p0, [x30]
+st1d { z0.q }, p0, [sp]
+
+st1d { z0.q }, p0, [x0, x0, lsl #3]
+st1d { z31.q }, p0, [x0, x0, LSL #3]
+st1d { z0.q }, p7, [x0, x0, LSL #3]
+st1d { z0.q }, p0, [x30, x0, LSL #3]
+st1d { z0.q }, p0, [sp, x0, LSL #3]
+st1d { z0.q }, p0, [x0, x15, LSL #3]
+st1d { z0.q }, p0, [x0, x30, LSL #3]
+
+st1w { z0.q }, p0, [x0]
+st1w { z0.q }, p0, [x0, #0, mul vl]
+st1w { z0.q }, p0, [x0, #7, mul vl]
+st1w { z0.q }, p0, [x0, #-8, mul VL]
+st1w { z0.q }, p0, [x0, #-1, MUL vl]
+st1w { z31.q }, p0, [x0]
+st1w { z0.q }, p7, [x0]
+st1w { z0.q }, p0, [x30]
+st1w { z0.q }, p0, [sp]
+
+st1w { z0.q }, p0, [x0, x0, lsl #2]
+st1w { z31.q }, p0, [x0, x0, LSL #2]
+st1w { z0.q }, p7, [x0, x0, LSL #2]
+st1w { z0.q }, p0, [x30, x0, LSL #2]
+st1w { z0.q }, p0, [sp, x0, LSL #2]
+st1w { z0.q }, p0, [x0, x15, LSL #2]
+st1w { z0.q }, p0, [x0, x30, LSL #2]
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 755373557fc6e03da9d828ad4cbf4ca15541adff..dfe3f05820ab156bb7d5fc5c86dd6cbaba91065c 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -268,6 +268,8 @@ enum aarch64_feature_bit {
AARCH64_FEATURE_SVE_B16B16,
/* SME non-widening BFloat16 instructions. */
AARCH64_FEATURE_SME_B16B16,
+ /* Armv9.5-A processors. */
+ AARCH64_FEATURE_V9_5A,
/* Virtual features. These are used to gate instructions that are enabled
by either of two (or more) sets of command line flags. */
@@ -279,8 +281,12 @@ enum aarch64_feature_bit {
AARCH64_FEATURE_FP8DOT2_SVE,
/* +sme-f16f16 or +sme-f8f16 */
AARCH64_FEATURE_SME_F16F16_F8F16,
- /* Armv9.5-A processors. */
- AARCH64_FEATURE_V9_5A,
+ /* +sve2p1 or +sme */
+ AARCH64_FEATURE_SVE2p1_SME,
+ /* +sve2p1 or +sme2 */
+ AARCH64_FEATURE_SVE2p1_SME2,
+ /* +sve2p1 or +sme2p1 */
+ AARCH64_FEATURE_SVE2p1_SME2p1,
AARCH64_NUM_FEATURES
};
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index 07e12f6d252c601a3e3963ce0a179078e4455f4e..eb1411378777098edd6dcf010567c5c6e7cbad01 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -271,7 +271,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000x000101x00xxxxxxxxxxxxxx
luti4. */
- return 3480;
+ return 3488;
}
else
{
@@ -310,7 +310,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000xx01101x00xxxxxxxxxxxxxx
luti4. */
- return 3481;
+ return 3489;
}
else
{
@@ -542,7 +542,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000010011x1xxxx00xxxxxxxxxx
movt. */
- return 3482;
+ return 3490;
}
}
else
@@ -1366,7 +1366,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx000000101xxxxxxxxxxxxxxxx00xxx
fmopa. */
- return 3548;
+ return 3556;
}
else
{
@@ -1374,7 +1374,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx000000101xxxxxxxxxxxxxxxx01xxx
fmopa. */
- return 3547;
+ return 3555;
}
}
else
@@ -1722,7 +1722,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010001xxxx1xx0xxxxx1000xxx
fmlall. */
- return 3541;
+ return 3549;
}
}
}
@@ -1772,7 +1772,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010001xxxx1xx1xxxxx100xxxx
fdot. */
- return 3526;
+ return 3534;
}
}
}
@@ -2223,7 +2223,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011001xxxxxxx0xxxxxx100xxx
fmlall. */
- return 3540;
+ return 3548;
}
}
}
@@ -2328,7 +2328,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011001xxxxxxx1xxxxxx10xxxx
fmlal. */
- return 3533;
+ return 3541;
}
}
}
@@ -2512,7 +2512,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011001xxxxxxx1xxxxxx11xxxx
fmlal. */
- return 3532;
+ return 3540;
}
}
}
@@ -2554,7 +2554,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010100xxxxxxxxxxxxxxxx0xxx
fmlall. */
- return 3539;
+ return 3547;
}
else
{
@@ -2922,7 +2922,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx000010101xxxx0xx0xxxxxx111xxx
fdot. */
- return 3519;
+ return 3527;
}
else
{
@@ -2991,7 +2991,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx000010101xxxx1xx0xxxxxx001xxx
fdot. */
- return 3520;
+ return 3528;
}
else
{
@@ -3070,7 +3070,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011100xxxxxxx0xxxxxxx0xxxx
fmlal. */
- return 3531;
+ return 3539;
}
else
{
@@ -3125,7 +3125,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011101xxxx0xx01xxxxx00xxxx
fvdotb. */
- return 3550;
+ return 3558;
}
else
{
@@ -3143,7 +3143,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011101xxxxxxx0xxxxxx10xxxx
fdot. */
- return 3525;
+ return 3533;
}
}
}
@@ -3217,7 +3217,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011101xxxxxxx1xxxxxx10xxxx
fvdot. */
- return 3549;
+ return 3557;
}
}
}
@@ -3297,7 +3297,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx000001110xxxxx0xx01xxxxxx1xxxx
fvdott. */
- return 3551;
+ return 3559;
}
else
{
@@ -3496,7 +3496,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx00xx000xxxx10000x
fmlall. */
- return 3545;
+ return 3553;
}
else
{
@@ -3504,7 +3504,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx10xx000xxxx10000x
fmlall. */
- return 3546;
+ return 3554;
}
}
}
@@ -3559,7 +3559,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx10xxxx0xx000xxxxx00x1x
fmlall. */
- return 3543;
+ return 3551;
}
else
{
@@ -3567,7 +3567,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx000xxxxx00x1x
fmlall. */
- return 3544;
+ return 3552;
}
}
}
@@ -3621,7 +3621,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx00xx100xxxx100xxx
fdot. */
- return 3529;
+ return 3537;
}
else
{
@@ -3629,7 +3629,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx10xx100xxxx100xxx
fdot. */
- return 3530;
+ return 3538;
}
}
}
@@ -3691,7 +3691,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001101xxxx00xx010xxxx1000xx
fmlal. */
- return 3537;
+ return 3545;
}
else
{
@@ -3699,7 +3699,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001101xxxx10xx010xxxx1000xx
fmlal. */
- return 3538;
+ return 3546;
}
}
}
@@ -3754,7 +3754,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx10xxxx0xx010xxxxx001xx
fmlal. */
- return 3535;
+ return 3543;
}
else
{
@@ -3762,7 +3762,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx010xxxxx001xx
fmlal. */
- return 3536;
+ return 3544;
}
}
}
@@ -3831,7 +3831,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx001xxxxx000xx
fmlall. */
- return 3542;
+ return 3550;
}
}
else
@@ -3914,7 +3914,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx011xxxxx00xxx
fmlal. */
- return 3534;
+ return 3542;
}
}
else
@@ -3960,7 +3960,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011010x1x00xx111xxxxx00xxx
fadd. */
- return 3483;
+ return 3491;
}
else
{
@@ -3990,7 +3990,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011010x1x10xx111xxxxx00xxx
fadd. */
- return 3484;
+ return 3492;
}
else
{
@@ -4146,7 +4146,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx00xx100xxxx110xxx
fdot. */
- return 3523;
+ return 3531;
}
else
{
@@ -4154,7 +4154,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx10xx100xxxx110xxx
fdot. */
- return 3524;
+ return 3532;
}
}
}
@@ -4449,7 +4449,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000010010xxxx0xx100xxxxx01xxx
fdot. */
- return 3527;
+ return 3535;
}
else
{
@@ -4457,7 +4457,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000010011xxxx0xx100xxxxx01xxx
fdot. */
- return 3528;
+ return 3536;
}
}
else
@@ -4793,7 +4793,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011010x1x00xx111xxxxx01xxx
fsub. */
- return 3485;
+ return 3493;
}
else
{
@@ -4823,7 +4823,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011010x1x10xx111xxxxx01xxx
fsub. */
- return 3486;
+ return 3494;
}
else
{
@@ -4919,7 +4919,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000010010xxxx0xx100xxxxx11xxx
fdot. */
- return 3521;
+ return 3529;
}
else
{
@@ -4927,7 +4927,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000010011xxxx0xx100xxxxx11xxx
fdot. */
- return 3522;
+ return 3530;
}
}
else
@@ -5502,7 +5502,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xxxxx101000xx1x0xxxx0
fscale. */
- return 3457;
+ return 3465;
}
}
else
@@ -5694,7 +5694,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001x0100100111000xxxx0xxxxx
fcvt. */
- return 3454;
+ return 3462;
}
else
{
@@ -5702,7 +5702,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001x1100100111000xxxx0xxxxx
bfcvt. */
- return 3449;
+ return 3457;
}
}
else
@@ -5711,7 +5711,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx110100111000xxxx0xxxxx
fcvt. */
- return 3455;
+ return 3463;
}
}
else
@@ -5740,7 +5740,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xx100111000xxxx1xxxxx
fcvtn. */
- return 3456;
+ return 3464;
}
}
}
@@ -5823,7 +5823,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000010010x110111000xxxxxxxxx0
f1cvt. */
- return 3450;
+ return 3458;
}
else
{
@@ -5831,7 +5831,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011010x110111000xxxxxxxxx0
f2cvt. */
- return 3451;
+ return 3459;
}
}
else
@@ -5842,7 +5842,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000010110x110111000xxxxxxxxx0
bf1cvt. */
- return 3445;
+ return 3453;
}
else
{
@@ -5850,7 +5850,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011110x110111000xxxxxxxxx0
bf2cvt. */
- return 3446;
+ return 3454;
}
}
}
@@ -5885,7 +5885,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001001xxx10111000xxxxxxxxx1
f1cvtl. */
- return 3452;
+ return 3460;
}
else
{
@@ -5893,7 +5893,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001101xxx10111000xxxxxxxxx1
f2cvtl. */
- return 3453;
+ return 3461;
}
}
else
@@ -5904,7 +5904,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001011xxx10111000xxxxxxxxx1
bf1cvtl. */
- return 3447;
+ return 3455;
}
else
{
@@ -5912,7 +5912,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001111xxx10111000xxxxxxxxx1
bf2cvtl. */
- return 3448;
+ return 3456;
}
}
}
@@ -6181,7 +6181,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xxxxx1x1100xx100xxxx0
fscale. */
- return 3459;
+ return 3467;
}
}
else
@@ -6357,7 +6357,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xxxxx1x1010xx100xxxx0
fscale. */
- return 3458;
+ return 3466;
}
else
{
@@ -6365,7 +6365,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xxxxx1x1110xx100xxxx0
fscale. */
- return 3460;
+ return 3468;
}
}
}
@@ -11533,7 +11533,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x11010000xxxxxxx1xxxxxxxxxxxxx
addpt. */
- return 3461;
+ return 3469;
}
else
{
@@ -11541,7 +11541,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1x11010000xxxxxxx1xxxxxxxxxxxxx
subpt. */
- return 3462;
+ return 3470;
}
}
}
@@ -12459,7 +12459,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxx1011x11xxxxx0xxxxxxxxxxxxxxx
maddpt. */
- return 3463;
+ return 3471;
}
else
{
@@ -12467,7 +12467,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxx1011x11xxxxx1xxxxxxxxxxxxxxx
msubpt. */
- return 3464;
+ return 3472;
}
}
}
@@ -12552,7 +12552,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx000100000xxxxxxxxxxxxx
addpt. */
- return 3465;
+ return 3473;
}
else
{
@@ -12659,7 +12659,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx000101000xxxxxxxxxxxxx
subpt. */
- return 3467;
+ return 3475;
}
else
{
@@ -12864,7 +12864,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx1xxxxx000010xxxxxxxxxx
addpt. */
- return 3466;
+ return 3474;
}
else
{
@@ -12905,7 +12905,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx1xxxxx000011xxxxxxxxxx
subpt. */
- return 3468;
+ return 3476;
}
else
{
@@ -14563,7 +14563,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx110100xxxxxxxxxx
mlapt. */
- return 3470;
+ return 3478;
}
}
else
@@ -14593,7 +14593,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx110110xxxxxxxxxx
madpt. */
- return 3469;
+ return 3477;
}
}
}
@@ -15747,7 +15747,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
110001x0x00xxxxx101xxxxxxxxxxxxx
ld1q. */
- return 3406;
+ return 3414;
}
else
{
@@ -17279,7 +17279,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0x00xxxxx000xxxxxxxxxxxxx
st3q. */
- return 3415;
+ return 3423;
}
else
{
@@ -17289,7 +17289,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0010xxxxx000xxxxxxxxxxxxx
st2q. */
- return 3414;
+ return 3422;
}
else
{
@@ -17297,7 +17297,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0110xxxxx000xxxxxxxxxxxxx
st4q. */
- return 3416;
+ return 3424;
}
}
}
@@ -17963,7 +17963,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x0xx01xxxx111xxxxxxxxxxxxx
ld2q. */
- return 3407;
+ return 3415;
}
}
}
@@ -18099,7 +18099,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x0xx1xxxxx100xxxxxxxxxxxxx
ld2q. */
- return 3410;
+ return 3418;
}
}
else
@@ -18244,7 +18244,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x00x1xxxxx000xxxxxxxxxxxxx
st2q. */
- return 3417;
+ return 3425;
}
}
else
@@ -18287,7 +18287,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0101xxxxx000xxxxxxxxxxxxx
st3q. */
- return 3418;
+ return 3426;
}
}
else
@@ -18328,7 +18328,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0111xxxxx000xxxxxxxxxxxxx
st4q. */
- return 3419;
+ return 3427;
}
}
}
@@ -18357,7 +18357,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0001xxxxx0100x1xxxxxxxxxx
fdot. */
- return 3506;
+ return 3514;
}
}
else
@@ -18366,7 +18366,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0001xxxxx0101xxxxxxxxxxxx
fmlalb. */
- return 3508;
+ return 3516;
}
}
else
@@ -18407,7 +18407,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0101xxxxx0101xxxxxxxxxxxx
fmlalt. */
- return 3518;
+ return 3526;
}
}
else
@@ -18440,7 +18440,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0011xxxxx010xx1xxxxxxxxxx
fdot. */
- return 3504;
+ return 3512;
}
}
else
@@ -18511,7 +18511,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx100010xxxxxxxxxx
fmlallbb. */
- return 3509;
+ return 3517;
}
}
else
@@ -18520,7 +18520,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1000x1xxxxxxxxxx
fdot. */
- return 3505;
+ return 3513;
}
}
else
@@ -18529,7 +18529,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1100xxxxxxxxxxxx
fmlallbb. */
- return 3510;
+ return 3518;
}
}
else
@@ -18538,7 +18538,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1x01xxxxxxxxxxxx
fmlallbt. */
- return 3511;
+ return 3519;
}
}
else
@@ -18565,7 +18565,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0101xxxxx100010xxxxxxxxxx
fmlalb. */
- return 3507;
+ return 3515;
}
}
else
@@ -18583,7 +18583,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0101xxxxx1100xxxxxxxxxxxx
fmlalltb. */
- return 3514;
+ return 3522;
}
}
else
@@ -18592,7 +18592,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0101xxxxx1x01xxxxxxxxxxxx
fmlalt. */
- return 3517;
+ return 3525;
}
}
else
@@ -18625,7 +18625,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0011xxxxx100xx1xxxxxxxxxx
fdot. */
- return 3503;
+ return 3511;
}
}
else
@@ -18634,7 +18634,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0011xxxxx110xxxxxxxxxxxxx
fmlallbt. */
- return 3512;
+ return 3520;
}
}
else
@@ -18666,7 +18666,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0111xxxxx110xxxxxxxxxxxxx
fmlalltt. */
- return 3516;
+ return 3524;
}
}
else
@@ -18965,7 +18965,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0xx1xxxxx001xxxxxxxxxxxxx
st1q. */
- return 3413;
+ return 3421;
}
}
else
@@ -18980,7 +18980,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1010xxxxxxxxxxxx
fmlalltb. */
- return 3513;
+ return 3521;
}
else
{
@@ -18988,7 +18988,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1011xxxxxxxxxxxx
fmlalltt. */
- return 3515;
+ return 3523;
}
}
else
@@ -21443,7 +21443,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x1xx1xxxxx101100xxxxxxxxxx
luti2. */
- return 3475;
+ return 3483;
}
}
else
@@ -21452,7 +21452,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x1xx1xxxxx101x10xxxxxxxxxx
luti2. */
- return 3476;
+ return 3484;
}
}
else
@@ -21465,7 +21465,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x1xx1xxxxx101001xxxxxxxxxx
luti4. */
- return 3477;
+ return 3485;
}
else
{
@@ -21473,7 +21473,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x1xx1xxxxx101101xxxxxxxxxx
luti4. */
- return 3478;
+ return 3486;
}
}
else
@@ -21482,7 +21482,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x1xx1xxxxx101x11xxxxxxxxxx
luti4. */
- return 3479;
+ return 3487;
}
}
}
@@ -22363,21 +22363,43 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- if (((word >> 23) & 0x1) == 0)
+ if (((word >> 20) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 101001x10x0xxxxx001xxxxxxxxxxxxx
- ld1rqw. */
- return 1613;
+ if (((word >> 23) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 101001x10x00xxxx001xxxxxxxxxxxxx
+ ld1rqw. */
+ return 1613;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 101001x11x00xxxx001xxxxxxxxxxxxx
+ ld1rqd. */
+ return 1609;
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 101001x11x0xxxxx001xxxxxxxxxxxxx
- ld1rqd. */
- return 1609;
+ if (((word >> 23) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 101001x10x01xxxx001xxxxxxxxxxxxx
+ ld1w. */
+ return 3408;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 101001x11x01xxxx001xxxxxxxxxxxxx
+ ld1d. */
+ return 3406;
+ }
}
}
}
@@ -22433,7 +22455,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx001000001x00xxxxxxxxxx
f1cvt. */
- return 3437;
+ return 3445;
}
else
{
@@ -22441,7 +22463,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx001000001x10xxxxxxxxxx
bf1cvt. */
- return 3433;
+ return 3441;
}
}
else
@@ -22452,7 +22474,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx001000001x01xxxxxxxxxx
f2cvt. */
- return 3438;
+ return 3446;
}
else
{
@@ -22460,7 +22482,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx001000001x11xxxxxxxxxx
bf2cvt. */
- return 3434;
+ return 3442;
}
}
}
@@ -22505,7 +22527,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1010001x00xxxxxxxxxx
fcvtn. */
- return 3442;
+ return 3450;
}
else
{
@@ -22513,7 +22535,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1010001x10xxxxxxxxxx
bfcvtn. */
- return 3441;
+ return 3449;
}
}
else
@@ -22524,7 +22546,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1010001x01xxxxxxxxxx
fcvtnb. */
- return 3443;
+ return 3451;
}
else
{
@@ -22532,7 +22554,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1010001x11xxxxxxxxxx
fcvtnt. */
- return 3444;
+ return 3452;
}
}
}
@@ -22593,7 +22615,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1001001x00xxxxxxxxxx
f1cvtlt. */
- return 3439;
+ return 3447;
}
else
{
@@ -22601,7 +22623,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1001001x10xxxxxxxxxx
bf1cvtlt. */
- return 3435;
+ return 3443;
}
}
else
@@ -22612,7 +22634,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1001001x01xxxxxxxxxx
f2cvtlt. */
- return 3440;
+ return 3448;
}
else
{
@@ -22620,7 +22642,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1001001x11xxxxxxxxxx
bf2cvtlt. */
- return 3436;
+ return 3444;
}
}
}
@@ -23438,21 +23460,43 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 22) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 111001x1x0xxxxxx010xxxxxxxxxxxxx
- str. */
- return 2010;
+ if (((word >> 23) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 111001x100xxxxxx010xxxxxxxxxxxxx
+ st1w. */
+ return 3413;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 111001x110xxxxxx010xxxxxxxxxxxxx
+ str. */
+ return 2010;
+ }
}
else
{
if (((word >> 21) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 111001x1x10xxxxx010xxxxxxxxxxxxx
- st1w. */
- return 1968;
+ if (((word >> 23) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 111001x1010xxxxx010xxxxxxxxxxxxx
+ st1w. */
+ return 1968;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 111001x1110xxxxx010xxxxxxxxxxxxx
+ st1d. */
+ return 3411;
+ }
}
else
{
@@ -23607,21 +23651,43 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 13) & 0x1) == 0)
{
- if (((word >> 4) & 0x1) == 0)
+ if (((word >> 31) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x01001x1xx0xxxxx100xxxxxxxx0xxxx
- cmpeq. */
- return 1384;
+ if (((word >> 4) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 001001x1xx0xxxxx100xxxxxxxx0xxxx
+ cmpeq. */
+ return 1384;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 001001x1xx0xxxxx100xxxxxxxx1xxxx
+ cmpne. */
+ return 1407;
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x01001x1xx0xxxxx100xxxxxxxx1xxxx
- cmpne. */
- return 1407;
+ if (((word >> 23) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 101001x10x0xxxxx100xxxxxxxxxxxxx
+ ld1w. */
+ return 3409;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 101001x11x0xxxxx100xxxxxxxxxxxxx
+ ld1d. */
+ return 3407;
+ }
}
}
else
@@ -23946,7 +24012,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x10x01xxxx111xxxxxxxxxxxxx
ld3q. */
- return 3408;
+ return 3416;
}
else
{
@@ -23954,7 +24020,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x11x01xxxx111xxxxxxxxxxxxx
ld4q. */
- return 3409;
+ return 3417;
}
}
}
@@ -24842,11 +24908,33 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 20) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 111001x1xx00xxxx111xxxxxxxxxxxxx
- st1w. */
- return 1973;
+ if (((word >> 22) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 111001x1x000xxxx111xxxxxxxxxxxxx
+ st1w. */
+ return 3412;
+ }
+ else
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 111001x10100xxxx111xxxxxxxxxxxxx
+ st1w. */
+ return 1973;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 111001x11100xxxx111xxxxxxxxxxxxx
+ st1d. */
+ return 3410;
+ }
+ }
}
else
{
@@ -25127,7 +25215,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x10x1xxxxx100xxxxxxxxxxxxx
ld3q. */
- return 3411;
+ return 3419;
}
else
{
@@ -25135,7 +25223,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x11x1xxxxx100xxxxxxxxxxxxx
ld4q. */
- return 3412;
+ return 3420;
}
}
else
@@ -27200,7 +27288,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110100xxxxxxxx100xxxxxxxxxx
luti2. */
- return 3471;
+ return 3479;
}
}
}
@@ -27214,7 +27302,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110010xxxxxxxx000xxxxxxxxxx
luti4. */
- return 3473;
+ return 3481;
}
else
{
@@ -27222,7 +27310,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110010xxxxxxxx100xxxxxxxxxx
luti4. */
- return 3474;
+ return 3482;
}
}
else
@@ -27231,7 +27319,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110110xxxxxxxxx00xxxxxxxxxx
luti2. */
- return 3472;
+ return 3480;
}
}
}
@@ -27347,7 +27435,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00001110x00xxxxxx10001xxxxxxxxxx
fmlallbb. */
- return 3495;
+ return 3503;
}
else
{
@@ -27355,7 +27443,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01001110x00xxxxxx10001xxxxxxxxxx
fmlalltb. */
- return 3497;
+ return 3505;
}
}
else
@@ -27366,7 +27454,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00001110x10xxxxxx10001xxxxxxxxxx
fmlallbt. */
- return 3496;
+ return 3504;
}
else
{
@@ -27374,7 +27462,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01001110x10xxxxxx10001xxxxxxxxxx
fmlalltt. */
- return 3498;
+ return 3506;
}
}
}
@@ -27462,7 +27550,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00001110x00xxxxxx11101xxxxxxxxxx
fcvtn. */
- return 3428;
+ return 3436;
}
else
{
@@ -27470,7 +27558,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01001110x00xxxxxx11101xxxxxxxxxx
fcvtn2. */
- return 3429;
+ return 3437;
}
}
else
@@ -27479,7 +27567,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110x10xxxxxx11101xxxxxxxxxx
fcvtn. */
- return 3430;
+ return 3438;
}
}
}
@@ -27622,7 +27710,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110x00xxxxxx11111xxxxxxxxxx
fdot. */
- return 3487;
+ return 3495;
}
else
{
@@ -27632,7 +27720,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110010xxxxxx11111xxxxxxxxxx
fdot. */
- return 3489;
+ return 3497;
}
else
{
@@ -27642,7 +27730,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00001110110xxxxxx11111xxxxxxxxxx
fmlalb. */
- return 3491;
+ return 3499;
}
else
{
@@ -27650,7 +27738,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01001110110xxxxxx11111xxxxxxxxxx
fmlalt. */
- return 3492;
+ return 3500;
}
}
}
@@ -27924,7 +28012,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx101110110xxxxx0x1111xxxxxxxxxx
fscale. */
- return 3431;
+ return 3439;
}
}
}
@@ -29316,7 +29404,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0101110001xxxx1011110xxxxxxxxxx
f1cvtl. */
- return 3424;
+ return 3432;
}
else
{
@@ -29324,7 +29412,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1101110001xxxx1011110xxxxxxxxxx
f1cvtl2. */
- return 3425;
+ return 3433;
}
}
else
@@ -29335,7 +29423,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0101110101xxxx1011110xxxxxxxxxx
bf1cvtl. */
- return 3420;
+ return 3428;
}
else
{
@@ -29343,7 +29431,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1101110101xxxx1011110xxxxxxxxxx
bf1cvtl2. */
- return 3421;
+ return 3429;
}
}
}
@@ -29357,7 +29445,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0101110011xxxx1011110xxxxxxxxxx
f2cvtl. */
- return 3426;
+ return 3434;
}
else
{
@@ -29365,7 +29453,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1101110011xxxx1011110xxxxxxxxxx
f2cvtl2. */
- return 3427;
+ return 3435;
}
}
else
@@ -29376,7 +29464,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0101110111xxxx1011110xxxxxxxxxx
bf2cvtl. */
- return 3422;
+ return 3430;
}
else
{
@@ -29384,7 +29472,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1101110111xxxx1011110xxxxxxxxxx
bf2cvtl2. */
- return 3423;
+ return 3431;
}
}
}
@@ -31383,7 +31471,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx1011101x1xxxxx111111xxxxxxxxxx
fscale. */
- return 3432;
+ return 3440;
}
}
}
@@ -33099,7 +33187,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx00111100xxxxxx0000x0xxxxxxxxxx
fdot. */
- return 3488;
+ return 3496;
}
else
{
@@ -33129,7 +33217,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx00111101xxxxxx0000x0xxxxxxxxxx
fdot. */
- return 3490;
+ return 3498;
}
else
{
@@ -33139,7 +33227,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x000111111xxxxxx0000x0xxxxxxxxxx
fmlalb. */
- return 3493;
+ return 3501;
}
else
{
@@ -33147,7 +33235,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x100111111xxxxxx0000x0xxxxxxxxxx
fmlalt. */
- return 3494;
+ return 3502;
}
}
}
@@ -33689,7 +33777,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x010111100xxxxxx1000x0xxxxxxxxxx
fmlallbb. */
- return 3499;
+ return 3507;
}
else
{
@@ -33697,7 +33785,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x110111100xxxxxx1000x0xxxxxxxxxx
fmlalltb. */
- return 3501;
+ return 3509;
}
}
else
@@ -33728,7 +33816,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0101111x1xxxxxx1000x0xxxxxxxxxx
fmlallbt. */
- return 3500;
+ return 3508;
}
else
{
@@ -33736,7 +33824,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1101111x1xxxxxx1000x0xxxxxxxxxx
fmlalltt. */
- return 3502;
+ return 3510;
}
}
}
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 16fa47b1a6187e450c73d8c6667cd1678b5ca76d..70cd3ffb6e0000835f88fbdffdf53ff8cb40974c 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2863,6 +2863,12 @@ static const aarch64_feature_set aarch64_feature_sme_f16f16_f8f16 =
AARCH64_FEATURES (2, SME_F16F16_F8F16, SME2);
static const aarch64_feature_set aarch64_feature_sme_f16f16 =
AARCH64_FEATURES (2, SME_F16F16, SME2);
+static const aarch64_feature_set aarch64_feature_sve2p1_sme =
+ AARCH64_FEATURES (2, SVE2p1_SME, SVE);
+static const aarch64_feature_set aarch64_feature_sve2p1_sme2 =
+ AARCH64_FEATURES (2, SVE2p1_SME2, SVE);
+static const aarch64_feature_set aarch64_feature_sve2p1_sme2p1 =
+ AARCH64_FEATURES (2, SVE2p1_SME2p1, SVE);
#define CORE &aarch64_feature_v8
#define FP &aarch64_feature_fp
@@ -2954,6 +2960,9 @@ static const aarch64_feature_set aarch64_feature_sme_f16f16 =
#define SME_F8F16 &aarch64_feature_sme_f8f16
#define SME_F16F16_F8F16 &aarch64_feature_sme_f16f16_f8f16
#define SME_F16F16 &aarch64_feature_sme_f16f16
+#define SVE2p1_SME &aarch64_feature_sve2p1_sme
+#define SVE2p1_SME2 &aarch64_feature_sve2p1_sme2
+#define SVE2p1_SME2p1 &aarch64_feature_sve2p1_sme2p1
#define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL }
@@ -3190,6 +3199,24 @@ static const aarch64_feature_set aarch64_feature_sme_f16f16 =
#define SME_F16F16_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
{ NAME, OPCODE, MASK, CLASS, OP, SME_F16F16, OPS, QUALS, \
FLAGS | F_STRICT, 0, TIED, NULL }
+#define SVE2p1_SME_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
+ { NAME, OPCODE, MASK, CLASS, OP, SVE2p1_SME, OPS, QUALS, \
+ F_STRICT | FLAGS, 0, TIED, NULL }
+#define SVE2p1_SME_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \
+ { NAME, OPCODE, MASK, CLASS, OP, SVE2p1_SME, OPS, QUALS, \
+ F_STRICT | FLAGS, CONSTRAINTS, TIED, NULL }
+#define SVE2p1_SME2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
+ { NAME, OPCODE, MASK, CLASS, OP, SVE2p1_SME2, OPS, QUALS, \
+ F_STRICT | FLAGS, 0, TIED, NULL }
+#define SVE2p1_SME2_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \
+ { NAME, OPCODE, MASK, CLASS, OP, SVE2p1_SME2, OPS, QUALS, \
+ F_STRICT | FLAGS, CONSTRAINTS, TIED, NULL }
+#define SVE2p1_SME2p1_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
+ { NAME, OPCODE, MASK, CLASS, OP, SVE2p1_SME2p1, OPS, QUALS, \
+ F_STRICT | FLAGS, 0, TIED, NULL }
+#define SVE2p1_SME2p1_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \
+ { NAME, OPCODE, MASK, CLASS, OP, SVE2p1_SME2p1, OPS, QUALS, \
+ F_STRICT | FLAGS, CONSTRAINTS, TIED, NULL }
#define MOPS_CPY_OP1_OP2_PME_INSN(NAME, OPCODE, MASK, FLAGS, CONSTRAINTS) \
MOPS_INSN (NAME, OPCODE, MASK, 0, \
@@ -5825,42 +5852,42 @@ const struct aarch64_opcode aarch64_opcode_table[] =
SME_INSN ("ldr", 0xe1000000, 0xffff9c10, sme_ldr, 0, OP2 (SME_ZA_array_off4, SME_ADDR_RI_U4xVL), {}, 0, 1),
SME_INSN ("str", 0xe1200000, 0xffff9c10, sme_str, 0, OP2 (SME_ZA_array_off4, SME_ADDR_RI_U4xVL), {}, 0, 1),
- SME_INSNC ("revd", 0x52e8000, 0xffffe000, sme_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_QMQ, 0, C_SCAN_MOVPRFX, 0),
- SME_INSNC ("sclamp", 0x4400c000, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, C_SCAN_MOVPRFX, 0),
- SME_INSNC ("uclamp", 0x4400c400, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, C_SCAN_MOVPRFX, 0),
- SME_INSN ("psel", 0x25204000, 0xff20c210, sme_psel, 0, OP3 (SVE_Pd, SVE_Pg4_10, SME_PnT_Wm_imm), OP_SVE_NN_BHSD, 0, 0),
- SME_INSN ("psel", 0x25204000, 0xff20c210, sme_psel, 0, OP3 (SVE_PNd, SVE_PNg4_10, SME_PnT_Wm_imm), OP_SVE_NN_BHSD, 0, 0),
+ SVE2p1_SME_INSNC ("revd", 0x052e8000, 0xffffe000, sme_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_QMQ, 0, C_SCAN_MOVPRFX, 0),
+ SVE2p1_SME_INSNC ("sclamp", 0x4400c000, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, C_SCAN_MOVPRFX, 0),
+ SVE2p1_SME_INSNC ("uclamp", 0x4400c400, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, C_SCAN_MOVPRFX, 0),
+ SVE2p1_SME_INSN ("psel", 0x25204000, 0xff20c210, sme_psel, 0, OP3 (SVE_Pd, SVE_Pg4_10, SME_PnT_Wm_imm), OP_SVE_NN_BHSD, 0, 0),
+ SVE2p1_SME_INSN ("psel", 0x25204000, 0xff20c210, sme_psel, 0, OP3 (SVE_PNd, SVE_PNg4_10, SME_PnT_Wm_imm), OP_SVE_NN_BHSD, 0, 0),
/* Added in SME2, but part of the prefetch hint space and available
without special command-line flags. */
CORE_INSN ("rprfm", 0xf8a04818, 0xffe04c18, sme_misc, 0, OP3 (RPRFMOP, Rm, SIMD_ADDR_SIMPLE), OP_SVE_UXU, 0),
/* SME2 extensions to SVE2. */
- SME2_INSNC ("bfmlslb", 0x64e06000, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
- SME2_INSNC ("bfmlslb", 0x64e0a000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
- SME2_INSNC ("bfmlslt", 0x64e06400, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
- SME2_INSNC ("bfmlslt", 0x64e0a400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
- SME2_INSNC ("fdot", 0x64204000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_19_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
- SME2_INSNC ("fdot", 0x64208000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
- SME2_INSNC ("fclamp", 0x64202400, 0xff20fc00, sme_size_22_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD, 0, C_SCAN_MOVPRFX, 0),
- SME2_INSNC ("sdot", 0x4480c800, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_19_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
- SME2_INSNC ("sdot", 0x4400c800, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
- SME2_INSN ("sqcvtn", 0x45314000, 0xfffffc20, sve_misc, 0, OP2 (SVE_Zd, SME_Znx2), OP_SVE_HS, 0, 0),
- SME2_INSN ("sqcvtun", 0x45315000, 0xfffffc20, sve_misc, 0, OP2 (SVE_Zd, SME_Znx2), OP_SVE_HS, 0, 0),
- SME2_INSN ("sqrshrn", 0x45b02800, 0xfff0fc20, sme_misc, 0, OP3 (SVE_Zd, SME_Znx2, SME_SHRIMM4), OP_SVE_HSU, 0, 0),
- SME2_INSN ("sqrshrun", 0x45b00800, 0xfff0fc20, sme_misc, 0, OP3 (SVE_Zd, SME_Znx2, SME_SHRIMM4), OP_SVE_HSU, 0, 0),
- SME2_INSNC ("udot", 0x4480cc00, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_19_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
- SME2_INSNC ("udot", 0x4400cc00, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
- SME2_INSN ("uqcvtn", 0x45314800, 0xfffffc20, sve_misc, 0, OP2 (SVE_Zd, SME_Znx2), OP_SVE_HS, 0, 0),
- SME2_INSN ("uqrshrn", 0x45b03800, 0xfff0fc20, sme_misc, 0, OP3 (SVE_Zd, SME_Znx2, SME_SHRIMM4), OP_SVE_HSU, 0, 0),
- SME2_INSN ("whilege", 0x25205010, 0xff20fc11, sme_size_22, 0, OP3 (SME_Pdx2, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0),
- SME2_INSN ("whilegt", 0x25205011, 0xff20fc11, sme_size_22, 0, OP3 (SME_Pdx2, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0),
- SME2_INSN ("whilehi", 0x25205811, 0xff20fc11, sme_size_22, 0, OP3 (SME_Pdx2, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0),
- SME2_INSN ("whilehs", 0x25205810, 0xff20fc11, sme_size_22, 0, OP3 (SME_Pdx2, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0),
- SME2_INSN ("whilele", 0x25205411, 0xff20fc11, sme_size_22, 0, OP3 (SME_Pdx2, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0),
- SME2_INSN ("whilelo", 0x25205c10, 0xff20fc11, sme_size_22, 0, OP3 (SME_Pdx2, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0),
- SME2_INSN ("whilels", 0x25205c11, 0xff20fc11, sme_size_22, 0, OP3 (SME_Pdx2, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0),
- SME2_INSN ("whilelt", 0x25205410, 0xff20fc11, sme_size_22, 0, OP3 (SME_Pdx2, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0),
+ SVE2p1_SME2_INSNC ("bfmlslb", 0x64e06000, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
+ SVE2p1_SME2_INSNC ("bfmlslb", 0x64e0a000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
+ SVE2p1_SME2_INSNC ("bfmlslt", 0x64e06400, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
+ SVE2p1_SME2_INSNC ("bfmlslt", 0x64e0a400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
+ SVE2p1_SME2_INSNC ("fdot", 0x64204000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_19_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
+ SVE2p1_SME2_INSNC ("fdot", 0x64208000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
+ SVE2p1_SME2_INSNC ("fclamp", 0x64202400, 0xff20fc00, sme_size_22_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD, 0, C_SCAN_MOVPRFX, 0),
+ SVE2p1_SME2_INSNC ("sdot", 0x4480c800, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_19_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
+ SVE2p1_SME2_INSNC ("sdot", 0x4400c800, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
+ SVE2p1_SME2_INSN ("sqcvtn", 0x45314000, 0xfffffc20, sve_misc, 0, OP2 (SVE_Zd, SME_Znx2), OP_SVE_HS, 0, 0),
+ SVE2p1_SME2_INSN ("sqcvtun", 0x45315000, 0xfffffc20, sve_misc, 0, OP2 (SVE_Zd, SME_Znx2), OP_SVE_HS, 0, 0),
+ SVE2p1_SME2_INSN ("sqrshrn", 0x45b02800, 0xfff0fc20, sme_misc, 0, OP3 (SVE_Zd, SME_Znx2, SME_SHRIMM4), OP_SVE_HSU, 0, 0),
+ SVE2p1_SME2_INSN ("sqrshrun", 0x45b00800, 0xfff0fc20, sme_misc, 0, OP3 (SVE_Zd, SME_Znx2, SME_SHRIMM4), OP_SVE_HSU, 0, 0),
+ SVE2p1_SME2_INSNC ("udot", 0x4480cc00, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_19_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
+ SVE2p1_SME2_INSNC ("udot", 0x4400cc00, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
+ SVE2p1_SME2_INSN ("uqcvtn", 0x45314800, 0xfffffc20, sve_misc, 0, OP2 (SVE_Zd, SME_Znx2), OP_SVE_HS, 0, 0),
+ SVE2p1_SME2_INSN ("uqrshrn", 0x45b03800, 0xfff0fc20, sme_misc, 0, OP3 (SVE_Zd, SME_Znx2, SME_SHRIMM4), OP_SVE_HSU, 0, 0),
+ SVE2p1_SME2_INSN ("whilege", 0x25205010, 0xff20fc11, sme_size_22, 0, OP3 (SME_Pdx2, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0),
+ SVE2p1_SME2_INSN ("whilegt", 0x25205011, 0xff20fc11, sme_size_22, 0, OP3 (SME_Pdx2, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0),
+ SVE2p1_SME2_INSN ("whilehi", 0x25205811, 0xff20fc11, sme_size_22, 0, OP3 (SME_Pdx2, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0),
+ SVE2p1_SME2_INSN ("whilehs", 0x25205810, 0xff20fc11, sme_size_22, 0, OP3 (SME_Pdx2, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0),
+ SVE2p1_SME2_INSN ("whilele", 0x25205411, 0xff20fc11, sme_size_22, 0, OP3 (SME_Pdx2, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0),
+ SVE2p1_SME2_INSN ("whilelo", 0x25205c10, 0xff20fc11, sme_size_22, 0, OP3 (SME_Pdx2, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0),
+ SVE2p1_SME2_INSN ("whilels", 0x25205c11, 0xff20fc11, sme_size_22, 0, OP3 (SME_Pdx2, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0),
+ SVE2p1_SME2_INSN ("whilelt", 0x25205410, 0xff20fc11, sme_size_22, 0, OP3 (SME_Pdx2, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0),
/* SME2 extensions to SME. */
SME2_INSN ("add", 0xc1a01c10, 0xffbf9c38, sme_int_sd, 0, OP2 (SME_ZA_array_off3_0, SME_Znx2), OP_SVE_VVV_SD, F_OD (2), 0),
@@ -5898,7 +5925,7 @@ const struct aarch64_opcode aarch64_opcode_table[] =
SME2_INSN ("bfvdot", 0xc1500018, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX2), OP_SVE_SHH, F_OD (2), 0),
SME2_INSN ("bmopa", 0x80800008, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_SMMSS, 0, 0),
SME2_INSN ("bmops", 0x80800018, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_SMMSS, 0, 0),
- SME2_INSN ("cntp", 0x25208200, 0xff3ffa00, sme_size_22, 0, OP3 (Rd, SME_PNn, SME_VLxN_10), OP_SVE_XV_BHSD, 0, 0),
+ SVE2p1_SME2_INSN ("cntp", 0x25208200, 0xff3ffa00, sme_size_22, 0, OP3 (Rd, SME_PNn, SME_VLxN_10), OP_SVE_XV_BHSD, 0, 0),
SME2_INSN ("fadd", 0xc1a01c00, 0xffbf9c38, sme_fp_sd, 0, OP2 (SME_ZA_array_off3_0, SME_Znx2), OP_SVE_VVV_SD, F_OD (2), 0),
SME2_INSN ("fadd", 0xc1a11c00, 0xffbf9c78, sme_fp_sd, 0, OP2 (SME_ZA_array_off3_0, SME_Znx4), OP_SVE_VVV_SD, F_OD (4), 0),
SME2_INSN ("fclamp", 0xc120c000, 0xff20fc01, sme_size_22_hsd, 0, OP3 (SME_Zdnx2, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD, 0, 0),
@@ -5970,68 +5997,68 @@ const struct aarch64_opcode aarch64_opcode_table[] =
SME2_INSN ("fsub", 0xc1a01c08, 0xffbf9c38, sme_fp_sd, 0, OP2 (SME_ZA_array_off3_0, SME_Znx2), OP_SVE_VVV_SD, F_OD (2), 0),
SME2_INSN ("fsub", 0xc1a11c08, 0xffbf9c78, sme_fp_sd, 0, OP2 (SME_ZA_array_off3_0, SME_Znx4), OP_SVE_VVV_SD, F_OD (4), 0),
SME2_INSN ("fvdot", 0xc1500008, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX2), OP_SVE_SHH, F_OD (2), 0),
- SME2_INSN ("ld1b", 0xa0400000, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_BZU, 0, 0),
- SME2_INSN ("ld1b", 0xa0408000, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_BZU, 0, 0),
+ SVE2p1_SME2_INSN ("ld1b", 0xa0400000, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_BZU, 0, 0),
+ SVE2p1_SME2_INSN ("ld1b", 0xa0408000, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_BZU, 0, 0),
SME2_INSN ("ld1b", 0xa1400000, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_BZU, 0, 0),
SME2_INSN ("ld1b", 0xa1408000, 0xfff0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_BZU, 0, 0),
- SME2_INSN ("ld1b", 0xa0000000, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR), OP_SVE_BZU, 0, 0),
- SME2_INSN ("ld1b", 0xa0008000, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR), OP_SVE_BZU, 0, 0),
+ SVE2p1_SME2_INSN ("ld1b", 0xa0000000, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR), OP_SVE_BZU, 0, 0),
+ SVE2p1_SME2_INSN ("ld1b", 0xa0008000, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR), OP_SVE_BZU, 0, 0),
SME2_INSN ("ld1b", 0xa1000000, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR), OP_SVE_BZU, 0, 0),
SME2_INSN ("ld1b", 0xa1008000, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR), OP_SVE_BZU, 0, 0),
- SME2_INSN ("ld1d", 0xa0406000, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_DZU, 0, 0),
- SME2_INSN ("ld1d", 0xa040e000, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_DZU, 0, 0),
+ SVE2p1_SME2_INSN ("ld1d", 0xa0406000, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_DZU, 0, 0),
+ SVE2p1_SME2_INSN ("ld1d", 0xa040e000, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_DZU, 0, 0),
SME2_INSN ("ld1d", 0xa1406000, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_DZU, 0, 0),
SME2_INSN ("ld1d", 0xa140e000, 0xfff0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_DZU, 0, 0),
- SME2_INSN ("ld1d", 0xa0006000, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DZU, 0, 0),
- SME2_INSN ("ld1d", 0xa000e000, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DZU, 0, 0),
+ SVE2p1_SME2_INSN ("ld1d", 0xa0006000, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DZU, 0, 0),
+ SVE2p1_SME2_INSN ("ld1d", 0xa000e000, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DZU, 0, 0),
SME2_INSN ("ld1d", 0xa1006000, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DZU, 0, 0),
SME2_INSN ("ld1d", 0xa100e000, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DZU, 0, 0),
- SME2_INSN ("ld1h", 0xa0402000, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_HZU, 0, 0),
- SME2_INSN ("ld1h", 0xa040a000, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_HZU, 0, 0),
+ SVE2p1_SME2_INSN ("ld1h", 0xa0402000, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_HZU, 0, 0),
+ SVE2p1_SME2_INSN ("ld1h", 0xa040a000, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_HZU, 0, 0),
SME2_INSN ("ld1h", 0xa1402000, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_HZU, 0, 0),
SME2_INSN ("ld1h", 0xa140a000, 0xfff0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_HZU, 0, 0),
- SME2_INSN ("ld1h", 0xa0002000, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HZU, 0, 0),
- SME2_INSN ("ld1h", 0xa000a000, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HZU, 0, 0),
+ SVE2p1_SME2_INSN ("ld1h", 0xa0002000, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HZU, 0, 0),
+ SVE2p1_SME2_INSN ("ld1h", 0xa000a000, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HZU, 0, 0),
SME2_INSN ("ld1h", 0xa1002000, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HZU, 0, 0),
SME2_INSN ("ld1h", 0xa100a000, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HZU, 0, 0),
- SME2_INSN ("ld1w", 0xa0404000, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_SZU, 0, 0),
- SME2_INSN ("ld1w", 0xa040c000, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_SZU, 0, 0),
+ SVE2p1_SME2_INSN ("ld1w", 0xa0404000, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_SZU, 0, 0),
+ SVE2p1_SME2_INSN ("ld1w", 0xa040c000, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_SZU, 0, 0),
SME2_INSN ("ld1w", 0xa1404000, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_SZU, 0, 0),
SME2_INSN ("ld1w", 0xa140c000, 0xfff0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_SZU, 0, 0),
- SME2_INSN ("ld1w", 0xa0004000, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SZU, 0, 0),
- SME2_INSN ("ld1w", 0xa000c000, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SZU, 0, 0),
+ SVE2p1_SME2_INSN ("ld1w", 0xa0004000, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SZU, 0, 0),
+ SVE2p1_SME2_INSN ("ld1w", 0xa000c000, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SZU, 0, 0),
SME2_INSN ("ld1w", 0xa1004000, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SZU, 0, 0),
SME2_INSN ("ld1w", 0xa100c000, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SZU, 0, 0),
- SME2_INSN ("ldnt1b", 0xa0400001, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_BZU, 0, 0),
- SME2_INSN ("ldnt1b", 0xa0408001, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_BZU, 0, 0),
+ SVE2p1_SME2_INSN ("ldnt1b", 0xa0400001, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_BZU, 0, 0),
+ SVE2p1_SME2_INSN ("ldnt1b", 0xa0408001, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_BZU, 0, 0),
SME2_INSN ("ldnt1b", 0xa1400008, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_BZU, 0, 0),
SME2_INSN ("ldnt1b", 0xa1408008, 0xfff0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_BZU, 0, 0),
- SME2_INSN ("ldnt1b", 0xa0000001, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR), OP_SVE_BZU, 0, 0),
- SME2_INSN ("ldnt1b", 0xa0008001, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR), OP_SVE_BZU, 0, 0),
+ SVE2p1_SME2_INSN ("ldnt1b", 0xa0000001, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR), OP_SVE_BZU, 0, 0),
+ SVE2p1_SME2_INSN ("ldnt1b", 0xa0008001, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR), OP_SVE_BZU, 0, 0),
SME2_INSN ("ldnt1b", 0xa1000008, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR), OP_SVE_BZU, 0, 0),
SME2_INSN ("ldnt1b", 0xa1008008, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR), OP_SVE_BZU, 0, 0),
- SME2_INSN ("ldnt1d", 0xa0406001, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_DZU, 0, 0),
- SME2_INSN ("ldnt1d", 0xa040e001, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_DZU, 0, 0),
+ SVE2p1_SME2_INSN ("ldnt1d", 0xa0406001, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_DZU, 0, 0),
+ SVE2p1_SME2_INSN ("ldnt1d", 0xa040e001, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_DZU, 0, 0),
SME2_INSN ("ldnt1d", 0xa1406008, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_DZU, 0, 0),
SME2_INSN ("ldnt1d", 0xa140e008, 0xfff0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_DZU, 0, 0),
- SME2_INSN ("ldnt1d", 0xa0006001, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DZU, 0, 0),
- SME2_INSN ("ldnt1d", 0xa000e001, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DZU, 0, 0),
+ SVE2p1_SME2_INSN ("ldnt1d", 0xa0006001, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DZU, 0, 0),
+ SVE2p1_SME2_INSN ("ldnt1d", 0xa000e001, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DZU, 0, 0),
SME2_INSN ("ldnt1d", 0xa1006008, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DZU, 0, 0),
SME2_INSN ("ldnt1d", 0xa100e008, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DZU, 0, 0),
- SME2_INSN ("ldnt1h", 0xa0402001, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_HZU, 0, 0),
- SME2_INSN ("ldnt1h", 0xa040a001, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_HZU, 0, 0),
+ SVE2p1_SME2_INSN ("ldnt1h", 0xa0402001, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_HZU, 0, 0),
+ SVE2p1_SME2_INSN ("ldnt1h", 0xa040a001, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_HZU, 0, 0),
SME2_INSN ("ldnt1h", 0xa1402008, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_HZU, 0, 0),
SME2_INSN ("ldnt1h", 0xa140a008, 0xfff0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_HZU, 0, 0),
- SME2_INSN ("ldnt1h", 0xa0002001, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HZU, 0, 0),
- SME2_INSN ("ldnt1h", 0xa000a001, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HZU, 0, 0),
+ SVE2p1_SME2_INSN ("ldnt1h", 0xa0002001, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HZU, 0, 0),
+ SVE2p1_SME2_INSN ("ldnt1h", 0xa000a001, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HZU, 0, 0),
SME2_INSN ("ldnt1h", 0xa1002008, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HZU, 0, 0),
SME2_INSN ("ldnt1h", 0xa100a008, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HZU, 0, 0),
- SME2_INSN ("ldnt1w", 0xa0404001, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_SZU, 0, 0),
- SME2_INSN ("ldnt1w", 0xa040c001, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_SZU, 0, 0),
+ SVE2p1_SME2_INSN ("ldnt1w", 0xa0404001, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_SZU, 0, 0),
+ SVE2p1_SME2_INSN ("ldnt1w", 0xa040c001, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_SZU, 0, 0),
SME2_INSN ("ldnt1w", 0xa1404008, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_SZU, 0, 0),
SME2_INSN ("ldnt1w", 0xa140c008, 0xfff0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_SZU, 0, 0),
- SME2_INSN ("ldnt1w", 0xa0004001, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SZU, 0, 0),
- SME2_INSN ("ldnt1w", 0xa000c001, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SZU, 0, 0),
+ SVE2p1_SME2_INSN ("ldnt1w", 0xa0004001, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SZU, 0, 0),
+ SVE2p1_SME2_INSN ("ldnt1w", 0xa000c001, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SZU, 0, 0),
SME2_INSN ("ldnt1w", 0xa1004008, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SZU, 0, 0),
SME2_INSN ("ldnt1w", 0xa100c008, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SZU, 0, 0),
SME2_INSN ("ldr", 0xe11f8000, 0xfffffc1f, sme_misc, 0, OP2 (SME_ZT0, SIMD_ADDR_SIMPLE), {}, 0, 0),
@@ -6059,9 +6086,9 @@ const struct aarch64_opcode aarch64_opcode_table[] =
SME2_INSN ("mova", 0xc0040400, 0xff3f1c78, sme_size_22, 0, OP2 (SME_ZA_HV_idx_destxN, SME_Znx4), OP_SVE_VV_BHSDQ, F_OD (4), 0),
SME2_INSN ("movt", 0xc04e03e0, 0xffff8fe0, sme_misc, 0, OP2 (SME_ZT0_INDEX, Rt), OP_SVE_UX, 0, 0),
SME2_INSN ("movt", 0xc04c03e0, 0xffff8fe0, sme_misc, 0, OP2 (Rt, SME_ZT0_INDEX), OP_SVE_XU, 0, 0),
- SME2_INSN ("pext", 0x25207010, 0xff3ffc10, sme_size_22, 0, OP2 (SVE_Pd, SME_PNn3_INDEX2), OP_SVE_VU_BHSD, 0, 0),
- SME2_INSN ("pext", 0x25207410, 0xff3ffe10, sme_size_22, 0, OP2 (SME_PdxN, SME_PNn3_INDEX1), OP_SVE_VU_BHSD, F_OD (2), 0),
- SME2_INSN ("ptrue", 0x25207810, 0xff3ffff8, sme_size_22, 0, OP1 (SME_PNd3), OP_SVE_V_BHSD, 0, 0),
+ SVE2p1_SME2_INSN ("pext", 0x25207010, 0xff3ffc10, sme_size_22, 0, OP2 (SVE_Pd, SME_PNn3_INDEX2), OP_SVE_VU_BHSD, 0, 0),
+ SVE2p1_SME2_INSN ("pext", 0x25207410, 0xff3ffe10, sme_size_22, 0, OP2 (SME_PdxN, SME_PNn3_INDEX1), OP_SVE_VU_BHSD, F_OD (2), 0),
+ SVE2p1_SME2_INSN ("ptrue", 0x25207810, 0xff3ffff8, sme_size_22, 0, OP1 (SME_PNd3), OP_SVE_V_BHSD, 0, 0),
SME2_INSN ("sclamp", 0xc120c400, 0xff20fc01, sme_size_22, 0, OP3 (SME_Zdnx2, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
SME2_INSN ("sclamp", 0xc120cc00, 0xff20fc03, sme_size_22, 0, OP3 (SME_Zdnx4, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
SME2_INSN ("scvtf", 0xc122e000, 0xfffffc21, sve_misc, 0, OP2 (SME_Zdnx2, SME_Znx2), OP_SVE_SS, 0, 0),
@@ -6142,68 +6169,68 @@ const struct aarch64_opcode aarch64_opcode_table[] =
SME2_INSN ("srshl", 0xc120aa20, 0xff30ffe3, sme_size_22, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zm), OP_SVE_VVV_BHSD, 0, 1),
SME2_INSN ("srshl", 0xc120b220, 0xff21ffe1, sme_size_22, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zmx2), OP_SVE_VVV_BHSD, 0, 1),
SME2_INSN ("srshl", 0xc120ba20, 0xff23ffe3, sme_size_22, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zmx4), OP_SVE_VVV_BHSD, 0, 1),
- SME2_INSN ("st1b", 0xa0600000, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_BUU, 0, 0),
- SME2_INSN ("st1b", 0xa0608000, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_BUU, 0, 0),
+ SVE2p1_SME2_INSN ("st1b", 0xa0600000, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_BUU, 0, 0),
+ SVE2p1_SME2_INSN ("st1b", 0xa0608000, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_BUU, 0, 0),
SME2_INSN ("st1b", 0xa1600000, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_BUU, 0, 0),
SME2_INSN ("st1b", 0xa1608000, 0xfff0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_BUU, 0, 0),
- SME2_INSN ("st1b", 0xa0200000, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR), OP_SVE_BUU, 0, 0),
- SME2_INSN ("st1b", 0xa0208000, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR), OP_SVE_BUU, 0, 0),
+ SVE2p1_SME2_INSN ("st1b", 0xa0200000, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR), OP_SVE_BUU, 0, 0),
+ SVE2p1_SME2_INSN ("st1b", 0xa0208000, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR), OP_SVE_BUU, 0, 0),
SME2_INSN ("st1b", 0xa1200000, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR), OP_SVE_BUU, 0, 0),
SME2_INSN ("st1b", 0xa1208000, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR), OP_SVE_BUU, 0, 0),
- SME2_INSN ("st1d", 0xa0606000, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_DUU, 0, 0),
- SME2_INSN ("st1d", 0xa060e000, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_DUU, 0, 0),
+ SVE2p1_SME2_INSN ("st1d", 0xa0606000, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_DUU, 0, 0),
+ SVE2p1_SME2_INSN ("st1d", 0xa060e000, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_DUU, 0, 0),
SME2_INSN ("st1d", 0xa1606000, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_DUU, 0, 0),
SME2_INSN ("st1d", 0xa160e000, 0xfff0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_DUU, 0, 0),
- SME2_INSN ("st1d", 0xa0206000, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DUU, 0, 0),
- SME2_INSN ("st1d", 0xa020e000, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DUU, 0, 0),
+ SVE2p1_SME2_INSN ("st1d", 0xa0206000, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DUU, 0, 0),
+ SVE2p1_SME2_INSN ("st1d", 0xa020e000, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DUU, 0, 0),
SME2_INSN ("st1d", 0xa1206000, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DUU, 0, 0),
SME2_INSN ("st1d", 0xa120e000, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DUU, 0, 0),
- SME2_INSN ("st1h", 0xa0602000, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_HUU, 0, 0),
- SME2_INSN ("st1h", 0xa060a000, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_HUU, 0, 0),
+ SVE2p1_SME2_INSN ("st1h", 0xa0602000, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_HUU, 0, 0),
+ SVE2p1_SME2_INSN ("st1h", 0xa060a000, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_HUU, 0, 0),
SME2_INSN ("st1h", 0xa1602000, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_HUU, 0, 0),
SME2_INSN ("st1h", 0xa160a000, 0xfff0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_HUU, 0, 0),
- SME2_INSN ("st1h", 0xa0202000, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HUU, 0, 0),
- SME2_INSN ("st1h", 0xa020a000, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HUU, 0, 0),
+ SVE2p1_SME2_INSN ("st1h", 0xa0202000, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HUU, 0, 0),
+ SVE2p1_SME2_INSN ("st1h", 0xa020a000, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HUU, 0, 0),
SME2_INSN ("st1h", 0xa1202000, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HUU, 0, 0),
SME2_INSN ("st1h", 0xa120a000, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HUU, 0, 0),
- SME2_INSN ("st1w", 0xa0604000, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_SUU, 0, 0),
- SME2_INSN ("st1w", 0xa060c000, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_SUU, 0, 0),
+ SVE2p1_SME2_INSN ("st1w", 0xa0604000, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_SUU, 0, 0),
+ SVE2p1_SME2_INSN ("st1w", 0xa060c000, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_SUU, 0, 0),
SME2_INSN ("st1w", 0xa1604000, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_SUU, 0, 0),
SME2_INSN ("st1w", 0xa160c000, 0xfff0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_SUU, 0, 0),
- SME2_INSN ("st1w", 0xa0204000, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SUU, 0, 0),
- SME2_INSN ("st1w", 0xa020c000, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SUU, 0, 0),
+ SVE2p1_SME2_INSN ("st1w", 0xa0204000, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SUU, 0, 0),
+ SVE2p1_SME2_INSN ("st1w", 0xa020c000, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SUU, 0, 0),
SME2_INSN ("st1w", 0xa1204000, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SUU, 0, 0),
SME2_INSN ("st1w", 0xa120c000, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SUU, 0, 0),
- SME2_INSN ("stnt1b", 0xa0600001, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_BUU, 0, 0),
- SME2_INSN ("stnt1b", 0xa0608001, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_BUU, 0, 0),
+ SVE2p1_SME2_INSN ("stnt1b", 0xa0600001, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_BUU, 0, 0),
+ SVE2p1_SME2_INSN ("stnt1b", 0xa0608001, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_BUU, 0, 0),
SME2_INSN ("stnt1b", 0xa1600008, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_BUU, 0, 0),
SME2_INSN ("stnt1b", 0xa1608008, 0xfff0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_BUU, 0, 0),
- SME2_INSN ("stnt1b", 0xa0200001, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR), OP_SVE_BUU, 0, 0),
- SME2_INSN ("stnt1b", 0xa0208001, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR), OP_SVE_BUU, 0, 0),
+ SVE2p1_SME2_INSN ("stnt1b", 0xa0200001, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR), OP_SVE_BUU, 0, 0),
+ SVE2p1_SME2_INSN ("stnt1b", 0xa0208001, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR), OP_SVE_BUU, 0, 0),
SME2_INSN ("stnt1b", 0xa1200008, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR), OP_SVE_BUU, 0, 0),
SME2_INSN ("stnt1b", 0xa1208008, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR), OP_SVE_BUU, 0, 0),
- SME2_INSN ("stnt1d", 0xa0606001, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_DUU, 0, 0),
- SME2_INSN ("stnt1d", 0xa060e001, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_DUU, 0, 0),
+ SVE2p1_SME2_INSN ("stnt1d", 0xa0606001, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_DUU, 0, 0),
+ SVE2p1_SME2_INSN ("stnt1d", 0xa060e001, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_DUU, 0, 0),
SME2_INSN ("stnt1d", 0xa1606008, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_DUU, 0, 0),
SME2_INSN ("stnt1d", 0xa160e008, 0xfff0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_DUU, 0, 0),
- SME2_INSN ("stnt1d", 0xa0206001, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DUU, 0, 0),
- SME2_INSN ("stnt1d", 0xa020e001, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DUU, 0, 0),
+ SVE2p1_SME2_INSN ("stnt1d", 0xa0206001, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DUU, 0, 0),
+ SVE2p1_SME2_INSN ("stnt1d", 0xa020e001, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DUU, 0, 0),
SME2_INSN ("stnt1d", 0xa1206008, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DUU, 0, 0),
SME2_INSN ("stnt1d", 0xa120e008, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DUU, 0, 0),
- SME2_INSN ("stnt1h", 0xa0602001, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_HUU, 0, 0),
- SME2_INSN ("stnt1h", 0xa060a001, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_HUU, 0, 0),
+ SVE2p1_SME2_INSN ("stnt1h", 0xa0602001, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_HUU, 0, 0),
+ SVE2p1_SME2_INSN ("stnt1h", 0xa060a001, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_HUU, 0, 0),
SME2_INSN ("stnt1h", 0xa1602008, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_HUU, 0, 0),
SME2_INSN ("stnt1h", 0xa160a008, 0xfff0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_HUU, 0, 0),
- SME2_INSN ("stnt1h", 0xa0202001, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HUU, 0, 0),
- SME2_INSN ("stnt1h", 0xa020a001, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HUU, 0, 0),
+ SVE2p1_SME2_INSN ("stnt1h", 0xa0202001, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HUU, 0, 0),
+ SVE2p1_SME2_INSN ("stnt1h", 0xa020a001, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HUU, 0, 0),
SME2_INSN ("stnt1h", 0xa1202008, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HUU, 0, 0),
SME2_INSN ("stnt1h", 0xa120a008, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HUU, 0, 0),
- SME2_INSN ("stnt1w", 0xa0604001, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_SUU, 0, 0),
- SME2_INSN ("stnt1w", 0xa060c001, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_SUU, 0, 0),
+ SVE2p1_SME2_INSN ("stnt1w", 0xa0604001, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_SUU, 0, 0),
+ SVE2p1_SME2_INSN ("stnt1w", 0xa060c001, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_SUU, 0, 0),
SME2_INSN ("stnt1w", 0xa1604008, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_SUU, 0, 0),
SME2_INSN ("stnt1w", 0xa160c008, 0xfff0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_SUU, 0, 0),
- SME2_INSN ("stnt1w", 0xa0204001, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SUU, 0, 0),
- SME2_INSN ("stnt1w", 0xa020c001, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SUU, 0, 0),
+ SVE2p1_SME2_INSN ("stnt1w", 0xa0204001, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SUU, 0, 0),
+ SVE2p1_SME2_INSN ("stnt1w", 0xa020c001, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SUU, 0, 0),
SME2_INSN ("stnt1w", 0xa1204008, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SUU, 0, 0),
SME2_INSN ("stnt1w", 0xa120c008, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SUU, 0, 0),
SME2_INSN ("str", 0xe13f8000, 0xfffffc1f, sme_misc, 0, OP2 (SME_ZT0, SIMD_ADDR_SIMPLE), {}, 0, 0),
@@ -6318,14 +6345,14 @@ const struct aarch64_opcode aarch64_opcode_table[] =
SME2_INSN ("uzp", 0xc120d401, 0xffe0fc01, sme_misc, 0, OP3 (SME_Zdnx2, SVE_Zn, SVE_Zm_16), OP_SVE_QQQ, 0, 0),
SME2_INSN ("uzp", 0xc136e002, 0xff3ffc63, sme_size_22, 0, OP2 (SME_Zdnx4, SME_Znx4), OP_SVE_VV_BHSD, 0, 0),
SME2_INSN ("uzp", 0xc137e002, 0xfffffc63, sme_misc, 0, OP2 (SME_Zdnx4, SME_Znx4), OP_SVE_QQ, 0, 0),
- SME2_INSN ("whilege", 0x25204010, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0),
- SME2_INSN ("whilegt", 0x25204018, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0),
- SME2_INSN ("whilehi", 0x25204818, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0),
- SME2_INSN ("whilehs", 0x25204810, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0),
- SME2_INSN ("whilele", 0x25204418, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0),
- SME2_INSN ("whilelo", 0x25204c10, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0),
- SME2_INSN ("whilels", 0x25204c18, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0),
- SME2_INSN ("whilelt", 0x25204410, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0),
+ SVE2p1_SME2_INSN ("whilege", 0x25204010, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0),
+ SVE2p1_SME2_INSN ("whilegt", 0x25204018, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0),
+ SVE2p1_SME2_INSN ("whilehi", 0x25204818, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0),
+ SVE2p1_SME2_INSN ("whilehs", 0x25204810, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0),
+ SVE2p1_SME2_INSN ("whilele", 0x25204418, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0),
+ SVE2p1_SME2_INSN ("whilelo", 0x25204c10, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0),
+ SVE2p1_SME2_INSN ("whilels", 0x25204c18, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0),
+ SVE2p1_SME2_INSN ("whilelt", 0x25204410, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0),
SME2_INSN ("zero", 0xc0480001, 0xffffffff, sme_misc, 0, OP1 (SME_ZT0_LIST), {}, 0, 0),
SME2_INSN ("zip", 0xc120d000, 0xff20fc01, sme_size_22, 0, OP3 (SME_Zdnx2, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
SME2_INSN ("zip", 0xc120d400, 0xffe0fc01, sme_misc, 0, OP3 (SME_Zdnx2, SVE_Zn, SVE_Zm_16), OP_SVE_QQQ, 0, 0),
@@ -6766,54 +6793,63 @@ const struct aarch64_opcode aarch64_opcode_table[] =
SME_F16F16_INSN("fcvtl", 0xc1a0e001, 0xfffffc01, sme_misc, 0, OP2 (SME_Zdnx2, SVE_Zn), OP_SVE_SH, F_OD (2), 0),
/* SVE2p1 Instructions. */
- SVE2p1_INSN("addqv",0x04052000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, 0),
- SVE2p1_INSN("andqv",0x041e2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, 0),
- SVE2p1_INSN("smaxqv",0x040c2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, 0),
- SVE2p1_INSN("sminqv",0x040e2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, 0),
- SVE2p1_INSN("umaxqv",0x040d2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, 0),
- SVE2p1_INSN("uminqv",0x040f2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, 0),
- SVE2p1_INSN("eorqv",0x041d2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, 0),
- SVE2p1_INSN("faddqv",0x6410a000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_HSD_HSD, F_OPD_SIZE, 0),
- SVE2p1_INSN("fmaxnmqv",0x6414a000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_HSD_HSD, F_OPD_SIZE, 0),
- SVE2p1_INSN("fmaxqv",0x6416a000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_HSD_HSD, F_OPD_SIZE, 0),
- SVE2p1_INSN("fminnmqv",0x6415a000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_HSD_HSD, F_OPD_SIZE, 0),
- SVE2p1_INSN("fminqv",0x6417a000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_HSD_HSD, F_OPD_SIZE, 0),
-
- SVE2p1_INSN("dupq",0x05202400, 0xffe0fc00, sve_index, 0, OP2 (SVE_Zd, SVE_Zn_5_INDEX), OP_SVE_VV_BHSD, 0, 0),
- SVE2p1_INSN("orqv",0x041c2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, 0),
- SVE2p1_INSN("tblq",0x4400f800, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_ZnxN, SVE_Zm_16), OP_SVE_VVV_BHSD, F_OD(1), 0),
- SVE2p1_INSN("tbxq",0x05203400, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
- SVE2p1_INSNC("extq",0x05602400, 0xfff0fc00, sve_misc, 0, OP4 (SVE_Zd, SVE_Zd, SVE_Zm_5, SVE_UIMM4), OP_SVE_BBBU, 0, C_SCAN_MOVPRFX, 1),
- SVE2p1_INSN("uzpq1",0x4400e800, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
- SVE2p1_INSN("uzpq2",0x4400ec00, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
- SVE2p1_INSN("zipq1",0x4400e000, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
- SVE2p1_INSN("zipq2",0x4400e400, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
-
- SVE2p1_INSN("pmov",0x052a3800, 0xfffffc10, sve_misc, 0, OP2 (SVE_Pd, SVE_Zn0_INDEX), OP_SVE_BU, 0, 0),
- SVE2p1_INSN("pmov",0x052c3800, 0xfffdfc10, sve_misc, 0, OP2 (SVE_Pd, SVE_Zn1_17_INDEX), OP_SVE_HU, 0, 0),
- SVE2p1_INSN("pmov",0x05683800, 0xfff9fc10, sve_misc, 0, OP2 (SVE_Pd, SVE_Zn2_18_INDEX), OP_SVE_SU, 0, 0),
- SVE2p1_INSN("pmov",0x05a83800, 0xffb9fc10, sve_misc, 0, OP2 (SVE_Pd, SVE_Zn3_22_INDEX), OP_SVE_DU, 0, 0),
-
- SVE2p1_INSN("pmov",0x052b3800, 0xfffffe00, sve_misc, 0, OP2 (SVE_Zd0_INDEX, SVE_Pg4_5), OP_SVE_UB, 0, 0),
- SVE2p1_INSN("pmov",0x052d3800, 0xfffdfe00, sve_misc, 0, OP2 (SVE_Zd1_17_INDEX, SVE_Pg4_5), OP_SVE_UH, 0, 0),
- SVE2p1_INSN("pmov",0x05693800, 0xfff9fe00, sve_misc, 0, OP2 (SVE_Zd2_18_INDEX, SVE_Pg4_5), OP_SVE_US, 0, 0),
- SVE2p1_INSN("pmov",0x05a93800, 0xffb9fe00, sve_misc, 0, OP2 (SVE_Zd3_22_INDEX, SVE_Pg4_5), OP_SVE_UD, 0, 0),
+ SVE2p1_SME2p1_INSN("addqv",0x04052000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, 0),
+ SVE2p1_SME2p1_INSN("andqv",0x041e2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, 0),
+ SVE2p1_SME2p1_INSN("smaxqv",0x040c2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, 0),
+ SVE2p1_SME2p1_INSN("sminqv",0x040e2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, 0),
+ SVE2p1_SME2p1_INSN("umaxqv",0x040d2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, 0),
+ SVE2p1_SME2p1_INSN("uminqv",0x040f2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, 0),
+ SVE2p1_SME2p1_INSN("eorqv",0x041d2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, 0),
+ SVE2p1_SME2p1_INSN("faddqv",0x6410a000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_HSD_HSD, F_OPD_SIZE, 0),
+ SVE2p1_SME2p1_INSN("fmaxnmqv",0x6414a000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_HSD_HSD, F_OPD_SIZE, 0),
+ SVE2p1_SME2p1_INSN("fmaxqv",0x6416a000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_HSD_HSD, F_OPD_SIZE, 0),
+ SVE2p1_SME2p1_INSN("fminnmqv",0x6415a000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_HSD_HSD, F_OPD_SIZE, 0),
+ SVE2p1_SME2p1_INSN("fminqv",0x6417a000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_HSD_HSD, F_OPD_SIZE, 0),
+
+ SVE2p1_SME2p1_INSN("dupq",0x05202400, 0xffe0fc00, sve_index, 0, OP2 (SVE_Zd, SVE_Zn_5_INDEX), OP_SVE_VV_BHSD, 0, 0),
+ SVE2p1_SME2p1_INSN("orqv",0x041c2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, 0),
+ SVE2p1_SME2p1_INSN("tblq",0x4400f800, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_ZnxN, SVE_Zm_16), OP_SVE_VVV_BHSD, F_OD(1), 0),
+ SVE2p1_SME2p1_INSN("tbxq",0x05203400, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
+ SVE2p1_SME2p1_INSNC("extq",0x05602400, 0xfff0fc00, sve_misc, 0, OP4 (SVE_Zd, SVE_Zd, SVE_Zm_5, SVE_UIMM4), OP_SVE_BBBU, 0, C_SCAN_MOVPRFX, 1),
+ SVE2p1_SME2p1_INSN("uzpq1",0x4400e800, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
+ SVE2p1_SME2p1_INSN("uzpq2",0x4400ec00, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
+ SVE2p1_SME2p1_INSN("zipq1",0x4400e000, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
+ SVE2p1_SME2p1_INSN("zipq2",0x4400e400, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
+
+ SVE2p1_SME2p1_INSN("pmov",0x052a3800, 0xfffffc10, sve_misc, 0, OP2 (SVE_Pd, SVE_Zn0_INDEX), OP_SVE_BU, 0, 0),
+ SVE2p1_SME2p1_INSN("pmov",0x052c3800, 0xfffdfc10, sve_misc, 0, OP2 (SVE_Pd, SVE_Zn1_17_INDEX), OP_SVE_HU, 0, 0),
+ SVE2p1_SME2p1_INSN("pmov",0x05683800, 0xfff9fc10, sve_misc, 0, OP2 (SVE_Pd, SVE_Zn2_18_INDEX), OP_SVE_SU, 0, 0),
+ SVE2p1_SME2p1_INSN("pmov",0x05a83800, 0xffb9fc10, sve_misc, 0, OP2 (SVE_Pd, SVE_Zn3_22_INDEX), OP_SVE_DU, 0, 0),
+
+ SVE2p1_SME2p1_INSN("pmov",0x052b3800, 0xfffffe00, sve_misc, 0, OP2 (SVE_Zd0_INDEX, SVE_Pg4_5), OP_SVE_UB, 0, 0),
+ SVE2p1_SME2p1_INSN("pmov",0x052d3800, 0xfffdfe00, sve_misc, 0, OP2 (SVE_Zd1_17_INDEX, SVE_Pg4_5), OP_SVE_UH, 0, 0),
+ SVE2p1_SME2p1_INSN("pmov",0x05693800, 0xfff9fe00, sve_misc, 0, OP2 (SVE_Zd2_18_INDEX, SVE_Pg4_5), OP_SVE_US, 0, 0),
+ SVE2p1_SME2p1_INSN("pmov",0x05a93800, 0xffb9fe00, sve_misc, 0, OP2 (SVE_Zd3_22_INDEX, SVE_Pg4_5), OP_SVE_UD, 0, 0),
+
+ SVE2p1_INSN("ld1d",0xa5902000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_QZU, F_OD(1), 0),
+ SVE2p1_INSN("ld1d",0xa5808000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL3), OP_SVE_QZU, F_OD(1), 0),
+ SVE2p1_INSN("ld1w",0xa5102000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_QZU, F_OD(1), 0),
+ SVE2p1_INSN("ld1w",0xa5008000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL2), OP_SVE_QZU, F_OD(1), 0),
+ SVE2p1_INSN("st1d",0xe5c0e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_QUU, F_OD(1), 0),
+ SVE2p1_INSN("st1d",0xe5c04000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL3), OP_SVE_QUU, F_OD(1), 0),
+ SVE2p1_INSN("st1w",0xe500e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_QUU, F_OD(1), 0),
+ SVE2p1_INSN("st1w",0xe5004000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL2), OP_SVE_QUU, F_OD(1), 0),
SVE2p1_INSN("ld1q",0xc400a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_QZD, F_OD (1), 0),
- SVE2p1_INSN("ld2q",0xa490e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_QZU, F_OD (2), 0),
- SVE2p1_INSN("ld3q",0xa510e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x3xVL), OP_SVE_QZU, F_OD (3), 0),
- SVE2p1_INSN("ld4q",0xa590e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_QZU, F_OD (4), 0),
- SVE2p1_INSN("ld2q",0xa4a08000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL4), OP_SVE_QZU, F_OD (2), 0),
- SVE2p1_INSN("ld3q",0xa5208000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL4), OP_SVE_QZU, F_OD (3), 0),
- SVE2p1_INSN("ld4q",0xa5a08000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL4), OP_SVE_QZU, F_OD (4), 0),
+ SVE2p1_SME2p1_INSN("ld2q",0xa490e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_QZU, F_OD (2), 0),
+ SVE2p1_SME2p1_INSN("ld3q",0xa510e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x3xVL), OP_SVE_QZU, F_OD (3), 0),
+ SVE2p1_SME2p1_INSN("ld4q",0xa590e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_QZU, F_OD (4), 0),
+ SVE2p1_SME2p1_INSN("ld2q",0xa4a08000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL4), OP_SVE_QZU, F_OD (2), 0),
+ SVE2p1_SME2p1_INSN("ld3q",0xa5208000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL4), OP_SVE_QZU, F_OD (3), 0),
+ SVE2p1_SME2p1_INSN("ld4q",0xa5a08000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL4), OP_SVE_QZU, F_OD (4), 0),
SVE2p1_INSN("st1q",0xe4202000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_QUD, F_OD (1), 0),
- SVE2p1_INSN("st2q",0xe4400000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_QUU, F_OD (2), 0),
- SVE2p1_INSN("st3q",0xe4800000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x3xVL), OP_SVE_QUU, F_OD (3), 0),
- SVE2p1_INSN("st4q",0xe4c00000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_QUU, F_OD (4), 0),
- SVE2p1_INSN("st2q",0xe4600000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL4), OP_SVE_QUU, F_OD (2), 0),
- SVE2p1_INSN("st3q",0xe4a00000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL4), OP_SVE_QUU, F_OD (3), 0),
- SVE2p1_INSN("st4q",0xe4e00000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL4), OP_SVE_QUU, F_OD (4), 0),
+ SVE2p1_SME2p1_INSN("st2q",0xe4400000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_QUU, F_OD (2), 0),
+ SVE2p1_SME2p1_INSN("st3q",0xe4800000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x3xVL), OP_SVE_QUU, F_OD (3), 0),
+ SVE2p1_SME2p1_INSN("st4q",0xe4c00000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_QUU, F_OD (4), 0),
+ SVE2p1_SME2p1_INSN("st2q",0xe4600000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL4), OP_SVE_QUU, F_OD (2), 0),
+ SVE2p1_SME2p1_INSN("st3q",0xe4a00000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL4), OP_SVE_QUU, F_OD (3), 0),
+ SVE2p1_SME2p1_INSN("st4q",0xe4e00000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL4), OP_SVE_QUU, F_OD (4), 0),
FP8_INSN("bf1cvtl", 0x2ea17800, 0xfffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2_HB_LOWER, 0),
FP8_INSN("bf1cvtl2", 0x6ea17800, 0xfffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2_HB_FULL, 0),
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