[PATCH 1/2] RISC-V: Support extension Zicfiss and Zicfilp
Kito Cheng
kito.cheng@gmail.com
Fri Jan 17 01:53:39 GMT 2025
Hi Nelson and Jan:
Thanks for your comments, v2 has addressed all comments I believe :)
On Mon, Jan 13, 2025 at 10:38 AM Nelson Chu <nelson@rivosinc.com> wrote:
>
> Jan's comments won't be repeated here, so...
>
> On Fri, Jan 10, 2025 at 6:17 PM Kito Cheng <kito.cheng@sifive.com> wrote:
>>
>> From: Monk Chiang <monk.chiang@sifive.com>
>>
>> Spec: https://github.com/riscv/riscv-cfi/releases/tag/v1.0
>> ---
>>
>> diff --git a/gas/testsuite/gas/riscv/march-imply-zicfilp.d b/gas/testsuite/gas/riscv/march-imply-zicfilp.d
>> new file mode 100644
>> index 00000000000..753da438121
>> --- /dev/null
>> +++ b/gas/testsuite/gas/riscv/march-imply-zicfilp.d
>> @@ -0,0 +1,6 @@
>> +#as: -march=rv32i_zicfilp -march-attr
>> +#readelf: -A
>> +#source: empty.s
>> +Attribute Section: riscv
>> +File Attributes
>> + Tag_RISCV_arch: "rv32i2p1_zicfilp1p0_zicsr2p0"
>
>
> Should be included into the imply test case since,
>
> https://github.com/bminor/binutils-gdb/commit/14ea7f9b443950dac2b40f234e820be8a09cbb8a
>
>
>>
>> diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
>> index de4c13fb6db..86d995ed97c 100644
>> --- a/include/opcode/riscv.h
>> +++ b/include/opcode/riscv.h
>> @@ -133,6 +133,12 @@ static inline unsigned int riscv_insn_length (insn_t insn)
>> #define EXTRACT_CV_SIMD_UIMM6(x) \
>> ((RV_X(x, 25, 1)) | (RV_X(x, 20, 5) << 1))
>>
>> +#define EXTRACT_ZICFISS_UIMM5(x) \
>> + (RV_X(x, 15, 5))
>> +
>> +#define EXTRACT_C_MOP_N(x) \
>> + (RV_X(x, 7, 4))
>> +
>> #define ENCODE_ITYPE_IMM(x) \
>> (RV_X(x, 0, 12) << 20)
>> #define ENCODE_STYPE_IMM(x) \
>> @@ -201,6 +207,9 @@ static inline unsigned int riscv_insn_length (insn_t insn)
>> #define ENCODE_CV_SIMD_UIMM6(x) \
>> ((RV_X(x, 0, 1) << 25) | (RV_X(x, 1, 5) << 20))
>>
>> +#define ENCODE_ZICFISS_UIMM5(x) \
>> + (RV_X(x, 0, 5) << 15)
>> +
>> #define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x))
>> #define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x))
>> #define VALID_BTYPE_IMM(x) (EXTRACT_BTYPE_IMM(ENCODE_BTYPE_IMM(x)) == (x))
>> @@ -229,6 +238,10 @@ static inline unsigned int riscv_insn_length (insn_t insn)
>> #define VALID_ZCB_HALFWORD_UIMM(x) (EXTRACT_ZCB_HALFWORD_UIMM(ENCODE_ZCB_HALFWORD_UIMM(x)) == (x))
>> #define VALID_ZCMP_SPIMM(x) (EXTRACT_ZCMP_SPIMM(ENCODE_ZCMP_SPIMM(x)) == (x))
>>
>> +/* Zicfiss extension. */
>> +#define VALID_ZICFISS_UIMM5(x) (EXTRACT_ZICFISS_UIMM5(ENCODE_ZICFISS_UIMM5(x)) != 0 \
>> + && EXTRACT_ZICFISS_UIMM5(ENCODE_ZICFISS_UIMM5(x)) == (x))
>> +
>> #define RISCV_RTYPE(insn, rd, rs1, rs2) \
>> ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2))
>> #define RISCV_ITYPE(insn, rd, rs1, imm) \
>> @@ -374,6 +387,10 @@ static inline unsigned int riscv_insn_length (insn_t insn)
>> #define OP_MASK_SREG2 0x7
>> #define OP_SH_SREG2 2
>>
>> +/* Zicfiss fields. */
>> +#define OP_MASK_ZICFISS_UIMM5 0x1f
>> +#define OP_SH_ZICFISS_UIMM5 15
>
>
> These new defined VALID/ENCODE/EXTRACT for zicfiss looks useless in this patch?
>
>>
>> +static int
>> +match_c_mop_1 (const struct riscv_opcode *op,
>> + insn_t insn)
>> +{
>> + int n = EXTRACT_C_MOP_N (insn) ;
>> + return match_opcode (op, insn) && n == 1;
>> +}
>> +
>> +static int
>> +match_c_mop_5 (const struct riscv_opcode *op,
>> + insn_t insn)
>> +{
>> + int n = EXTRACT_C_MOP_N (insn) ;
>> + return match_opcode (op, insn) && n == 5;
>> +}
>
>
> The match_c_mop_1 and match_c_mop_5 look useless in this patch?
>
> Nelson
>
>>
>> const struct riscv_opcode riscv_opcodes[] =
>> {
>> @@ -546,6 +577,10 @@ const struct riscv_opcode riscv_opcodes[] =
>> {"or", 0, INSN_CLASS_C, "Cs,Cw,Ct", MATCH_C_OR, MASK_C_OR, match_opcode, INSN_ALIAS },
>> {"or", 0, INSN_CLASS_C, "Cs,Ct,Cw", MATCH_C_OR, MASK_C_OR, match_opcode, INSN_ALIAS },
>> {"or", 0, INSN_CLASS_I, "d,s,t", MATCH_OR, MASK_OR, match_opcode, 0 },
>> +
>> +/* Zicfilp instructions. */
>> +{"lpad", 0, INSN_CLASS_ZICFILP, "u", MATCH_LPAD, MASK_LPAD, match_opcode, 0 },
>> +
>> {"auipc", 0, INSN_CLASS_I, "d,u", MATCH_AUIPC, MASK_AUIPC, match_opcode, 0 },
>> {"seqz", 0, INSN_CLASS_I, "d,s", MATCH_SLTIU|ENCODE_ITYPE_IMM (1), MASK_SLTIU | MASK_IMM, match_opcode, INSN_ALIAS },
>> {"snez", 0, INSN_CLASS_I, "d,t", MATCH_SLTU, MASK_SLTU|MASK_RS1, match_opcode, INSN_ALIAS },
>> @@ -1150,6 +1185,23 @@ const struct riscv_opcode riscv_opcodes[] =
>> {"czero.eqz", 0, INSN_CLASS_ZICOND, "d,s,t", MATCH_CZERO_EQZ, MASK_CZERO_EQZ, match_opcode, 0 },
>> {"czero.nez", 0, INSN_CLASS_ZICOND, "d,s,t", MATCH_CZERO_NEZ, MASK_CZERO_NEZ, match_opcode, 0 },
>>
>> +/* Zicfiss instructions. */
>> +{"sspush", 0, INSN_CLASS_ZICFISS_AND_ZCMOP, "d", MATCH_C_SSPUSH, MASK_C_SSPUSH, match_rd_x1x5_opcode, INSN_ALIAS },
>> +{"sspush", 0, INSN_CLASS_ZICFISS, "t", MATCH_SSPUSH, MASK_SSPUSH, match_rs2_x1x5_opcode, 0 },
>> +{"sspopchk", 0, INSN_CLASS_ZICFISS_AND_ZCMOP, "d", MATCH_C_SSPOPCHK, MASK_C_SSPOPCHK, match_rd_x1x5_opcode, INSN_ALIAS },
>> +{"sspopchk", 0, INSN_CLASS_ZICFISS, "s", MATCH_SSPOPCHK, MASK_SSPOPCHK, match_rs1_x1x5_opcode, 0 },
>> +{"c.sspush", 0, INSN_CLASS_ZICFISS_AND_ZCMOP, "d", MATCH_C_SSPUSH, MASK_C_SSPUSH, match_rd_x1x5_opcode, 0 },
>> +{"c.sspopchk", 0, INSN_CLASS_ZICFISS_AND_ZCMOP, "d", MATCH_C_SSPOPCHK, MASK_C_SSPOPCHK, match_rd_x1x5_opcode, 0 },
>> +{"ssrdp", 0, INSN_CLASS_ZICFISS, "d", MATCH_SSRDP, MASK_SSRDP, match_opcode, 0 },
>> +{"ssamoswap.w", 32, INSN_CLASS_ZICFISS, "d,t,0(s)", MATCH_SSAMOSWAP_W, MASK_SSAMOSWAP_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
>> +{"ssamoswap.w.aq", 32, INSN_CLASS_ZICFISS, "d,t,0(s)", MATCH_SSAMOSWAP_W|MASK_AQ, MASK_SSAMOSWAP_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
>> +{"ssamoswap.w.rl", 32, INSN_CLASS_ZICFISS, "d,t,0(s)", MATCH_SSAMOSWAP_W|MASK_RL, MASK_SSAMOSWAP_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
>> +{"ssamoswap.w.aqrl", 32, INSN_CLASS_ZICFISS, "d,t,0(s)", MATCH_SSAMOSWAP_W|MASK_AQRL, MASK_SSAMOSWAP_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
>> +{"ssamoswap.d", 64, INSN_CLASS_ZICFISS, "d,t,0(s)", MATCH_SSAMOSWAP_D, MASK_SSAMOSWAP_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
>> +{"ssamoswap.d.aq", 64, INSN_CLASS_ZICFISS, "d,t,0(s)", MATCH_SSAMOSWAP_D|MASK_AQ, MASK_SSAMOSWAP_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
>> +{"ssamoswap.d.rl", 64, INSN_CLASS_ZICFISS, "d,t,0(s)", MATCH_SSAMOSWAP_D|MASK_RL, MASK_SSAMOSWAP_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
>> +{"ssamoswap.d.aqrl", 64, INSN_CLASS_ZICFISS, "d,t,0(s)", MATCH_SSAMOSWAP_D|MASK_AQRL, MASK_SSAMOSWAP_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
>> +
>> /* Zimop instructions. */
>> {"mop.r.0", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_0, MASK_MOP_R_0, match_opcode, 0 },
>> {"mop.r.1", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_1, MASK_MOP_R_1, match_opcode, 0 },
>> --
>> 2.34.1
>>
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