[RFC PATCH] x86: Ignore rounding for vcvt[, u]si2sd under r32 and vcvt[,u]dq2pd instead of reporting bad
Christian Ludloff
ludloff@gmail.com
Tue Jan 14 09:05:58 GMT 2025
The toolchains are priority #2 here.
The various chips with AVX10.2 are priority #1, i.e. did they get the
{er.ignored} right for the two CVTs I listed, or will they unexpectedly #UD
upon U=0...
--
C.
On Tue, Jan 14, 2025, 09:35 Haochen Jiang <haochen.jiang@intel.com> wrote:
> Hi all,
>
> I just did a quick try on the rounding ignore in disassembler for
> vcvt[,u]si2sd under r32 and vcvt[,u]dq2pd. It is doable in a small
> patch following, with some change in OP_Rounding. So I called it
> an RFC patch to see if we should do so.
>
> For assembler part, it is much easier to accept that inline asm. I
> will do that in parallel with disassembler RFC patch review.
>
> Thx,
> Haochen
>
> ---
>
> According to SDM, vcvt[,u]si2sd under r32 and vcvt[,u]dq2pd treat
> Rounding as Ignored when trying to using them. Thus, disassembler should
> not reject them or report bad.
>
> gas/ChangeLog:
>
> * testsuite/gas/i386/evex.d: Add new testcase for vcvt[,u]dq2pd.
> Change the output for vcvt[,u]si2sd.
> * testsuite/gas/i386/evex.s: Ditto.
> * testsuite/gas/i386/x86-64-evex.d: Ditto.
>
> opcodes/ChangeLog:
>
> * i386-dis-evex-w.h: Add EXxEVexRIG for vcvt[,u]dq2pd.
> * i386-dis.c (EXxEVexRIG): New.
> (evex_rounding_ignore_mode): Ditto.
> (OP_Rounding): Mark EVEX_b as used to change the handle for
> ignored rounding.
> ---
> gas/testsuite/gas/i386/evex.d | 12 ++++++++----
> gas/testsuite/gas/i386/evex.s | 4 ++++
> gas/testsuite/gas/i386/x86-64-evex.d | 8 ++++++--
> opcodes/i386-dis-evex-w.h | 4 ++--
> opcodes/i386-dis.c | 8 ++++++--
> 5 files changed, 26 insertions(+), 10 deletions(-)
>
> diff --git a/gas/testsuite/gas/i386/evex.d b/gas/testsuite/gas/i386/evex.d
> index 52670f82736..a352340cae6 100644
> --- a/gas/testsuite/gas/i386/evex.d
> +++ b/gas/testsuite/gas/i386/evex.d
> @@ -8,14 +8,18 @@ Disassembly of section .text:
>
> 0+ <_start>:
> +[a-f0-9]+: 62 f1 d6 38 2a f0 vcvtsi2ssl
> %eax,\{rd-sae\},%xmm5,%xmm6
> - +[a-f0-9]+: 62 f1 57 38 2a f0 vcvtsi2sdl
> %eax,\{rd-bad\},%xmm5,%xmm6
> - +[a-f0-9]+: 62 f1 d7 38 2a f0 vcvtsi2sdl
> %eax,\{rd-bad\},%xmm5,%xmm6
> + +[a-f0-9]+: 62 f1 57 38 2a f0 vcvtsi2sdl %eax,%xmm5,%xmm6
> + +[a-f0-9]+: 62 f1 d7 38 2a f0 vcvtsi2sdl %eax,%xmm5,%xmm6
> +[a-f0-9]+: 62 f1 d6 08 7b f0 vcvtusi2ssl %eax,%xmm5,%xmm6
> +[a-f0-9]+: 62 f1 57 08 7b f0 vcvtusi2sdl %eax,%xmm5,%xmm6
> +[a-f0-9]+: 62 f1 d7 08 7b f0 vcvtusi2sdl %eax,%xmm5,%xmm6
> +[a-f0-9]+: 62 f1 d6 38 7b f0 vcvtusi2ssl
> %eax,\{rd-sae\},%xmm5,%xmm6
> - +[a-f0-9]+: 62 f1 57 38 7b f0 vcvtusi2sdl
> %eax,\{rd-bad\},%xmm5,%xmm6
> - +[a-f0-9]+: 62 f1 d7 38 7b f0 vcvtusi2sdl
> %eax,\{rd-bad\},%xmm5,%xmm6
> + +[a-f0-9]+: 62 f1 57 38 7b f0 vcvtusi2sdl %eax,%xmm5,%xmm6
> + +[a-f0-9]+: 62 f1 d7 38 7b f0 vcvtusi2sdl %eax,%xmm5,%xmm6
> +[a-f0-9]+: 62 e1 7e 08 2d c0 \{evex\} vcvtss2si %xmm0,%eax
> +[a-f0-9]+: 62 e1 7c 08 c2 c0 00 vcmpeqps %xmm0,%xmm0,%k0
> + +[a-f0-9]+: 62 f1 7e 38 e6 f5 vcvtdq2pd %ymm5,%zmm6
> + +[a-f0-9]+: 62 f1 7a 38 e6 f5 vcvtdq2pd %xmm5,%ymm6
> + +[a-f0-9]+: 62 f1 7e 38 7a f5 vcvtudq2pd %ymm5,%zmm6
> + +[a-f0-9]+: 62 f1 7a 38 7a f5 vcvtudq2pd %xmm5,%ymm6
> #pass
> diff --git a/gas/testsuite/gas/i386/evex.s b/gas/testsuite/gas/i386/evex.s
> index b72e1cd1e4f..23582fe6005 100644
> --- a/gas/testsuite/gas/i386/evex.s
> +++ b/gas/testsuite/gas/i386/evex.s
> @@ -13,3 +13,7 @@ _start:
> .insn EVEX.LIG.F2.0F.W1 0x7b, %eax,{rd-sae},%xmm5,%xmm6
> .byte 0x62, 0xe1, 0x7e, 0x08, 0x2d, 0xc0
> .byte 0x62, 0xe1, 0x7c, 0x08, 0xc2, 0xc0, 0x00
> + .insn EVEX.L2.F3.0F.W0 0xe6, {rd-sae},%zmm5,%ymm6
> + .insn EVEX.L1.F3.0F.W0 0xe6, {rd-sae},%ymm5,%xmm6
> + .insn EVEX.L2.F3.0F.W0 0x7a, {rd-sae},%zmm5,%ymm6
> + .insn EVEX.L1.F3.0F.W0 0x7a, {rd-sae},%ymm5,%xmm6
> diff --git a/gas/testsuite/gas/i386/x86-64-evex.d
> b/gas/testsuite/gas/i386/x86-64-evex.d
> index 5d974c312da..6fb4bf87863 100644
> --- a/gas/testsuite/gas/i386/x86-64-evex.d
> +++ b/gas/testsuite/gas/i386/x86-64-evex.d
> @@ -9,14 +9,18 @@ Disassembly of section .text:
>
> 0+ <_start>:
> +[a-f0-9]+: 62 f1 d6 38 2a f0 vcvtsi2ss
> %rax,\{rd-sae\},%xmm5,%xmm6
> - +[a-f0-9]+: 62 f1 57 38 2a f0 vcvtsi2sd
> %eax,\{rd-bad\},%xmm5,%xmm6
> + +[a-f0-9]+: 62 f1 57 38 2a f0 vcvtsi2sd %eax,%xmm5,%xmm6
> +[a-f0-9]+: 62 f1 d7 38 2a f0 vcvtsi2sd
> %rax,\{rd-sae\},%xmm5,%xmm6
> +[a-f0-9]+: 62 f1 d6 08 7b f0 vcvtusi2ss %rax,%xmm5,%xmm6
> +[a-f0-9]+: 62 f1 57 08 7b f0 vcvtusi2sd %eax,%xmm5,%xmm6
> +[a-f0-9]+: 62 f1 d7 08 7b f0 vcvtusi2sd %rax,%xmm5,%xmm6
> +[a-f0-9]+: 62 f1 d6 38 7b f0 vcvtusi2ss
> %rax,\{rd-sae\},%xmm5,%xmm6
> - +[a-f0-9]+: 62 f1 57 38 7b f0 vcvtusi2sd
> %eax,\{rd-bad\},%xmm5,%xmm6
> + +[a-f0-9]+: 62 f1 57 38 7b f0 vcvtusi2sd %eax,%xmm5,%xmm6
> +[a-f0-9]+: 62 f1 d7 38 7b f0 vcvtusi2sd
> %rax,\{rd-sae\},%xmm5,%xmm6
> +[a-f0-9]+: 62 e1 7e 08 2d c0 vcvtss2si %xmm0,%r16d
> +[a-f0-9]+: 62 e1 7c 08 c2 c0 00 vcmpeqps %xmm0,%xmm0,\(bad\)
> + +[a-f0-9]+: 62 f1 7e 38 e6 f5 vcvtdq2pd %ymm5,%zmm6
> + +[a-f0-9]+: 62 f1 7a 38 e6 f5 vcvtdq2pd %xmm5,%ymm6
> + +[a-f0-9]+: 62 f1 7e 38 7a f5 vcvtudq2pd %ymm5,%zmm6
> + +[a-f0-9]+: 62 f1 7a 38 7a f5 vcvtudq2pd %xmm5,%ymm6
> #pass
> diff --git a/opcodes/i386-dis-evex-w.h b/opcodes/i386-dis-evex-w.h
> index 1bb716c0ba7..bad84c56fb4 100644
> --- a/opcodes/i386-dis-evex-w.h
> +++ b/opcodes/i386-dis-evex-w.h
> @@ -97,7 +97,7 @@
> },
> /* EVEX_W_0F7A_P_1 */
> {
> - { "vcvtudq2pd", { XM, EXEvexHalfBcstXmmq }, 0 },
> + { "vcvtudq2pd", { XM, EXEvexHalfBcstXmmq, EXxEVexRIG }, 0 },
> { "vcvtuqq2pd", { XM, EXx, EXxEVexR }, 0 },
> },
> /* EVEX_W_0F7A_P_2 */
> @@ -161,7 +161,7 @@
> },
> /* EVEX_W_0FE6_P_1 */
> {
> - { "%XEvcvtdq2pd", { XM, EXEvexHalfBcstXmmq }, 0 },
> + { "%XEvcvtdq2pd", { XM, EXEvexHalfBcstXmmq, EXxEVexRIG }, 0 },
> { "vcvtqq2pd", { XM, EXx, EXxEVexR }, 0 },
> },
> /* EVEX_W_0FE7 */
> diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
> index f9b6cf30fd0..5f94f1524cc 100644
> --- a/opcodes/i386-dis.c
> +++ b/opcodes/i386-dis.c
> @@ -605,6 +605,7 @@ fetch_error (const instr_info *ins)
> #define EXxEVexR { OP_Rounding, evex_rounding_mode }
> #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
> #define EXxEVexS { OP_Rounding, evex_sae_mode }
> +#define EXxEVexRIG { OP_Rounding, evex_rounding_ignore_mode }
>
> #define MaskG { OP_G, mask_mode }
> #define MaskE { OP_E, mask_mode }
> @@ -765,6 +766,8 @@ enum
> evex_rounding_64_mode,
> /* Supress all exceptions. */
> evex_sae_mode,
> + /* Rounding allowed, but ignored. */
> + evex_rounding_ignore_mode,
>
> /* Mask register operand. */
> mask_mode,
> @@ -14289,18 +14292,19 @@ OP_Rounding (instr_info *ins, int bytemode, int
> sizeflag ATTRIBUTE_UNUSED)
> if (ins->modrm.mod != 3 || !ins->vex.b)
> return true;
>
> + ins->evex_used |= EVEX_b_used;
> switch (bytemode)
> {
> + case evex_rounding_ignore_mode:
> + return true;
> case evex_rounding_64_mode:
> if (ins->address_mode != mode_64bit || !ins->vex.w)
> return true;
> /* Fall through. */
> case evex_rounding_mode:
> - ins->evex_used |= EVEX_b_used;
> oappend (ins, names_rounding[ins->vex.ll]);
> break;
> case evex_sae_mode:
> - ins->evex_used |= EVEX_b_used;
> oappend (ins, "{");
> break;
> default:
> --
> 2.31.1
>
>
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