[PATCH v3] Support Intel MOVRS
Haochen Jiang
haochen.jiang@intel.com
Mon Jan 13 07:18:46 GMT 2025
From: "Hu, Lin1" <lin1.hu@intel.com>
Hi all,
This is the v3 patch for MOVRS. Changes and patch descrption are embedded
below.
Ok for trunk?
Thx,
Haochen
Note: The documentation will use EVEX.W0 for r8 MOVRS APX_F extension.
I choose to send out the patch as WIG since it makes sense and aligns with
previous ones. If it has to be W0 eventually, we could add W0 afterwards
as a bug fix. But let's go with WIG first.
---
Changes in v3:
- Remove MOD_TABLE table pass for M* operands except for prefetchrst2
since OP_M would check that.
---
This patch focus on supporting MOVRS ISA. We could take this full ISA
as four part: PREFETCHRST2, MOVRS, MOVRS APX_F extension and MOVRS AVX10.2
extension.
The APX_F extension for MOVRS will be:
- EVEX.LLZ.NP.MAP4.WIG 8A !(11):rrr:bbb for r8/m8 with NF=0 and
ND=0
- EVEX.LLZ.NP/66.MAP4.SCALABLE 8B !(11):rrr:bbb for rv/mv with NF=0
and ND=0
The documentation will use EVEX.W0 for r8 MOVRS APX_F extension.
In this patch, we treated as WIG since it makes sense and aligns with
previous ones. If it has to be W0 eventually, we could add W0 afterwards
as a bug fix.
We did not merge the table together for APX_F since there is an explicit
x64 for movrs insn. Also, the space is different for legacy and apx_f forms.
---
Changes in v2:
- Combine the insn entry in i386-opc.tbl by using W.
- Remove W0 restriction in disassembler.
- Use the same source for suffix testcases as non-suffix testcases.
---
gas/ChangeLog:
* NEWS: Support Intel MOVRS.
* config/tc-i386.c: Add MOVRS.
* doc/c-i386.texi: Document .movrs.
* testsuite/gas/i386/i386.exp: Run MOVRS tests.
* testsuite/gas/i386/x86-64.exp: Ditto.
* testsuite/gas/i386/x86-64-apx-evex-promoted-intel.d: Add MOVRS
tests.
* testsuite/gas/i386/x86-64-apx-evex-promoted-wig.d: Ditto.
* testsuite/gas/i386/x86-64-apx-evex-promoted.d: Ditto.
* testsuite/gas/i386/x86-64-apx-evex-promoted.s: Ditto.
* testsuite/gas/i386/lfence-load.d: Add prefetchrst2.
* testsuite/gas/i386/lfence-load.s: Ditto.
* testsuite/gas/i386/nops-8.d: Ditto.
* testsuite/gas/i386/prefetch-intel.d: Ditto.
* testsuite/gas/i386/prefetch.d: Ditto.
* testsuite/gas/i386/x86-64-lfence-load.d: Ditto.
* testsuite/gas/i386/x86-64-lfence-load.s: Ditto.
* testsuite/gas/i386/x86-64-prefetch-intel.d: Ditto.
* testsuite/gas/i386/x86-64-prefetch.d: Ditto.
* testsuite/gas/i386/movrs-intel.d: New test.
* testsuite/gas/i386/movrs-inval.l: Ditto.
* testsuite/gas/i386/movrs-inval.s: Ditto.
* testsuite/gas/i386/movrs.d: Ditto.
* testsuite/gas/i386/movrs.s: Ditto.
* testsuite/gas/i386/x86-64-movrs-avx10_2-256-intel.d: Ditto.
* testsuite/gas/i386/x86-64-movrs-avx10_2-256.d: Ditto.
* testsuite/gas/i386/x86-64-movrs-avx10_2-256.s: Ditto.
* testsuite/gas/i386/x86-64-movrs-avx10_2-512-intel.d: Ditto.
* testsuite/gas/i386/x86-64-movrs-avx10_2-512.d: Ditto.
* testsuite/gas/i386/x86-64-movrs-avx10_2-512.s: Ditto.
* testsuite/gas/i386/x86-64-movrs-intel.d: Ditto.
* testsuite/gas/i386/x86-64-movrs.d: Ditto.
* testsuite/gas/i386/x86-64-movrs.s: Ditto.
* testsuite/gas/i386/x86-64-movrs-intel-suffix.d: Ditto.
* testsuite/gas/i386/x86-64-movrs-suffix.d: Ditto.
* testsuite/gas/i386/x86-64-movrs-suffix.s: Ditto.
opcodes/ChangeLog:
* i386-dis-evex-prefix.h: Add PREFIX_EVEX_MAP5_6F_X86_64.
* i386-dis-evex-x86.h: Add X86_64_EVEX_MAP5_6F.
* i386-dis-evex.h (evex_table): New entry for movrs.
* i386-dis.c (MOD_0F18_REG_4): New.
(PREFIX_EVEX_MAP5_6F_X86_64): Ditto.
(X86_64_0F388A): Ditto.
(X86_64_0F388B): Ditto.
(X86_64_EVEX_MAP5_6F): Ditto.
(three_byte_table): New entry for MOVRS.
(reg_table): Ditto.
(mod_table): Ditto.
(x86_64_table): Ditto. Also include i386-dis-evex-x86.h.
* i386-gen.c (cpu_flags): Add MOVRS.
* i386-init.h: Regenerated.
* i386-mnem.h: Ditto.
* i386-opc.h (i386_cpu_flags): Add cpumovrs.
* i386-opc.tbl: Add MOVRS instrctions.
* i386-tbl.h: Regenerated.
Co-authored-by: Haochen Jiang <haochen.jiang@intel.com>
Co-authored-by: Lili Cui <lili.cui@intel.com>
---
gas/NEWS | 2 +
gas/config/tc-i386.c | 1 +
gas/doc/c-i386.texi | 2 +
gas/testsuite/gas/i386/i386.exp | 3 +
gas/testsuite/gas/i386/lfence-load.d | 1 +
gas/testsuite/gas/i386/lfence-load.s | 1 +
gas/testsuite/gas/i386/movrs-intel.d | 15 +
gas/testsuite/gas/i386/movrs-inval.l | 9 +
gas/testsuite/gas/i386/movrs-inval.s | 12 +
gas/testsuite/gas/i386/movrs.d | 13 +
gas/testsuite/gas/i386/movrs.s | 15 +
gas/testsuite/gas/i386/nops-8.d | 8 +-
gas/testsuite/gas/i386/prefetch-intel.d | 2 +-
gas/testsuite/gas/i386/prefetch.d | 2 +-
.../gas/i386/x86-64-apx-evex-promoted-intel.d | 8 +
.../gas/i386/x86-64-apx-evex-promoted-wig.d | 8 +
.../gas/i386/x86-64-apx-evex-promoted.d | 8 +
.../gas/i386/x86-64-apx-evex-promoted.s | 8 +
gas/testsuite/gas/i386/x86-64-lfence-load.d | 1 +
gas/testsuite/gas/i386/x86-64-lfence-load.s | 1 +
.../gas/i386/x86-64-movrs-avx10_2-256-intel.d | 27 +
.../gas/i386/x86-64-movrs-avx10_2-256.d | 25 +
.../gas/i386/x86-64-movrs-avx10_2-256.s | 41 +
.../gas/i386/x86-64-movrs-avx10_2-512-intel.d | 27 +
.../gas/i386/x86-64-movrs-avx10_2-512.d | 25 +
.../gas/i386/x86-64-movrs-avx10_2-512.s | 41 +
gas/testsuite/gas/i386/x86-64-movrs-intel.d | 31 +
.../gas/i386/x86-64-movrs-suffix-intel.d | 15 +
gas/testsuite/gas/i386/x86-64-movrs-suffix.d | 13 +
gas/testsuite/gas/i386/x86-64-movrs-suffix.s | 15 +
gas/testsuite/gas/i386/x86-64-movrs.d | 29 +
gas/testsuite/gas/i386/x86-64-movrs.s | 47 +
.../gas/i386/x86-64-prefetch-intel.d | 2 +-
gas/testsuite/gas/i386/x86-64-prefetch.d | 2 +-
gas/testsuite/gas/i386/x86-64.exp | 6 +
opcodes/i386-dis-evex-prefix.h | 7 +
opcodes/i386-dis-evex-x86-64.h | 5 +
opcodes/i386-dis-evex.h | 6 +-
opcodes/i386-dis.c | 31 +-
opcodes/i386-gen.c | 1 +
opcodes/i386-init.h | 716 +--
opcodes/i386-mnem.h | 4304 +++++++++--------
opcodes/i386-opc.h | 3 +
opcodes/i386-opc.tbl | 12 +
opcodes/i386-tbl.h | 356 +-
45 files changed, 3250 insertions(+), 2657 deletions(-)
create mode 100644 gas/testsuite/gas/i386/movrs-intel.d
create mode 100644 gas/testsuite/gas/i386/movrs-inval.l
create mode 100644 gas/testsuite/gas/i386/movrs-inval.s
create mode 100644 gas/testsuite/gas/i386/movrs.d
create mode 100644 gas/testsuite/gas/i386/movrs.s
create mode 100644 gas/testsuite/gas/i386/x86-64-movrs-avx10_2-256-intel.d
create mode 100644 gas/testsuite/gas/i386/x86-64-movrs-avx10_2-256.d
create mode 100644 gas/testsuite/gas/i386/x86-64-movrs-avx10_2-256.s
create mode 100644 gas/testsuite/gas/i386/x86-64-movrs-avx10_2-512-intel.d
create mode 100644 gas/testsuite/gas/i386/x86-64-movrs-avx10_2-512.d
create mode 100644 gas/testsuite/gas/i386/x86-64-movrs-avx10_2-512.s
create mode 100644 gas/testsuite/gas/i386/x86-64-movrs-intel.d
create mode 100644 gas/testsuite/gas/i386/x86-64-movrs-suffix-intel.d
create mode 100644 gas/testsuite/gas/i386/x86-64-movrs-suffix.d
create mode 100644 gas/testsuite/gas/i386/x86-64-movrs-suffix.s
create mode 100644 gas/testsuite/gas/i386/x86-64-movrs.d
create mode 100644 gas/testsuite/gas/i386/x86-64-movrs.s
create mode 100644 opcodes/i386-dis-evex-x86-64.h
diff --git a/gas/NEWS b/gas/NEWS
index 5c8975dbc44..00616889502 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,5 +1,7 @@
-*- text -*-
+* Add support for the x86 Intel MOVRS instructions.
+
* Add support for the x86 Zhaoxin PadLock RNG2 instruction.
* Add support for AArch64 SME and SVE non-widening BFloat16 (SVE_B16B16 and
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index af1b9988dd8..977646be64f 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -1226,6 +1226,7 @@ static const arch_entry cpu_arch[] =
SUBARCH (gmi, GMI, GMI, false),
SUBARCH (msr_imm, MSR_IMM, MSR_IMM, false),
SUBARCH (padlockrng2, PADLOCKRNG2, PADLOCKRNG2, false),
+ SUBARCH (movrs, MOVRS, MOVRS, false),
};
#undef SUBARCH
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index 20e21405053..e104a821f84 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -224,6 +224,7 @@ accept various extension mnemonics. For example,
@code{avx10.2/512},
@code{avx10.2/256},
@code{avx10.2/128},
+@code{movrs},
@code{amx_int8},
@code{amx_bf16},
@code{amx_fp16},
@@ -1700,6 +1701,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
@item @samp{.avx_ne_convert} @tab @samp{.rao_int} @tab @samp{.fred} @tab @samp{.lkgs}
@item @samp{.avx_vnni_int16} @tab @samp{.sha512} @tab @samp{.sm3} @tab @samp{.sm4}
@item @samp{.pbndkb} @tab @samp{.user_msr} @tab @samp{.msr_imm} @tab @samp{.avx10.2}
+@item @samp{.movrs}
@item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}
@item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
@item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk}
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index fed9283d4ed..e6e10f0e1a2 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -542,6 +542,9 @@ if [gas_32_check] then {
run_dump_test "avx10_2-512-sm4"
run_dump_test "avx10_2-512-sm4-intel"
run_list_test "avx10_2-sm4-inval"
+ run_dump_test "movrs"
+ run_dump_test "movrs-intel"
+ run_list_test "movrs-inval"
run_list_test "sg"
run_dump_test "clzero"
run_dump_test "invlpgb"
diff --git a/gas/testsuite/gas/i386/lfence-load.d b/gas/testsuite/gas/i386/lfence-load.d
index a315be75254..4bed6001644 100644
--- a/gas/testsuite/gas/i386/lfence-load.d
+++ b/gas/testsuite/gas/i386/lfence-load.d
@@ -33,6 +33,7 @@ Disassembly of section .text:
+[a-f0-9]+: 0f 18 55 00 prefetcht1 0x0\(%ebp\)
+[a-f0-9]+: 0f 18 5d 00 prefetcht2 0x0\(%ebp\)
+[a-f0-9]+: 0f 0d 4d 00 prefetchw 0x0\(%ebp\)
+ +[a-f0-9]+: 0f 18 65 00 prefetchrst2 0x0\(%ebp\)
+[a-f0-9]+: 1f pop %ds
+[a-f0-9]+: 0f ae e8 lfence
+[a-f0-9]+: 9d popf
diff --git a/gas/testsuite/gas/i386/lfence-load.s b/gas/testsuite/gas/i386/lfence-load.s
index 4b4aa1610b3..157ee28f28b 100644
--- a/gas/testsuite/gas/i386/lfence-load.s
+++ b/gas/testsuite/gas/i386/lfence-load.s
@@ -20,6 +20,7 @@ _start:
prefetcht1 (%ebp)
prefetcht2 (%ebp)
prefetchw (%ebp)
+ prefetchrst2 (%ebp)
pop %ds
popf
popa
diff --git a/gas/testsuite/gas/i386/movrs-intel.d b/gas/testsuite/gas/i386/movrs-intel.d
new file mode 100644
index 00000000000..ae7f750711d
--- /dev/null
+++ b/gas/testsuite/gas/i386/movrs-intel.d
@@ -0,0 +1,15 @@
+#objdump: -dw -Mintel
+#name: i386 MOVRS insns (Intel disassembly)
+#source: movrs.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+#...
+[a-f0-9]+ <_intel>:
+\s*[a-f0-9]+:\s*0f 18 a4 f4 00 00 00 10\s+prefetchrst2 BYTE PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*0f 18 21\s+prefetchrst2 BYTE PTR \[ecx\]
+\s*[a-f0-9]+:\s*0f 18 61 7f\s+prefetchrst2 BYTE PTR \[ecx\+0x7f\]
+\s*[a-f0-9]+:\s*0f 18 62 80\s+prefetchrst2 BYTE PTR \[edx-0x80\]
+#pass
diff --git a/gas/testsuite/gas/i386/movrs-inval.l b/gas/testsuite/gas/i386/movrs-inval.l
new file mode 100644
index 00000000000..43af5a158c1
--- /dev/null
+++ b/gas/testsuite/gas/i386/movrs-inval.l
@@ -0,0 +1,9 @@
+.* Assembler messages:
+.*:5: Error: `movrs' is only supported in 64-bit mode
+.*:6: Error: `movrs' is only supported in 64-bit mode
+.*:7: Error: `movrs' is only supported in 64-bit mode
+.*:8: Error: `movrs' is only supported in 64-bit mode
+.*:9: Error: `vmovrsb' is only supported in 64-bit mode
+.*:10: Error: `vmovrsd' is only supported in 64-bit mode
+.*:11: Error: `vmovrsq' is only supported in 64-bit mode
+.*:12: Error: `vmovrsw' is only supported in 64-bit mode
diff --git a/gas/testsuite/gas/i386/movrs-inval.s b/gas/testsuite/gas/i386/movrs-inval.s
new file mode 100644
index 00000000000..9236bf3d4eb
--- /dev/null
+++ b/gas/testsuite/gas/i386/movrs-inval.s
@@ -0,0 +1,12 @@
+# Check Illegal 32bit MOVRS instructions
+
+ .text
+_start:
+ movrs 0x10000000(%esp, %esi, 8), %dx
+ movrs 0x10000000(%esp, %esi, 8), %edx
+ movrs 0x10000000(%esp, %esi, 8), %r12
+ movrs 0x10000000(%esp, %esi, 8), %bl
+ vmovrsb 0x10000000(%esp, %esi, 8), %zmm6{%k7}
+ vmovrsd 0x10000000(%esp, %esi, 8), %zmm6{%k7}
+ vmovrsq 0x10000000(%esp, %esi, 8), %zmm6{%k7}
+ vmovrsw 0x10000000(%esp, %esi, 8), %zmm6{%k7}
diff --git a/gas/testsuite/gas/i386/movrs.d b/gas/testsuite/gas/i386/movrs.d
new file mode 100644
index 00000000000..5b2bb45b57c
--- /dev/null
+++ b/gas/testsuite/gas/i386/movrs.d
@@ -0,0 +1,13 @@
+#objdump: -dw
+#name: i386 MOVRS insns
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*0f 18 a4 f4 00 00 00 10\s+prefetchrst2 0x10000000\(%esp,%esi,8\)
+\s*[a-f0-9]+:\s*0f 18 21\s+prefetchrst2 \(%ecx\)
+\s*[a-f0-9]+:\s*0f 18 61 7f\s+prefetchrst2 0x7f\(%ecx\)
+\s*[a-f0-9]+:\s*0f 18 62 80\s+prefetchrst2 -0x80\(%edx\)
+#pass
diff --git a/gas/testsuite/gas/i386/movrs.s b/gas/testsuite/gas/i386/movrs.s
new file mode 100644
index 00000000000..e9592830296
--- /dev/null
+++ b/gas/testsuite/gas/i386/movrs.s
@@ -0,0 +1,15 @@
+# Check 32bit MOVRS instructions
+
+ .text
+_start:
+ prefetchrst2 0x10000000(%esp, %esi, 8)
+ prefetchrst2 (%ecx)
+ prefetchrst2 127(%ecx)
+ prefetchrst2 -128(%edx)
+
+_intel:
+ .intel_syntax noprefix
+ prefetchrst2 BYTE PTR [esp+esi*8+0x10000000]
+ prefetchrst2 BYTE PTR [ecx]
+ prefetchrst2 BYTE PTR [ecx+127]
+ prefetchrst2 BYTE PTR [edx-128]
diff --git a/gas/testsuite/gas/i386/nops-8.d b/gas/testsuite/gas/i386/nops-8.d
index 2d99ac7e51b..d0be54d2aac 100644
--- a/gas/testsuite/gas/i386/nops-8.d
+++ b/gas/testsuite/gas/i386/nops-8.d
@@ -74,7 +74,7 @@ Disassembly of section .text:
+[a-f0-9]+: 0f 18 08 prefetcht0 \(%eax\)
+[a-f0-9]+: 0f 18 10 prefetcht1 \(%eax\)
+[a-f0-9]+: 0f 18 18 prefetcht2 \(%eax\)
- +[a-f0-9]+: 0f 18 20 nopl \(%eax\)
+ +[a-f0-9]+: 0f 18 20 prefetchrst2 \(%eax\)
+[a-f0-9]+: 0f 18 28 nopl \(%eax\)
+[a-f0-9]+: 0f 18 30 nopl \(%eax\)
+[a-f0-9]+: 0f 18 38 nopl \(%eax\)
@@ -146,7 +146,7 @@ Disassembly of section .text:
+[a-f0-9]+: 66 0f 18 08 data16 prefetcht0 \(%eax\)
+[a-f0-9]+: 66 0f 18 10 data16 prefetcht1 \(%eax\)
+[a-f0-9]+: 66 0f 18 18 data16 prefetcht2 \(%eax\)
- +[a-f0-9]+: 66 0f 18 20 nopw \(%eax\)
+ +[a-f0-9]+: 66 0f 18 20 data16 prefetchrst2 \(%eax\)
+[a-f0-9]+: 66 0f 18 28 nopw \(%eax\)
+[a-f0-9]+: 66 0f 18 30 nopw \(%eax\)
+[a-f0-9]+: 66 0f 18 38 nopw \(%eax\)
@@ -218,7 +218,7 @@ Disassembly of section .text:
+[a-f0-9]+: f3 0f 18 08 repz prefetcht0 \(%eax\)
+[a-f0-9]+: f3 0f 18 10 repz prefetcht1 \(%eax\)
+[a-f0-9]+: f3 0f 18 18 repz prefetcht2 \(%eax\)
- +[a-f0-9]+: f3 0f 18 20 repz nopl \(%eax\)
+ +[a-f0-9]+: f3 0f 18 20 repz prefetchrst2 \(%eax\)
+[a-f0-9]+: f3 0f 18 28 repz nopl \(%eax\)
+[a-f0-9]+: f3 0f 18 30 repz nopl \(%eax\)
+[a-f0-9]+: f3 0f 18 38 repz nopl \(%eax\)
@@ -290,7 +290,7 @@ Disassembly of section .text:
+[a-f0-9]+: f2 0f 18 08 repnz prefetcht0 \(%eax\)
+[a-f0-9]+: f2 0f 18 10 repnz prefetcht1 \(%eax\)
+[a-f0-9]+: f2 0f 18 18 repnz prefetcht2 \(%eax\)
- +[a-f0-9]+: f2 0f 18 20 repnz nopl \(%eax\)
+ +[a-f0-9]+: f2 0f 18 20 repnz prefetchrst2 \(%eax\)
+[a-f0-9]+: f2 0f 18 28 repnz nopl \(%eax\)
+[a-f0-9]+: f2 0f 18 30 repnz nopl \(%eax\)
+[a-f0-9]+: f2 0f 18 38 repnz nopl \(%eax\)
diff --git a/gas/testsuite/gas/i386/prefetch-intel.d b/gas/testsuite/gas/i386/prefetch-intel.d
index ca0fd914515..1a6fad15c73 100644
--- a/gas/testsuite/gas/i386/prefetch-intel.d
+++ b/gas/testsuite/gas/i386/prefetch-intel.d
@@ -22,7 +22,7 @@ Disassembly of section .text:
\s*[a-f0-9]+: 0f 18 08 prefetcht0 BYTE PTR \[eax\]
\s*[a-f0-9]+: 0f 18 10 prefetcht1 BYTE PTR \[eax\]
\s*[a-f0-9]+: 0f 18 18 prefetcht2 BYTE PTR \[eax\]
-\s*[a-f0-9]+: 0f 18 20 nop DWORD PTR \[eax\]
+\s*[a-f0-9]+: 0f 18 20 prefetchrst2 BYTE PTR \[eax\]
\s*[a-f0-9]+: 0f 18 28 nop DWORD PTR \[eax\]
\s*[a-f0-9]+: 0f 18 30 nop DWORD PTR \[eax\]
\s*[a-f0-9]+: 0f 18 38 nop DWORD PTR \[eax\]
diff --git a/gas/testsuite/gas/i386/prefetch.d b/gas/testsuite/gas/i386/prefetch.d
index 285077862a7..f46c1410e94 100644
--- a/gas/testsuite/gas/i386/prefetch.d
+++ b/gas/testsuite/gas/i386/prefetch.d
@@ -21,7 +21,7 @@ Disassembly of section .text:
\s*[a-f0-9]+: 0f 18 08 prefetcht0 \(%eax\)
\s*[a-f0-9]+: 0f 18 10 prefetcht1 \(%eax\)
\s*[a-f0-9]+: 0f 18 18 prefetcht2 \(%eax\)
-\s*[a-f0-9]+: 0f 18 20 nopl \(%eax\)
+\s*[a-f0-9]+: 0f 18 20 prefetchrst2 \(%eax\)
\s*[a-f0-9]+: 0f 18 28 nopl \(%eax\)
\s*[a-f0-9]+: 0f 18 30 nopl \(%eax\)
\s*[a-f0-9]+: 0f 18 38 nopl \(%eax\)
diff --git a/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-intel.d b/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-intel.d
index d45167e318c..a782cd373b5 100644
--- a/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-intel.d
+++ b/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-intel.d
@@ -118,6 +118,10 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 4c 7d 08 f8 bc 87 23 01 00 00[ ]+movdir64b[ ]+r31,\[r31\+rax\*4\+0x123\]
[ ]*[a-f0-9]+:[ ]*62 4c 7c 08 f9 8c 87 23 01 00 00[ ]+movdiri[ ]+DWORD PTR \[r31\+rax\*4\+0x123\],r25d
[ ]*[a-f0-9]+:[ ]*62 4c fc 08 f9 bc 87 23 01 00 00[ ]+movdiri[ ]+QWORD PTR \[r31\+rax\*4\+0x123\],r31
+[ ]*[a-f0-9]+:[ ]*62 cc 7c 08 8a 84 87 23 01 00 00[ ]+movrs[ ]+r16b,BYTE PTR \[r31\+rax\*4\+0x123\]
+[ ]*[a-f0-9]+:[ ]*62 ec 7d 08 8b 94 80 23 01 00 00[ ]+movrs[ ]+r18w,WORD PTR \[r16\+rax\*4\+0x123\]
+[ ]*[a-f0-9]+:[ ]*62 4c 7c 08 8b 8c 87 23 01 00 00[ ]+movrs[ ]+r25d,DWORD PTR \[r31\+rax\*4\+0x123\]
+[ ]*[a-f0-9]+:[ ]*62 6c fc 08 8b bc 80 23 01 00 00[ ]+movrs[ ]+r31,QWORD PTR \[r16\+rax\*4\+0x123\]
[ ]*[a-f0-9]+:[ ]*62 5a 6f 08 f5 d1[ ]+pdep[ ]+r10d,edx,r25d
[ ]*[a-f0-9]+:[ ]*62 5a 87 08 f5 df[ ]+pdep[ ]+r11,r15,r31
[ ]*[a-f0-9]+:[ ]*62 da 37 00 f5 94 87 23 01 00 00[ ]+pdep[ ]+edx,r25d,DWORD PTR \[r31\+rax\*4\+0x123\]
@@ -253,6 +257,10 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 4c 7d 08 f8 bc 87 23 01 00 00[ ]+movdir64b[ ]+r31,\[r31\+rax\*4\+0x123\]
[ ]*[a-f0-9]+:[ ]*62 4c 7c 08 f9 8c 87 23 01 00 00[ ]+movdiri[ ]+DWORD PTR \[r31\+rax\*4\+0x123\],r25d
[ ]*[a-f0-9]+:[ ]*62 4c fc 08 f9 bc 87 23 01 00 00[ ]+movdiri[ ]+QWORD PTR \[r31\+rax\*4\+0x123\],r31
+[ ]*[a-f0-9]+:[ ]*62 cc 7c 08 8a 84 87 23 01 00 00[ ]+movrs[ ]+r16b,BYTE PTR \[r31\+rax\*4\+0x123\]
+[ ]*[a-f0-9]+:[ ]*62 ec 7d 08 8b 94 80 23 01 00 00[ ]+movrs[ ]+r18w,WORD PTR \[r16\+rax\*4\+0x123\]
+[ ]*[a-f0-9]+:[ ]*62 4c 7c 08 8b 8c 87 23 01 00 00[ ]+movrs[ ]+r25d,DWORD PTR \[r31\+rax\*4\+0x123\]
+[ ]*[a-f0-9]+:[ ]*62 6c fc 08 8b bc 80 23 01 00 00[ ]+movrs[ ]+r31,QWORD PTR \[r16\+rax\*4\+0x123\]
[ ]*[a-f0-9]+:[ ]*62 5a 6f 08 f5 d1[ ]+pdep[ ]+r10d,edx,r25d
[ ]*[a-f0-9]+:[ ]*62 5a 87 08 f5 df[ ]+pdep[ ]+r11,r15,r31
[ ]*[a-f0-9]+:[ ]*62 da 37 00 f5 94 87 23 01 00 00[ ]+pdep[ ]+edx,r25d,DWORD PTR \[r31\+rax\*4\+0x123\]
diff --git a/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-wig.d b/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-wig.d
index fa6d66b5dda..ac98dfc09b8 100644
--- a/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-wig.d
+++ b/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-wig.d
@@ -118,6 +118,10 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 4c .d 08 f8 bc 87 23 01 00 00[ ]+movdir64b[ ]+0x123\(%r31,%rax,4\),%r31
[ ]*[a-f0-9]+:[ ]*62 4c 7c 08 f9 8c 87 23 01 00 00[ ]+movdiri[ ]+%r25d,0x123\(%r31,%rax,4\)
[ ]*[a-f0-9]+:[ ]*62 4c fc 08 f9 bc 87 23 01 00 00[ ]+movdiri[ ]+%r31,0x123\(%r31,%rax,4\)
+[ ]*[a-f0-9]+:[ ]*62 cc fc 08 8a 84 87 23 01 00 00[ ]+movrs[ ]+0x123\(%r31,%rax,4\),%r16b
+[ ]*[a-f0-9]+:[ ]*62 ec 7d 08 8b 94 80 23 01 00 00[ ]+movrs[ ]+0x123\(%r16,%rax,4\),%r18w
+[ ]*[a-f0-9]+:[ ]*62 4c 7c 08 8b 8c 87 23 01 00 00[ ]+movrs[ ]+0x123\(%r31,%rax,4\),%r25d
+[ ]*[a-f0-9]+:[ ]*62 6c fc 08 8b bc 80 23 01 00 00[ ]+movrs[ ]+0x123\(%r16,%rax,4\),%r31
[ ]*[a-f0-9]+:[ ]*62 5a 6f 08 f5 d1[ ]+pdep[ ]+%r25d,%edx,%r10d
[ ]*[a-f0-9]+:[ ]*62 5a 87 08 f5 df[ ]+pdep[ ]+%r31,%r15,%r11
[ ]*[a-f0-9]+:[ ]*62 da 37 00 f5 94 87 23 01 00 00[ ]+pdep[ ]+0x123\(%r31,%rax,4\),%r25d,%edx
@@ -253,6 +257,10 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 4c .d 08 f8 bc 87 23 01 00 00[ ]+movdir64b[ ]+0x123\(%r31,%rax,4\),%r31
[ ]*[a-f0-9]+:[ ]*62 4c 7c 08 f9 8c 87 23 01 00 00[ ]+movdiri[ ]+%r25d,0x123\(%r31,%rax,4\)
[ ]*[a-f0-9]+:[ ]*62 4c fc 08 f9 bc 87 23 01 00 00[ ]+movdiri[ ]+%r31,0x123\(%r31,%rax,4\)
+[ ]*[a-f0-9]+:[ ]*62 cc fc 08 8a 84 87 23 01 00 00[ ]+movrs[ ]+0x123\(%r31,%rax,4\),%r16b
+[ ]*[a-f0-9]+:[ ]*62 ec 7d 08 8b 94 80 23 01 00 00[ ]+movrs[ ]+0x123\(%r16,%rax,4\),%r18w
+[ ]*[a-f0-9]+:[ ]*62 4c 7c 08 8b 8c 87 23 01 00 00[ ]+movrs[ ]+0x123\(%r31,%rax,4\),%r25d
+[ ]*[a-f0-9]+:[ ]*62 6c fc 08 8b bc 80 23 01 00 00[ ]+movrs[ ]+0x123\(%r16,%rax,4\),%r31
[ ]*[a-f0-9]+:[ ]*62 5a 6f 08 f5 d1[ ]+pdep[ ]+%r25d,%edx,%r10d
[ ]*[a-f0-9]+:[ ]*62 5a 87 08 f5 df[ ]+pdep[ ]+%r31,%r15,%r11
[ ]*[a-f0-9]+:[ ]*62 da 37 00 f5 94 87 23 01 00 00[ ]+pdep[ ]+0x123\(%r31,%rax,4\),%r25d,%edx
diff --git a/gas/testsuite/gas/i386/x86-64-apx-evex-promoted.d b/gas/testsuite/gas/i386/x86-64-apx-evex-promoted.d
index ba684c1b0c6..6aad9b34e9d 100644
--- a/gas/testsuite/gas/i386/x86-64-apx-evex-promoted.d
+++ b/gas/testsuite/gas/i386/x86-64-apx-evex-promoted.d
@@ -118,6 +118,10 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 4c 7d 08 f8 bc 87 23 01 00 00[ ]+movdir64b[ ]+0x123\(%r31,%rax,4\),%r31
[ ]*[a-f0-9]+:[ ]*62 4c 7c 08 f9 8c 87 23 01 00 00[ ]+movdiri[ ]+%r25d,0x123\(%r31,%rax,4\)
[ ]*[a-f0-9]+:[ ]*62 4c fc 08 f9 bc 87 23 01 00 00[ ]+movdiri[ ]+%r31,0x123\(%r31,%rax,4\)
+[ ]*[a-f0-9]+:[ ]*62 cc 7c 08 8a 84 87 23 01 00 00[ ]+movrs[ ]+0x123\(%r31,%rax,4\),%r16b
+[ ]*[a-f0-9]+:[ ]*62 ec 7d 08 8b 94 80 23 01 00 00[ ]+movrs[ ]+0x123\(%r16,%rax,4\),%r18w
+[ ]*[a-f0-9]+:[ ]*62 4c 7c 08 8b 8c 87 23 01 00 00[ ]+movrs[ ]+0x123\(%r31,%rax,4\),%r25d
+[ ]*[a-f0-9]+:[ ]*62 6c fc 08 8b bc 80 23 01 00 00[ ]+movrs[ ]+0x123\(%r16,%rax,4\),%r31
[ ]*[a-f0-9]+:[ ]*62 5a 6f 08 f5 d1[ ]+pdep[ ]+%r25d,%edx,%r10d
[ ]*[a-f0-9]+:[ ]*62 5a 87 08 f5 df[ ]+pdep[ ]+%r31,%r15,%r11
[ ]*[a-f0-9]+:[ ]*62 da 37 00 f5 94 87 23 01 00 00[ ]+pdep[ ]+0x123\(%r31,%rax,4\),%r25d,%edx
@@ -253,6 +257,10 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 4c 7d 08 f8 bc 87 23 01 00 00[ ]+movdir64b[ ]+0x123\(%r31,%rax,4\),%r31
[ ]*[a-f0-9]+:[ ]*62 4c 7c 08 f9 8c 87 23 01 00 00[ ]+movdiri[ ]+%r25d,0x123\(%r31,%rax,4\)
[ ]*[a-f0-9]+:[ ]*62 4c fc 08 f9 bc 87 23 01 00 00[ ]+movdiri[ ]+%r31,0x123\(%r31,%rax,4\)
+[ ]*[a-f0-9]+:[ ]*62 cc 7c 08 8a 84 87 23 01 00 00[ ]+movrs[ ]+0x123\(%r31,%rax,4\),%r16b
+[ ]*[a-f0-9]+:[ ]*62 ec 7d 08 8b 94 80 23 01 00 00[ ]+movrs[ ]+0x123\(%r16,%rax,4\),%r18w
+[ ]*[a-f0-9]+:[ ]*62 4c 7c 08 8b 8c 87 23 01 00 00[ ]+movrs[ ]+0x123\(%r31,%rax,4\),%r25d
+[ ]*[a-f0-9]+:[ ]*62 6c fc 08 8b bc 80 23 01 00 00[ ]+movrs[ ]+0x123\(%r16,%rax,4\),%r31
[ ]*[a-f0-9]+:[ ]*62 5a 6f 08 f5 d1[ ]+pdep[ ]+%r25d,%edx,%r10d
[ ]*[a-f0-9]+:[ ]*62 5a 87 08 f5 df[ ]+pdep[ ]+%r31,%r15,%r11
[ ]*[a-f0-9]+:[ ]*62 da 37 00 f5 94 87 23 01 00 00[ ]+pdep[ ]+0x123\(%r31,%rax,4\),%r25d,%edx
diff --git a/gas/testsuite/gas/i386/x86-64-apx-evex-promoted.s b/gas/testsuite/gas/i386/x86-64-apx-evex-promoted.s
index 3fc9832a84b..83bc9407da3 100644
--- a/gas/testsuite/gas/i386/x86-64-apx-evex-promoted.s
+++ b/gas/testsuite/gas/i386/x86-64-apx-evex-promoted.s
@@ -112,6 +112,10 @@ _start:
movdir64b 0x123(%r31,%rax,4),%r31
movdiri %r25d,0x123(%r31,%rax,4)
movdiri %r31,0x123(%r31,%rax,4)
+ movrs 0x123(%r31,%rax,4),%r16b
+ movrs 0x123(%r16,%rax,4),%r18w
+ movrs 0x123(%r31,%rax,4),%r25d
+ movrs 0x123(%r16,%rax,4),%r31
pdep %r25d,%edx,%r10d
pdep %r31,%r15,%r11
pdep 0x123(%r31,%rax,4),%r25d,%edx
@@ -249,6 +253,10 @@ _start:
movdir64b r31,[r31+rax*4+0x123]
movdiri DWORD PTR [r31+rax*4+0x123],r25d
movdiri QWORD PTR [r31+rax*4+0x123],r31
+ movrs r16b,BYTE PTR [r31+rax*4+0x123]
+ movrs r18w,WORD PTR [r16+rax*4+0x123]
+ movrs r25d,DWORD PTR [r31+rax*4+0x123]
+ movrs r31,QWORD PTR [r16+rax*4+0x123]
pdep r10d,edx,r25d
pdep r11,r15,r31
pdep edx,r25d,DWORD PTR [r31+rax*4+0x123]
diff --git a/gas/testsuite/gas/i386/x86-64-lfence-load.d b/gas/testsuite/gas/i386/x86-64-lfence-load.d
index dcfa810a513..c86155ec516 100644
--- a/gas/testsuite/gas/i386/x86-64-lfence-load.d
+++ b/gas/testsuite/gas/i386/x86-64-lfence-load.d
@@ -35,6 +35,7 @@ Disassembly of section .text:
+[a-f0-9]+: 0f 0d 4d 00 prefetchw 0x0\(%rbp\)
+[a-f0-9]+: 0f 18 3d 78 56 34 12 prefetchit0 0x12345678\(%rip\) # [0-9a-f]+ <_start\+0x[0-9a-f]+>
+[a-f0-9]+: 0f 18 35 78 56 34 12 prefetchit1 0x12345678\(%rip\) # [0-9a-f]+ <_start\+0x[0-9a-f]+>
+ +[a-f0-9]+: 0f 18 65 00 prefetchrst2 0x0\(%rbp\)
+[a-f0-9]+: 0f a1 pop %fs
+[a-f0-9]+: 0f ae e8 lfence
+[a-f0-9]+: 9d popf
diff --git a/gas/testsuite/gas/i386/x86-64-lfence-load.s b/gas/testsuite/gas/i386/x86-64-lfence-load.s
index 05c07adc189..e30b9a49800 100644
--- a/gas/testsuite/gas/i386/x86-64-lfence-load.s
+++ b/gas/testsuite/gas/i386/x86-64-lfence-load.s
@@ -22,6 +22,7 @@ _start:
prefetchw (%rbp)
prefetchit0 0x12345678(%rip)
prefetchit1 0x12345678(%rip)
+ prefetchrst2 (%rbp)
pop %fs
popf
xlatb (%rbx)
diff --git a/gas/testsuite/gas/i386/x86-64-movrs-avx10_2-256-intel.d b/gas/testsuite/gas/i386/x86-64-movrs-avx10_2-256-intel.d
new file mode 100644
index 00000000000..fbbc85f603e
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-movrs-avx10_2-256-intel.d
@@ -0,0 +1,27 @@
+#objdump: -dw -Mintel
+#name: x86_64 MOVRS, AVX10.2/256 insns (Intel disassembly)
+#source: x86-64-movrs-avx10_2-256.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+#...
+[a-f0-9]+ <_intel>:
+\s*[a-f0-9]+:\s*62 25 7f 0f 6f b4 f5 00 00 00 10\s+vmovrsb xmm30\{k7\},XMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*62 45 7f 08 6f 31\s+vmovrsb xmm30,XMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*62 65 7f 08 6f 71 7f\s+vmovrsb xmm30,XMMWORD PTR \[rcx\+0x7f0\]
+\s*[a-f0-9]+:\s*62 65 7f 8f 6f 72 80\s+vmovrsb xmm30\{k7\}\{z\},XMMWORD PTR \[rdx-0x800\]
+\s*[a-f0-9]+:\s*62 25 7e 0f 6f b4 f5 00 00 00 10\s+vmovrsd xmm30\{k7\},XMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*62 45 7e 08 6f 31\s+vmovrsd xmm30,XMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*62 65 7e 08 6f 71 7f\s+vmovrsd xmm30,XMMWORD PTR \[rcx\+0x7f0\]
+\s*[a-f0-9]+:\s*62 65 7e 8f 6f 72 80\s+vmovrsd xmm30\{k7\}\{z\},XMMWORD PTR \[rdx-0x800\]
+\s*[a-f0-9]+:\s*62 25 fe 0f 6f b4 f5 00 00 00 10\s+vmovrsq xmm30\{k7\},XMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*62 45 fe 08 6f 31\s+vmovrsq xmm30,XMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*62 65 fe 08 6f 71 7f\s+vmovrsq xmm30,XMMWORD PTR \[rcx\+0x7f0\]
+\s*[a-f0-9]+:\s*62 65 fe 8f 6f 72 80\s+vmovrsq xmm30\{k7\}\{z\},XMMWORD PTR \[rdx-0x800\]
+\s*[a-f0-9]+:\s*62 25 ff 0f 6f b4 f5 00 00 00 10\s+vmovrsw xmm30\{k7\},XMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*62 45 ff 08 6f 31\s+vmovrsw xmm30,XMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*62 65 ff 08 6f 71 7f\s+vmovrsw xmm30,XMMWORD PTR \[rcx\+0x7f0\]
+\s*[a-f0-9]+:\s*62 65 ff 8f 6f 72 80\s+vmovrsw xmm30\{k7\}\{z\},XMMWORD PTR \[rdx-0x800\]
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-movrs-avx10_2-256.d b/gas/testsuite/gas/i386/x86-64-movrs-avx10_2-256.d
new file mode 100644
index 00000000000..68b38be6aa6
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-movrs-avx10_2-256.d
@@ -0,0 +1,25 @@
+#objdump: -dw
+#name: x86_64 MOVRS, AVX10.2/256 insns
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*62 25 7f 0f 6f b4 f5 00 00 00 10\s+vmovrsb 0x10000000\(%rbp,%r14,8\),%xmm30\{%k7\}
+\s*[a-f0-9]+:\s*62 45 7f 08 6f 31\s+vmovrsb \(%r9\),%xmm30
+\s*[a-f0-9]+:\s*62 65 7f 08 6f 71 7f\s+vmovrsb 0x7f0\(%rcx\),%xmm30
+\s*[a-f0-9]+:\s*62 65 7f 8f 6f 72 80\s+vmovrsb -0x800\(%rdx\),%xmm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 25 7e 0f 6f b4 f5 00 00 00 10\s+vmovrsd 0x10000000\(%rbp,%r14,8\),%xmm30\{%k7\}
+\s*[a-f0-9]+:\s*62 45 7e 08 6f 31\s+vmovrsd \(%r9\),%xmm30
+\s*[a-f0-9]+:\s*62 65 7e 08 6f 71 7f\s+vmovrsd 0x7f0\(%rcx\),%xmm30
+\s*[a-f0-9]+:\s*62 65 7e 8f 6f 72 80\s+vmovrsd -0x800\(%rdx\),%xmm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 25 fe 0f 6f b4 f5 00 00 00 10\s+vmovrsq 0x10000000\(%rbp,%r14,8\),%xmm30\{%k7\}
+\s*[a-f0-9]+:\s*62 45 fe 08 6f 31\s+vmovrsq \(%r9\),%xmm30
+\s*[a-f0-9]+:\s*62 65 fe 08 6f 71 7f\s+vmovrsq 0x7f0\(%rcx\),%xmm30
+\s*[a-f0-9]+:\s*62 65 fe 8f 6f 72 80\s+vmovrsq -0x800\(%rdx\),%xmm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 25 ff 0f 6f b4 f5 00 00 00 10\s+vmovrsw 0x10000000\(%rbp,%r14,8\),%xmm30\{%k7\}
+\s*[a-f0-9]+:\s*62 45 ff 08 6f 31\s+vmovrsw \(%r9\),%xmm30
+\s*[a-f0-9]+:\s*62 65 ff 08 6f 71 7f\s+vmovrsw 0x7f0\(%rcx\),%xmm30
+\s*[a-f0-9]+:\s*62 65 ff 8f 6f 72 80\s+vmovrsw -0x800\(%rdx\),%xmm30\{%k7\}\{z\}
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-movrs-avx10_2-256.s b/gas/testsuite/gas/i386/x86-64-movrs-avx10_2-256.s
new file mode 100644
index 00000000000..c699d8e3d75
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-movrs-avx10_2-256.s
@@ -0,0 +1,41 @@
+# Check 64bit MOVRS, AVX10.2/256 instructions
+
+ .arch generic64
+ .arch .avx10.2/256
+ .arch .movrs
+_start:
+ vmovrsb 0x10000000(%rbp, %r14, 8), %xmm30{%k7}
+ vmovrsb (%r9), %xmm30
+ vmovrsb 2032(%rcx), %xmm30
+ vmovrsb -2048(%rdx), %xmm30{%k7}{z}
+ vmovrsd 0x10000000(%rbp, %r14, 8), %xmm30{%k7}
+ vmovrsd (%r9), %xmm30
+ vmovrsd 2032(%rcx), %xmm30
+ vmovrsd -2048(%rdx), %xmm30{%k7}{z}
+ vmovrsq 0x10000000(%rbp, %r14, 8), %xmm30{%k7}
+ vmovrsq (%r9), %xmm30
+ vmovrsq 2032(%rcx), %xmm30
+ vmovrsq -2048(%rdx), %xmm30{%k7}{z}
+ vmovrsw 0x10000000(%rbp, %r14, 8), %xmm30{%k7}
+ vmovrsw (%r9), %xmm30
+ vmovrsw 2032(%rcx), %xmm30
+ vmovrsw -2048(%rdx), %xmm30{%k7}{z}
+
+_intel:
+ .intel_syntax noprefix
+ vmovrsb xmm30{k7}, XMMWORD PTR [rbp+r14*8+0x10000000]
+ vmovrsb xmm30, XMMWORD PTR [r9]
+ vmovrsb xmm30, XMMWORD PTR [rcx+2032]
+ vmovrsb xmm30{k7}{z}, XMMWORD PTR [rdx-2048]
+ vmovrsd xmm30{k7}, XMMWORD PTR [rbp+r14*8+0x10000000]
+ vmovrsd xmm30, XMMWORD PTR [r9]
+ vmovrsd xmm30, XMMWORD PTR [rcx+2032]
+ vmovrsd xmm30{k7}{z}, XMMWORD PTR [rdx-2048]
+ vmovrsq xmm30{k7}, XMMWORD PTR [rbp+r14*8+0x10000000]
+ vmovrsq xmm30, XMMWORD PTR [r9]
+ vmovrsq xmm30, XMMWORD PTR [rcx+2032]
+ vmovrsq xmm30{k7}{z}, XMMWORD PTR [rdx-2048]
+ vmovrsw xmm30{k7}, XMMWORD PTR [rbp+r14*8+0x10000000]
+ vmovrsw xmm30, XMMWORD PTR [r9]
+ vmovrsw xmm30, XMMWORD PTR [rcx+2032]
+ vmovrsw xmm30{k7}{z}, XMMWORD PTR [rdx-2048]
diff --git a/gas/testsuite/gas/i386/x86-64-movrs-avx10_2-512-intel.d b/gas/testsuite/gas/i386/x86-64-movrs-avx10_2-512-intel.d
new file mode 100644
index 00000000000..e2f5847172a
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-movrs-avx10_2-512-intel.d
@@ -0,0 +1,27 @@
+#objdump: -dw -Mintel
+#name: x86_64 MOVRS, AVX10.2/512 insns (Intel disassembly)
+#source: x86-64-movrs-avx10_2-512.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+#...
+[a-f0-9]+ <_intel>:
+\s*[a-f0-9]+:\s*62 25 7f 4f 6f b4 f5 00 00 00 10\s+vmovrsb zmm30\{k7\},ZMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*62 45 7f 48 6f 31\s+vmovrsb zmm30,ZMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*62 65 7f 48 6f 71 7f\s+vmovrsb zmm30,ZMMWORD PTR \[rcx\+0x1fc0\]
+\s*[a-f0-9]+:\s*62 65 7f cf 6f 72 80\s+vmovrsb zmm30\{k7\}\{z\},ZMMWORD PTR \[rdx-0x2000\]
+\s*[a-f0-9]+:\s*62 25 7e 4f 6f b4 f5 00 00 00 10\s+vmovrsd zmm30\{k7\},ZMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*62 45 7e 48 6f 31\s+vmovrsd zmm30,ZMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*62 65 7e 48 6f 71 7f\s+vmovrsd zmm30,ZMMWORD PTR \[rcx\+0x1fc0\]
+\s*[a-f0-9]+:\s*62 65 7e cf 6f 72 80\s+vmovrsd zmm30\{k7\}\{z\},ZMMWORD PTR \[rdx-0x2000\]
+\s*[a-f0-9]+:\s*62 25 fe 4f 6f b4 f5 00 00 00 10\s+vmovrsq zmm30\{k7\},ZMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*62 45 fe 48 6f 31\s+vmovrsq zmm30,ZMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*62 65 fe 48 6f 71 7f\s+vmovrsq zmm30,ZMMWORD PTR \[rcx\+0x1fc0\]
+\s*[a-f0-9]+:\s*62 65 fe cf 6f 72 80\s+vmovrsq zmm30\{k7\}\{z\},ZMMWORD PTR \[rdx-0x2000\]
+\s*[a-f0-9]+:\s*62 25 ff 4f 6f b4 f5 00 00 00 10\s+vmovrsw zmm30\{k7\},ZMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*62 45 ff 48 6f 31\s+vmovrsw zmm30,ZMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*62 65 ff 48 6f 71 7f\s+vmovrsw zmm30,ZMMWORD PTR \[rcx\+0x1fc0\]
+\s*[a-f0-9]+:\s*62 65 ff cf 6f 72 80\s+vmovrsw zmm30\{k7\}\{z\},ZMMWORD PTR \[rdx-0x2000\]
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-movrs-avx10_2-512.d b/gas/testsuite/gas/i386/x86-64-movrs-avx10_2-512.d
new file mode 100644
index 00000000000..af32491c2e6
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-movrs-avx10_2-512.d
@@ -0,0 +1,25 @@
+#objdump: -dw
+#name: x86_64 MOVRS, AVX10.2/512 insns
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*62 25 7f 4f 6f b4 f5 00 00 00 10\s+vmovrsb 0x10000000\(%rbp,%r14,8\),%zmm30\{%k7\}
+\s*[a-f0-9]+:\s*62 45 7f 48 6f 31\s+vmovrsb \(%r9\),%zmm30
+\s*[a-f0-9]+:\s*62 65 7f 48 6f 71 7f\s+vmovrsb 0x1fc0\(%rcx\),%zmm30
+\s*[a-f0-9]+:\s*62 65 7f cf 6f 72 80\s+vmovrsb -0x2000\(%rdx\),%zmm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 25 7e 4f 6f b4 f5 00 00 00 10\s+vmovrsd 0x10000000\(%rbp,%r14,8\),%zmm30\{%k7\}
+\s*[a-f0-9]+:\s*62 45 7e 48 6f 31\s+vmovrsd \(%r9\),%zmm30
+\s*[a-f0-9]+:\s*62 65 7e 48 6f 71 7f\s+vmovrsd 0x1fc0\(%rcx\),%zmm30
+\s*[a-f0-9]+:\s*62 65 7e cf 6f 72 80\s+vmovrsd -0x2000\(%rdx\),%zmm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 25 fe 4f 6f b4 f5 00 00 00 10\s+vmovrsq 0x10000000\(%rbp,%r14,8\),%zmm30\{%k7\}
+\s*[a-f0-9]+:\s*62 45 fe 48 6f 31\s+vmovrsq \(%r9\),%zmm30
+\s*[a-f0-9]+:\s*62 65 fe 48 6f 71 7f\s+vmovrsq 0x1fc0\(%rcx\),%zmm30
+\s*[a-f0-9]+:\s*62 65 fe cf 6f 72 80\s+vmovrsq -0x2000\(%rdx\),%zmm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 25 ff 4f 6f b4 f5 00 00 00 10\s+vmovrsw 0x10000000\(%rbp,%r14,8\),%zmm30\{%k7\}
+\s*[a-f0-9]+:\s*62 45 ff 48 6f 31\s+vmovrsw \(%r9\),%zmm30
+\s*[a-f0-9]+:\s*62 65 ff 48 6f 71 7f\s+vmovrsw 0x1fc0\(%rcx\),%zmm30
+\s*[a-f0-9]+:\s*62 65 ff cf 6f 72 80\s+vmovrsw -0x2000\(%rdx\),%zmm30\{%k7\}\{z\}
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-movrs-avx10_2-512.s b/gas/testsuite/gas/i386/x86-64-movrs-avx10_2-512.s
new file mode 100644
index 00000000000..5caaf4f5097
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-movrs-avx10_2-512.s
@@ -0,0 +1,41 @@
+# Check 64bit MOVRS, AVX10.2/512 instructions
+
+ .arch generic64
+ .arch .avx10.2/512
+ .arch .movrs
+_start:
+ vmovrsb 0x10000000(%rbp, %r14, 8), %zmm30{%k7}
+ vmovrsb (%r9), %zmm30
+ vmovrsb 8128(%rcx), %zmm30
+ vmovrsb -8192(%rdx), %zmm30{%k7}{z}
+ vmovrsd 0x10000000(%rbp, %r14, 8), %zmm30{%k7}
+ vmovrsd (%r9), %zmm30
+ vmovrsd 8128(%rcx), %zmm30
+ vmovrsd -8192(%rdx), %zmm30{%k7}{z}
+ vmovrsq 0x10000000(%rbp, %r14, 8), %zmm30{%k7}
+ vmovrsq (%r9), %zmm30
+ vmovrsq 8128(%rcx), %zmm30
+ vmovrsq -8192(%rdx), %zmm30{%k7}{z}
+ vmovrsw 0x10000000(%rbp, %r14, 8), %zmm30{%k7}
+ vmovrsw (%r9), %zmm30
+ vmovrsw 8128(%rcx), %zmm30
+ vmovrsw -8192(%rdx), %zmm30{%k7}{z}
+
+_intel:
+ .intel_syntax noprefix
+ vmovrsb zmm30{k7}, ZMMWORD PTR [rbp+r14*8+0x10000000]
+ vmovrsb zmm30, ZMMWORD PTR [r9]
+ vmovrsb zmm30, ZMMWORD PTR [rcx+8128]
+ vmovrsb zmm30{k7}{z}, ZMMWORD PTR [rdx-8192]
+ vmovrsd zmm30{k7}, ZMMWORD PTR [rbp+r14*8+0x10000000]
+ vmovrsd zmm30, ZMMWORD PTR [r9]
+ vmovrsd zmm30, ZMMWORD PTR [rcx+8128]
+ vmovrsd zmm30{k7}{z}, ZMMWORD PTR [rdx-8192]
+ vmovrsq zmm30{k7}, ZMMWORD PTR [rbp+r14*8+0x10000000]
+ vmovrsq zmm30, ZMMWORD PTR [r9]
+ vmovrsq zmm30, ZMMWORD PTR [rcx+8128]
+ vmovrsq zmm30{k7}{z}, ZMMWORD PTR [rdx-8192]
+ vmovrsw zmm30{k7}, ZMMWORD PTR [rbp+r14*8+0x10000000]
+ vmovrsw zmm30, ZMMWORD PTR [r9]
+ vmovrsw zmm30, ZMMWORD PTR [rcx+8128]
+ vmovrsw zmm30{k7}{z}, ZMMWORD PTR [rdx-8192]
diff --git a/gas/testsuite/gas/i386/x86-64-movrs-intel.d b/gas/testsuite/gas/i386/x86-64-movrs-intel.d
new file mode 100644
index 00000000000..145644f8209
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-movrs-intel.d
@@ -0,0 +1,31 @@
+#objdump: -dw -Mintel
+#name: x86_64 MOVRS insns (Intel disassembly)
+#source: x86-64-movrs.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+#...
+[a-f0-9]+ <_intel>:
+\s*[a-f0-9]+:\s*66 42 0f 38 8b 94 f5 00 00 00 10\s+movrs dx,WORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*66 41 0f 38 8b 11\s+movrs dx,WORD PTR \[r9\]
+\s*[a-f0-9]+:\s*66 0f 38 8b 91 fe 00 00 00\s+movrs dx,WORD PTR \[rcx\+0xfe\]
+\s*[a-f0-9]+:\s*66 0f 38 8b 92 00 ff ff ff\s+movrs dx,WORD PTR \[rdx-0x100\]
+\s*[a-f0-9]+:\s*42 0f 38 8b 94 f5 00 00 00 10\s+movrs edx,DWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*41 0f 38 8b 11\s+movrs edx,DWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*0f 38 8b 91 fc 01 00 00\s+movrs edx,DWORD PTR \[rcx\+0x1fc\]
+\s*[a-f0-9]+:\s*0f 38 8b 92 00 fe ff ff\s+movrs edx,DWORD PTR \[rdx-0x200\]
+\s*[a-f0-9]+:\s*4e 0f 38 8b a4 f5 00 00 00 10\s+movrs r12,QWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*4d 0f 38 8b 21\s+movrs r12,QWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*4c 0f 38 8b a1 f8 03 00 00\s+movrs r12,QWORD PTR \[rcx\+0x3f8\]
+\s*[a-f0-9]+:\s*4c 0f 38 8b a2 00 fc ff ff\s+movrs r12,QWORD PTR \[rdx-0x400\]
+\s*[a-f0-9]+:\s*42 0f 38 8a 9c f5 00 00 00 10\s+movrs bl,BYTE PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*41 0f 38 8a 19\s+movrs bl,BYTE PTR \[r9\]
+\s*[a-f0-9]+:\s*0f 38 8a 59 7f\s+movrs bl,BYTE PTR \[rcx\+0x7f\]
+\s*[a-f0-9]+:\s*0f 38 8a 5a 80\s+movrs bl,BYTE PTR \[rdx-0x80\]
+\s*[a-f0-9]+:\s*42 0f 18 a4 f5 00 00 00 10\s+prefetchrst2 BYTE PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*41 0f 18 21\s+prefetchrst2 BYTE PTR \[r9\]
+\s*[a-f0-9]+:\s*0f 18 61 7f\s+prefetchrst2 BYTE PTR \[rcx\+0x7f\]
+\s*[a-f0-9]+:\s*0f 18 62 80\s+prefetchrst2 BYTE PTR \[rdx-0x80\]
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-movrs-suffix-intel.d b/gas/testsuite/gas/i386/x86-64-movrs-suffix-intel.d
new file mode 100644
index 00000000000..b1dcb2db898
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-movrs-suffix-intel.d
@@ -0,0 +1,15 @@
+#objdump: -dwMsuffix -Mintel
+#name: x86_64 MOVRS insns
+#source: x86-64-movrs-suffix.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+#...
+[a-f0-9]+ <_intel>:
+\s*[a-f0-9]+:\s*66 0f 38 8b 92 00 ff ff ff\s+movrsw -0x100\(%rdx\),%dx
+\s*[a-f0-9]+:\s*0f 38 8b 92 00 fe ff ff\s+movrsl -0x200\(%rdx\),%edx
+\s*[a-f0-9]+:\s*4c 0f 38 8b a2 00 fc ff ff\s+movrsq -0x400\(%rdx\),%r12
+\s*[a-f0-9]+:\s*0f 38 8a 5a 80\s+movrsb -0x80\(%rdx\),%bl
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-movrs-suffix.d b/gas/testsuite/gas/i386/x86-64-movrs-suffix.d
new file mode 100644
index 00000000000..7f71b1dfbd0
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-movrs-suffix.d
@@ -0,0 +1,13 @@
+#objdump: -dwMsuffix
+#name: x86_64 MOVRS insns
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*66 0f 38 8b 92 00 ff ff ff\s+movrsw -0x100\(%rdx\),%dx
+\s*[a-f0-9]+:\s*0f 38 8b 92 00 fe ff ff\s+movrsl -0x200\(%rdx\),%edx
+\s*[a-f0-9]+:\s*4c 0f 38 8b a2 00 fc ff ff\s+movrsq -0x400\(%rdx\),%r12
+\s*[a-f0-9]+:\s*0f 38 8a 5a 80\s+movrsb -0x80\(%rdx\),%bl
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-movrs-suffix.s b/gas/testsuite/gas/i386/x86-64-movrs-suffix.s
new file mode 100644
index 00000000000..6120b768d7c
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-movrs-suffix.s
@@ -0,0 +1,15 @@
+# Check 64bit MOVRS instructions
+
+ .text
+_start:
+ movrsw -256(%rdx), %dx
+ movrsl -512(%rdx), %edx
+ movrsq -1024(%rdx), %r12
+ movrsb -128(%rdx), %bl
+
+_intel:
+ .intel_syntax noprefix
+ movrsw dx, WORD PTR [rdx-256]
+ movrsl edx, DWORD PTR [rdx-512]
+ movrsq r12, QWORD PTR [rdx-1024]
+ movrsb bl, BYTE PTR [rdx-128]
diff --git a/gas/testsuite/gas/i386/x86-64-movrs.d b/gas/testsuite/gas/i386/x86-64-movrs.d
new file mode 100644
index 00000000000..b5d48cd4fe0
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-movrs.d
@@ -0,0 +1,29 @@
+#objdump: -dw
+#name: x86_64 MOVRS insns
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*66 42 0f 38 8b 94 f5 00 00 00 10\s+movrs 0x10000000\(%rbp,%r14,8\),%dx
+\s*[a-f0-9]+:\s*66 41 0f 38 8b 11\s+movrs \(%r9\),%dx
+\s*[a-f0-9]+:\s*66 0f 38 8b 91 fe 00 00 00\s+movrs 0xfe\(%rcx\),%dx
+\s*[a-f0-9]+:\s*66 0f 38 8b 92 00 ff ff ff\s+movrs -0x100\(%rdx\),%dx
+\s*[a-f0-9]+:\s*42 0f 38 8b 94 f5 00 00 00 10\s+movrs 0x10000000\(%rbp,%r14,8\),%edx
+\s*[a-f0-9]+:\s*41 0f 38 8b 11\s+movrs \(%r9\),%edx
+\s*[a-f0-9]+:\s*0f 38 8b 91 fc 01 00 00\s+movrs 0x1fc\(%rcx\),%edx
+\s*[a-f0-9]+:\s*0f 38 8b 92 00 fe ff ff\s+movrs -0x200\(%rdx\),%edx
+\s*[a-f0-9]+:\s*4e 0f 38 8b a4 f5 00 00 00 10\s+movrs 0x10000000\(%rbp,%r14,8\),%r12
+\s*[a-f0-9]+:\s*4d 0f 38 8b 21\s+movrs \(%r9\),%r12
+\s*[a-f0-9]+:\s*4c 0f 38 8b a1 f8 03 00 00\s+movrs 0x3f8\(%rcx\),%r12
+\s*[a-f0-9]+:\s*4c 0f 38 8b a2 00 fc ff ff\s+movrs -0x400\(%rdx\),%r12
+\s*[a-f0-9]+:\s*42 0f 38 8a 9c f5 00 00 00 10\s+movrs 0x10000000\(%rbp,%r14,8\),%bl
+\s*[a-f0-9]+:\s*41 0f 38 8a 19\s+movrs \(%r9\),%bl
+\s*[a-f0-9]+:\s*0f 38 8a 59 7f\s+movrs 0x7f\(%rcx\),%bl
+\s*[a-f0-9]+:\s*0f 38 8a 5a 80\s+movrs -0x80\(%rdx\),%bl
+\s*[a-f0-9]+:\s*42 0f 18 a4 f5 00 00 00 10\s+prefetchrst2 0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*41 0f 18 21\s+prefetchrst2 \(%r9\)
+\s*[a-f0-9]+:\s*0f 18 61 7f\s+prefetchrst2 0x7f\(%rcx\)
+\s*[a-f0-9]+:\s*0f 18 62 80\s+prefetchrst2 -0x80\(%rdx\)
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-movrs.s b/gas/testsuite/gas/i386/x86-64-movrs.s
new file mode 100644
index 00000000000..e15269a8a3e
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-movrs.s
@@ -0,0 +1,47 @@
+# Check 64bit MOVRS instructions
+
+ .text
+_start:
+ movrs 0x10000000(%rbp, %r14, 8), %dx
+ movrs (%r9), %dx
+ movrs 254(%rcx), %dx
+ movrs -256(%rdx), %dx
+ movrs 0x10000000(%rbp, %r14, 8), %edx
+ movrs (%r9), %edx
+ movrs 508(%rcx), %edx
+ movrs -512(%rdx), %edx
+ movrs 0x10000000(%rbp, %r14, 8), %r12
+ movrs (%r9), %r12
+ movrs 1016(%rcx), %r12
+ movrs -1024(%rdx), %r12
+ movrs 0x10000000(%rbp, %r14, 8), %bl
+ movrs (%r9), %bl
+ movrs 127(%rcx), %bl
+ movrs -128(%rdx), %bl
+ prefetchrst2 0x10000000(%rbp, %r14, 8)
+ prefetchrst2 (%r9)
+ prefetchrst2 127(%rcx)
+ prefetchrst2 -128(%rdx)
+
+_intel:
+ .intel_syntax noprefix
+ movrs dx, WORD PTR [rbp+r14*8+0x10000000]
+ movrs dx, WORD PTR [r9]
+ movrs dx, WORD PTR [rcx+254]
+ movrs dx, WORD PTR [rdx-256]
+ movrs edx, DWORD PTR [rbp+r14*8+0x10000000]
+ movrs edx, DWORD PTR [r9]
+ movrs edx, DWORD PTR [rcx+508]
+ movrs edx, DWORD PTR [rdx-512]
+ movrs r12, QWORD PTR [rbp+r14*8+0x10000000]
+ movrs r12, QWORD PTR [r9]
+ movrs r12, QWORD PTR [rcx+1016]
+ movrs r12, QWORD PTR [rdx-1024]
+ movrs bl, BYTE PTR [rbp+r14*8+0x10000000]
+ movrs bl, BYTE PTR [r9]
+ movrs bl, BYTE PTR [rcx+127]
+ movrs bl, BYTE PTR [rdx-128]
+ prefetchrst2 BYTE PTR [rbp+r14*8+0x10000000]
+ prefetchrst2 BYTE PTR [r9]
+ prefetchrst2 BYTE PTR [rcx+127]
+ prefetchrst2 BYTE PTR [rdx-128]
diff --git a/gas/testsuite/gas/i386/x86-64-prefetch-intel.d b/gas/testsuite/gas/i386/x86-64-prefetch-intel.d
index b0f9556f942..29c5253019c 100644
--- a/gas/testsuite/gas/i386/x86-64-prefetch-intel.d
+++ b/gas/testsuite/gas/i386/x86-64-prefetch-intel.d
@@ -22,7 +22,7 @@ Disassembly of section .text:
\s*[a-f0-9]+: 0f 18 08 prefetcht0 BYTE PTR \[rax\]
\s*[a-f0-9]+: 0f 18 10 prefetcht1 BYTE PTR \[rax\]
\s*[a-f0-9]+: 0f 18 18 prefetcht2 BYTE PTR \[rax\]
-\s*[a-f0-9]+: 0f 18 20 nop DWORD PTR \[rax\]
+\s*[a-f0-9]+: 0f 18 20 prefetchrst2 BYTE PTR \[rax\]
\s*[a-f0-9]+: 0f 18 28 nop DWORD PTR \[rax\]
\s*[a-f0-9]+: 0f 18 30 nop DWORD PTR \[rax\]
\s*[a-f0-9]+: 0f 18 38 nop DWORD PTR \[rax\]
diff --git a/gas/testsuite/gas/i386/x86-64-prefetch.d b/gas/testsuite/gas/i386/x86-64-prefetch.d
index 3e83ef5bf4c..18205c28188 100644
--- a/gas/testsuite/gas/i386/x86-64-prefetch.d
+++ b/gas/testsuite/gas/i386/x86-64-prefetch.d
@@ -22,7 +22,7 @@ Disassembly of section .text:
\s*[a-f0-9]+: 0f 18 08 prefetcht0 \(%rax\)
\s*[a-f0-9]+: 0f 18 10 prefetcht1 \(%rax\)
\s*[a-f0-9]+: 0f 18 18 prefetcht2 \(%rax\)
-\s*[a-f0-9]+: 0f 18 20 nopl \(%rax\)
+\s*[a-f0-9]+: 0f 18 20 prefetchrst2 \(%rax\)
\s*[a-f0-9]+: 0f 18 28 nopl \(%rax\)
\s*[a-f0-9]+: 0f 18 30 nopl \(%rax\)
\s*[a-f0-9]+: 0f 18 38 nopl \(%rax\)
diff --git a/gas/testsuite/gas/i386/x86-64.exp b/gas/testsuite/gas/i386/x86-64.exp
index fe503671312..265bd0b2e66 100644
--- a/gas/testsuite/gas/i386/x86-64.exp
+++ b/gas/testsuite/gas/i386/x86-64.exp
@@ -535,6 +535,12 @@ run_dump_test "x86-64-amx-fp8"
run_dump_test "x86-64-amx-fp8-intel"
run_list_test "x86-64-amx-fp8-inval"
run_dump_test "x86-64-amx-fp8-bad"
+run_dump_test "x86-64-movrs"
+run_dump_test "x86-64-movrs-intel"
+run_dump_test "x86-64-movrs-avx10_2-512"
+run_dump_test "x86-64-movrs-avx10_2-512-intel"
+run_dump_test "x86-64-movrs-avx10_2-256"
+run_dump_test "x86-64-movrs-avx10_2-256-intel"
run_dump_test "x86-64-clzero"
run_dump_test "x86-64-mwaitx-bdver4"
run_list_test "x86-64-mwaitx-reg"
diff --git a/opcodes/i386-dis-evex-prefix.h b/opcodes/i386-dis-evex-prefix.h
index 16fb2698390..6f953d6e678 100644
--- a/opcodes/i386-dis-evex-prefix.h
+++ b/opcodes/i386-dis-evex-prefix.h
@@ -580,6 +580,13 @@
{ VEX_W_TABLE (EVEX_W_MAP5_6E_P_1) },
{ "vmovwY", { XMScalar, Edw }, 0 },
},
+ /* PREFIX_EVEX_MAP5_6F_X86_64 */
+ {
+ { Bad_Opcode },
+ { "vmovrs%DQ", { XM, Mx }, 0 },
+ { Bad_Opcode },
+ { "vmovrs%BW", { XM, Mx }, 0 },
+ },
/* PREFIX_EVEX_MAP5_74 */
{
{ "vcvtbiasp%XH2bf8s", { XMxmmq, Vex, EXxh }, 0 },
diff --git a/opcodes/i386-dis-evex-x86-64.h b/opcodes/i386-dis-evex-x86-64.h
new file mode 100644
index 00000000000..bb5a9f383e4
--- /dev/null
+++ b/opcodes/i386-dis-evex-x86-64.h
@@ -0,0 +1,5 @@
+ /* X86_64_EVEX_MAP5_6F */
+ {
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_EVEX_MAP5_6F_X86_64) },
+ },
diff --git a/opcodes/i386-dis-evex.h b/opcodes/i386-dis-evex.h
index 006d0c4a990..caba430a097 100644
--- a/opcodes/i386-dis-evex.h
+++ b/opcodes/i386-dis-evex.h
@@ -1030,8 +1030,8 @@ static const struct dis386 evex_table[][256] = {
/* 88 */
{ "%NFpopcntS", { Gv, Ev }, PREFIX_NP_OR_DATA },
{ Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
+ { "movrsB", { Gb, Mb }, NO_PREFIX },
+ { "movrsS", { Gv, Mv }, PREFIX_NP_OR_DATA },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
@@ -1290,7 +1290,7 @@ static const struct dis386 evex_table[][256] = {
{ PREFIX_TABLE (PREFIX_EVEX_MAP5_6C) },
{ PREFIX_TABLE (PREFIX_EVEX_MAP5_6D) },
{ EVEX_LEN_TABLE (EVEX_LEN_MAP5_6E) },
- { Bad_Opcode },
+ { X86_64_TABLE (X86_64_EVEX_MAP5_6F) },
/* 70 */
{ Bad_Opcode },
{ Bad_Opcode },
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index f9b6cf30fd0..038ad9b0ded 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -942,6 +942,7 @@ enum
MOD_0F18_REG_1,
MOD_0F18_REG_2,
MOD_0F18_REG_3,
+ MOD_0F18_REG_4,
MOD_0F18_REG_6,
MOD_0F18_REG_7,
MOD_0F1A_PREFIX_0,
@@ -1258,6 +1259,7 @@ enum
PREFIX_EVEX_MAP5_6C,
PREFIX_EVEX_MAP5_6D,
PREFIX_EVEX_MAP5_6E_L_0,
+ PREFIX_EVEX_MAP5_6F_X86_64,
PREFIX_EVEX_MAP5_74,
PREFIX_EVEX_MAP5_78,
PREFIX_EVEX_MAP5_79,
@@ -1346,6 +1348,8 @@ enum
X86_64_0F18_REG_7_MOD_0,
X86_64_0F24,
X86_64_0F26,
+ X86_64_0F388A,
+ X86_64_0F388B,
X86_64_0F38F8_M_1,
X86_64_0FC7_REG_6_MOD_3_PREFIX_1,
@@ -1364,6 +1368,8 @@ enum
X86_64_VEX_MAP5_FD,
X86_64_VEX_MAP7_F6_L_0_W_0_R_0,
X86_64_VEX_MAP7_F8_L_0_W_0_R_0,
+
+ X86_64_EVEX_MAP5_6F,
};
enum
@@ -2865,7 +2871,7 @@ static const struct dis386 reg_table[][8] = {
{ MOD_TABLE (MOD_0F18_REG_1) },
{ MOD_TABLE (MOD_0F18_REG_2) },
{ MOD_TABLE (MOD_0F18_REG_3) },
- { "nopQ", { Ev }, 0 },
+ { MOD_TABLE (MOD_0F18_REG_4) },
{ "nopQ", { Ev }, 0 },
{ MOD_TABLE (MOD_0F18_REG_6) },
{ MOD_TABLE (MOD_0F18_REG_7) },
@@ -4616,6 +4622,18 @@ static const struct dis386 x86_64_table[][2] = {
{ "movZ", { Td, Em }, 0 },
},
+ {
+ /* X86_64_0F388A */
+ { Bad_Opcode },
+ { "movrsB", { Gb, Mb }, PREFIX_OPCODE },
+ },
+
+ {
+ /* X86_64_0F388B */
+ { Bad_Opcode },
+ { "movrsS", { Gv, Mv }, PREFIX_OPCODE },
+ },
+
{
/* X86_64_0F38F8_M_1 */
{ Bad_Opcode },
@@ -4711,6 +4729,8 @@ static const struct dis386 x86_64_table[][2] = {
{ Bad_Opcode },
{ PREFIX_TABLE (PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64) },
},
+
+#include "i386-dis-evex-x86-64.h"
};
static const struct dis386 three_byte_table[][256] = {
@@ -4873,8 +4893,8 @@ static const struct dis386 three_byte_table[][256] = {
/* 88 */
{ Bad_Opcode },
{ Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
+ { X86_64_TABLE (X86_64_0F388A) },
+ { X86_64_TABLE (X86_64_0F388B) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
@@ -8393,6 +8413,11 @@ static const struct dis386 mod_table[][2] = {
{ "prefetcht2", { Mb }, 0 },
{ "nopQ", { Ev }, 0 },
},
+ {
+ /* MOD_0F18_REG_4 */
+ { "prefetchrst2", { Mb }, 0 },
+ { "nopQ", { Ev }, 0 },
+ },
{
/* MOD_0F18_REG_6 */
{ X86_64_TABLE (X86_64_0F18_REG_6_MOD_0) },
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index 60aa8ddbad7..1bb20b40228 100644
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -420,6 +420,7 @@ static bitfield cpu_flags[] =
BITFIELD (MSR_IMM),
BITFIELD (APX_F),
BITFIELD (AVX10_2),
+ BITFIELD (MOVRS),
BITFIELD (MWAITX),
BITFIELD (CLZERO),
BITFIELD (OSPKE),
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index 5d330550205..1ca3b575c62 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -231,6 +231,8 @@ enum i386_cpu
CpuUSER_MSR,
/* Intel MSR_IMM Instructions support required. */
CpuMSR_IMM,
+ /* Intel MOVRS Instructions support required. */
+ CpuMOVRS,
/* mwaitx instruction required */
CpuMWAITX,
/* Clzero instruction required */
@@ -496,6 +498,7 @@ typedef union i386_cpu_flags
unsigned int cpulkgs:1;
unsigned int cpuuser_msr:1;
unsigned int cpumsr_imm:1;
+ unsigned int cpumovrs:1;
unsigned int cpumwaitx:1;
unsigned int cpuclzero:1;
unsigned int cpuospke:1;
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 32dd883926c..fb7b0a346d1 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -3557,3 +3557,15 @@ vcomxs<sdh>, 0x<sdh:spfx>2f, AVX10_2, Modrm|EVexLIG|<sdh:spc1>|<sdh:vexw>|Disp8M
vucomxs<sdh>, 0x<sdh:spfx>2e, AVX10_2, Modrm|EVexLIG|<sdh:spc1>|<sdh:vexw>|Disp8MemShift|NoSuf|SAE, { RegXMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM }
// AVX10.2 instructions end.
+
+// MOVRS instructions.
+
+prefetchrst2, 0xf18/4, MOVRS, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex }
+
+movrs, 0x8a, MOVRS&x64, D|W|Modrm|Space0F38|CheckOperandSize|No_sSuf, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
+movrs, 0x8a, MOVRS&APX_F, D|W|Modrm|EVexMap4|EVex128|CheckOperandSize|No_sSuf, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
+
+vmovrs<bw>, 0xf26f, AVX10_2&MOVRS&x64, Modrm|Masking|Map5|<bw:vexw>|Disp8ShiftVL|CheckOperandSize|NoSuf, { Xmmword|Ymmword|Zmmword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
+vmovrs<dq>, 0xf36f, AVX10_2&MOVRS&x64, Modrm|Masking|Map5|<dq:vexw>|Disp8ShiftVL|CheckOperandSize|NoSuf, { Xmmword|Ymmword|Zmmword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
+
+// MOVRS instructions end.
--
2.31.1
More information about the Binutils
mailing list