[PATCH v3 2/5] aarch64: Add support for FEAT_SVE_B16B16 min and max instructions.

Thu Jan 9 11:59:59 GMT 2025

On Tue, Jan 07, 2025 at 11:34:12AM +0000, Srinath Parvathaneni wrote:
> 
> This patch adds support for SME Z-targeting multi-vector non-widening
> BFloat16 instructions, under tick FEAT_SVE_B16B16 and command line flag
> "+sve-b16b16+sme2".
> 
> Also the test files related to FEAT_SVE_B16B16 (+sme2) are prefixed with
> sve-b16b16-sme2*.
> eg: sve-b16b16-sme2-1.s, sve-b16b16-sme2-1.d.
> 
> The spec for this feature and instructions is availabe here [1]:
> [1]: https://developer.arm.com/documentation/ddi0602/2024-06/SME-Instructions?lang=en
> ---
>  .../gas/aarch64/sve-b16b16-sme2-bad-1.d       |   3 +
>  .../gas/aarch64/sve-b16b16-sme2-bad-1.l       | 159 ++++++++++++++++++
>  .../gas/aarch64/sve-b16b16-sme2-bad-1.s       | 136 +++++++++++++++
>  gas/testsuite/gas/aarch64/sve-b16b16-sme2.d   | 122 ++++++++++++++
>  gas/testsuite/gas/aarch64/sve-b16b16-sme2.s   | 138 +++++++++++++++
>  .../gas/aarch64/sve-b16b16-sve2-bad-2.l       |   4 +-
>  opcodes/aarch64-tbl.h                         |  29 ++++
>  7 files changed, 589 insertions(+), 2 deletions(-)
>  create mode 100644 gas/testsuite/gas/aarch64/sve-b16b16-sme2-bad-1.d
>  create mode 100644 gas/testsuite/gas/aarch64/sve-b16b16-sme2-bad-1.l
>  create mode 100644 gas/testsuite/gas/aarch64/sve-b16b16-sme2-bad-1.s
>  create mode 100644 gas/testsuite/gas/aarch64/sve-b16b16-sme2.d
>  create mode 100644 gas/testsuite/gas/aarch64/sve-b16b16-sme2.s
> 

> diff --git a/gas/testsuite/gas/aarch64/sve-b16b16-sme2-bad-1.d b/gas/testsuite/gas/aarch64/sve-b16b16-sme2-bad-1.d
> new file mode 100644
> index 00000000000..7ebb81d3850
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/sve-b16b16-sme2-bad-1.d
> @@ -0,0 +1,3 @@
> +#name: Test of invalid SME2.1 non-widening BFloat16 min max instructions.

Minor nit, but these aren't tied to SME2.1, so it's probably better to say just SME2 (or SME).

> +#as: -march=armv8-a+sve-b16b16+sme2
> +#error_output: sve-b16b16-sme2-bad-1.l
(snip)
> diff --git a/gas/testsuite/gas/aarch64/sve-b16b16-sme2.d b/gas/testsuite/gas/aarch64/sve-b16b16-sme2.d
> new file mode 100644
> index 00000000000..1a378eb0996
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/sve-b16b16-sme2.d
> @@ -0,0 +1,122 @@
> +#name: Test of SME2.1 non-widening BFloat16 min max instructions.

As above - these aren't tied to SME2.1.

> +#as: -march=armv8-a+sve-b16b16+sme2
> +#objdump: -dr
> +
(snip)
> diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
> index d133ab045d8..0c98da05ad7 100644
> --- a/opcodes/aarch64-tbl.h
> +++ b/opcodes/aarch64-tbl.h
> @@ -2813,6 +2813,8 @@ static const aarch64_feature_set aarch64_feature_d128_the =
>    AARCH64_FEATURES (2, D128, THE);
>  static const aarch64_feature_set aarch64_feature_sve_b16b16_sve2 =
>    AARCH64_FEATURES (2, SVE_B16B16, SVE2);
> +static const aarch64_feature_set aarch64_feature_sve_b16b16_sme2 =
> +  AARCH64_FEATURES (2, SVE_B16B16, SME2);
>  static const aarch64_feature_set aarch64_feature_sme2p1 =
>    AARCH64_FEATURE (SME2p1);
>  static const aarch64_feature_set aarch64_feature_sve2p1 =
> @@ -2924,6 +2926,7 @@ static const aarch64_feature_set aarch64_feature_sme_f16f16_f8f16 =
>  #define THE	  &aarch64_feature_the
>  #define D128_THE  &aarch64_feature_d128_the
>  #define B16B16_SVE2  &aarch64_feature_sve_b16b16_sve2
> +#define SVE_B16B16_SME  &aarch64_feature_sve_b16b16_sme2
>  #define SME2p1  &aarch64_feature_sme2p1
>  #define SVE2p1  &aarch64_feature_sve2p1
>  #define RCPC3	  &aarch64_feature_rcpc3
> @@ -3026,6 +3029,12 @@ static const aarch64_feature_set aarch64_feature_sme_f16f16_f8f16 =
>  #define B16B16_SVE2_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \
>    { NAME, OPCODE, MASK, CLASS, OP, B16B16_SVE2, OPS, QUALS, \
>      FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL }
> +#define SVE_B16B16_SME_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
> +  { NAME, OPCODE, MASK, CLASS, OP, SVE_B16B16_SME, OPS, QUALS, \
> +    FLAGS | F_STRICT, 0, TIED, NULL }
> +#define SVE_B16B16_SME_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \
> +  { NAME, OPCODE, MASK, CLASS, OP, SVE_B16B16_SME, OPS, QUALS, \
> +    FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL }
>  #define SVE2p1_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
>    { NAME, OPCODE, MASK, CLASS, OP, SVE2p1, OPS, QUALS, \
>      FLAGS | F_STRICT, 0, TIED, NULL }
> @@ -6643,6 +6652,26 @@ const struct aarch64_opcode aarch64_opcode_table[] =
>    B16B16_SVE2_INSN("bfsub", 0x65000400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_HHH, 0, 0),
>    B16B16_SVE2_INSN("bfmul", 0x64202800, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_22_INDEX), OP_SVE_VVV_H, 0, 0),
>  
> +/* SME Z-targeting multi-vector non-widening BFloat16 instructions.  */
> +  SVE_B16B16_SME_INSN("bfmax", 0xc120a100, 0xfff0ffe1, sme_misc, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zm), OP_SVE_HHH, F_OD(2), 1),
> +  SVE_B16B16_SME_INSN("bfmax", 0xc120a900, 0xfff0ffe3, sme_misc, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zm), OP_SVE_HHH, F_OD(4), 1),
> +  SVE_B16B16_SME_INSN("bfmax", 0xc120b100, 0xffe1ffe1, sme_misc, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zmx2), OP_SVE_HHH, F_OD(2), 1),
> +  SVE_B16B16_SME_INSN("bfmax", 0xc120b900, 0xffe3ffe3, sme_misc, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zmx4), OP_SVE_HHH, F_OD(4), 1),
> +  SVE_B16B16_SME_INSN("bfmaxnm", 0xc120a120, 0xfff0ffe1, sme_misc, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zm), OP_SVE_HHH, F_OD(2), 1),
> +  SVE_B16B16_SME_INSN("bfmaxnm", 0xc120a920, 0xfff0ffe3, sme_misc, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zm), OP_SVE_HHH, F_OD(4), 1),
> +  SVE_B16B16_SME_INSN("bfmaxnm", 0xc120b120, 0xffe1ffe1, sme_misc, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zmx2), OP_SVE_HHH, F_OD(2), 1),
> +  SVE_B16B16_SME_INSN("bfmaxnm", 0xc120b920, 0xffe3ffe3, sme_misc, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zmx4), OP_SVE_HHH, F_OD(4), 1),
> +  SVE_B16B16_SME_INSN("bfmin", 0xc120a101, 0xfff0ffe1, sme_misc, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zm), OP_SVE_HHH, F_OD(2), 1),
> +  SVE_B16B16_SME_INSN("bfmin", 0xc120a901, 0xfff0ffe3, sme_misc, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zm), OP_SVE_HHH, F_OD(4), 1),
> +  SVE_B16B16_SME_INSN("bfmin", 0xc120b101, 0xffe1ffe1, sme_misc, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zmx2), OP_SVE_HHH, F_OD(2), 1),
> +  SVE_B16B16_SME_INSN("bfmin", 0xc120b901, 0xffe3ffe3, sme_misc, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zmx4), OP_SVE_HHH, F_OD(4), 1),
> +  SVE_B16B16_SME_INSN("bfminnm", 0xc120a121, 0xfff0ffe1, sme_misc, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zm), OP_SVE_HHH, F_OD(2), 1),
> +  SVE_B16B16_SME_INSN("bfminnm", 0xc120a921, 0xfff0ffe3, sme_misc, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zm), OP_SVE_HHH, F_OD(4), 1),
> +  SVE_B16B16_SME_INSN("bfminnm", 0xc120b121, 0xffe1ffe1, sme_misc, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zmx2), OP_SVE_HHH, F_OD(2), 1),
> +  SVE_B16B16_SME_INSN("bfminnm", 0xc120b921, 0xffe3ffe3, sme_misc, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zmx4), OP_SVE_HHH, F_OD(4), 1),
> +  SVE_B16B16_SME_INSN("bfclamp", 0xc120c000, 0xffe0fc01, sme_misc, 0, OP3 (SME_Zdnx2, SVE_Zn, SVE_Zm_16), OP_SVE_HHH, 0, 0),
> +  SVE_B16B16_SME_INSN("bfclamp", 0xc120c800, 0xffe0fc03, sme_misc, 0, OP3 (SME_Zdnx4, SVE_Zn, SVE_Zm_16), OP_SVE_HHH,0, 0),

My previous comment about these instructions not using operand specific data
applied to all instructions added in this patch, not just the bfclamp ones you
amended here.  Can you remove F_OD(*) from the rest of them as well?

> +
>  /* SME2.1 movaz instructions.  */
>    SME2p1_INSN ("movaz", 0xc0060600, 0xffff1f83, sme2_movaz, 0, OP2 (SME_Zdnx4, SME_ZA_array_vrsb_2), OP_SVE_BB, 0, 0),
>    SME2p1_INSN ("movaz", 0xc0460600, 0xffff1f83, sme2_movaz, 0, OP2 (SME_Zdnx4, SME_ZA_array_vrsh_2), OP_SVE_HH, 0, 0),