[PATCH 1/2] Support Intel MOVRS

[Jiang, Haochen]

> From: Jan Beulich <jbeulich@suse.com>
> Sent: Tuesday, January 7, 2025 4:56 PM
> 
> On 07.01.2025 03:57, Jiang, Haochen wrote:
> >> From: Jan Beulich <jbeulich@suse.com>
> >> Sent: Monday, January 6, 2025 4:39 PM
> >>
> >> On 30.12.2024 08:39, Jiang, Haochen wrote:
> >>>> From: Jan Beulich <jbeulich@suse.com>
> >>>> Sent: Friday, December 27, 2024 8:27 PM
> >>>>
> >>>> On 24.12.2024 10:24, Haochen Jiang wrote:
> >>>
> >>> It is not a VEX/EVEX promotion, but a legacy/EVEX promotion. Could
> >>> we do that?
> >>>
> >>> If we could, the problem here is still MOVRS is not 64-bit default.
> >>> Then the non-APX part needs x64, making it multiple CPUIDs. Maybe it
> >>> also needs work around in cpu_flags_match second assert just like
> >>> AMX_MOVRS & AMX_TRANSPOSE. At least we could check the all.bitfield
> >>> to let them skip that assert.
> >>
> >> Perhaps a misunderstanding? I talk about our W attribute in the
> >> opcode table, not EVEX.W.
> >
> > VexW0 should be removed per my understanding although I am still
> > waiting for clarification from HW team on that. My problem and
> > statement is on "allowing to go from 4 to 2 templates". It seems to me
> > not that doable. Could you help explain on that part?
> 
> I'm confused, and I really have a hard time seeing how else I can make clear
> that I'm _not_ talking about VEX.W or EVEX.W. Let me nevertheless try: Just
> like we use W in
> 
> mov, 0x88, 0, D|W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixRelease,
> { Reg8|Reg16|Reg32|Reg64,
> Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> 
> I expect you should also be able to use it for the MOVRS templates, thus
> merging the 8-bit forms you presently have as separate templates into the 16-
> /32-/64-bit forms. The encoding (of the low opcode bit) certainly follows that
> same model. And for the EVEX encodings there's more general VexWIG
> handling for the 8-bit APX forms as well, so that aspect also shouldn't be a
> reason to require separate templates.
> 

I get your point now. Let me change that.

Thx,
Haochen