[PATCH] RISC-V: Make SSAMOSWAP.W available for rv64
Kito Cheng
kito.cheng@sifive.com
Fri Feb 14 02:40:53 GMT 2025
From: Hau Hsu <hau.hsu@sifive.com>
Previously we limited SSAMOSWAP.W only available on RV32, but it should
be available on RV64 as well.
See
https://github.com/riscv/riscv-cfi/blob/main/src/cfi_backward.adoc
https://github.com/riscv/riscv-isa-manual/blob/702a3e6e843235a2a13b918ae6938b04f8974ffc/src/unpriv-cfi.adoc#L789
---
bfd/elfnn-riscv.c | 6 ++++--
gas/testsuite/gas/riscv/zicfisslp-64.d | 8 ++++++++
gas/testsuite/gas/riscv/zicfisslp-64.s | 8 ++++++++
opcodes/riscv-opc.c | 8 ++++----
4 files changed, 24 insertions(+), 6 deletions(-)
diff --git a/bfd/elfnn-riscv.c b/bfd/elfnn-riscv.c
index 430300a2448..71399e70aad 100644
--- a/bfd/elfnn-riscv.c
+++ b/bfd/elfnn-riscv.c
@@ -5142,10 +5142,11 @@ _bfd_riscv_relax_pc (bfd *abfd ATTRIBUTE_UNUSED,
/* Is the reference in range of x0 or gp?
Valid gp range conservatively because of alignment issue.
+ x0 is only valid for non-PIE.
Should we also consider the alignment issue for x0 base? */
if (undefined_weak
- || VALID_ITYPE_IMM (symval)
+ || (!bfd_link_pie (link_info) && VALID_ITYPE_IMM (symval))
|| (symval >= gp
&& VALID_ITYPE_IMM (symval - gp + max_alignment + reserve_size))
|| (symval < gp
@@ -5223,6 +5224,7 @@ _bfd_riscv_relax_section (bfd *abfd, asection *sec,
if (bfd_link_relocatable (info)
|| sec->sec_flg0
|| sec->reloc_count == 0
+// || (!bfd_link_pie (info) && (sec->flags & SEC_RELOC) == 0)
|| (sec->flags & SEC_RELOC) == 0
|| (sec->flags & SEC_HAS_CONTENTS) == 0
|| (info->disable_target_specific_optimizations
@@ -5284,7 +5286,7 @@ _bfd_riscv_relax_section (bfd *abfd, asection *sec,
|| type == R_RISCV_TPREL_LO12_I
|| type == R_RISCV_TPREL_LO12_S)
relax_func = _bfd_riscv_relax_tls_le;
- else if (!bfd_link_pic (info)
+ else if ((!bfd_link_pic (info) || bfd_link_pie (info))
&& (type == R_RISCV_PCREL_HI20
|| type == R_RISCV_PCREL_LO12_I
|| type == R_RISCV_PCREL_LO12_S))
diff --git a/gas/testsuite/gas/riscv/zicfisslp-64.d b/gas/testsuite/gas/riscv/zicfisslp-64.d
index 0eb1b87ab8d..1dba3a62b27 100644
--- a/gas/testsuite/gas/riscv/zicfisslp-64.d
+++ b/gas/testsuite/gas/riscv/zicfisslp-64.d
@@ -12,6 +12,14 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+cdc0c073[ ]+sspopchk[ ]+ra
[ ]+[0-9a-f]+:[ ]+cdc2c073[ ]+sspopchk[ ]+t0
[ ]+[0-9a-f]+:[ ]+cdc04573[ ]+ssrdp[ ]+a0
+[ ]+[0-9a-f]+:[ ]+48a5252f[ ]+ssamoswap.w[ ]+a0,a0,\(a0\)
+[ ]+[0-9a-f]+:[ ]+48a5252f[ ]+ssamoswap.w[ ]+a0,a0,\(a0\)
+[ ]+[0-9a-f]+:[ ]+4ca5252f[ ]+ssamoswap.w.aq[ ]+a0,a0,\(a0\)
+[ ]+[0-9a-f]+:[ ]+4ca5252f[ ]+ssamoswap.w.aq[ ]+a0,a0,\(a0\)
+[ ]+[0-9a-f]+:[ ]+4aa5252f[ ]+ssamoswap.w.rl[ ]+a0,a0,\(a0\)
+[ ]+[0-9a-f]+:[ ]+4aa5252f[ ]+ssamoswap.w.rl[ ]+a0,a0,\(a0\)
+[ ]+[0-9a-f]+:[ ]+4ea5252f[ ]+ssamoswap.w.aqrl[ ]+a0,a0,\(a0\)
+[ ]+[0-9a-f]+:[ ]+4ea5252f[ ]+ssamoswap.w.aqrl[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+48a5352f[ ]+ssamoswap.d[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+48a5352f[ ]+ssamoswap.d[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+4ca5352f[ ]+ssamoswap.d.aq[ ]+a0,a0,\(a0\)
diff --git a/gas/testsuite/gas/riscv/zicfisslp-64.s b/gas/testsuite/gas/riscv/zicfisslp-64.s
index 1199a430c95..21ff0e29689 100644
--- a/gas/testsuite/gas/riscv/zicfisslp-64.s
+++ b/gas/testsuite/gas/riscv/zicfisslp-64.s
@@ -6,6 +6,14 @@
sspopchk x1
sspopchk x5
ssrdp a0
+ ssamoswap.w a0,a0,0(a0)
+ ssamoswap.w a0,a0,(a0)
+ ssamoswap.w.aq a0,a0,0(a0)
+ ssamoswap.w.aq a0,a0,(a0)
+ ssamoswap.w.rl a0,a0,0(a0)
+ ssamoswap.w.rl a0,a0,(a0)
+ ssamoswap.w.aqrl a0,a0,0(a0)
+ ssamoswap.w.aqrl a0,a0,(a0)
ssamoswap.d a0, a0, 0(a0)
ssamoswap.d a0, a0, (a0)
ssamoswap.d.aq a0, a0, 0(a0)
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index ceb94a563e2..9e6c2ae45fb 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -1187,10 +1187,10 @@ const struct riscv_opcode riscv_opcodes[] =
{"c.sspush", 0, INSN_CLASS_ZICFISS_AND_ZCMOP, "d", MATCH_C_SSPUSH, MASK_C_SSPUSH, match_rd_x1x5_opcode, 0 },
{"c.sspopchk", 0, INSN_CLASS_ZICFISS_AND_ZCMOP, "d", MATCH_C_SSPOPCHK, MASK_C_SSPOPCHK, match_rd_x1x5_opcode, 0 },
{"ssrdp", 0, INSN_CLASS_ZICFISS, "d", MATCH_SSRDP, MASK_SSRDP, match_opcode, 0 },
-{"ssamoswap.w", 32, INSN_CLASS_ZICFISS, "d,t,0(s)", MATCH_SSAMOSWAP_W, MASK_SSAMOSWAP_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
-{"ssamoswap.w.aq", 32, INSN_CLASS_ZICFISS, "d,t,0(s)", MATCH_SSAMOSWAP_W|MASK_AQ, MASK_SSAMOSWAP_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
-{"ssamoswap.w.rl", 32, INSN_CLASS_ZICFISS, "d,t,0(s)", MATCH_SSAMOSWAP_W|MASK_RL, MASK_SSAMOSWAP_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
-{"ssamoswap.w.aqrl", 32, INSN_CLASS_ZICFISS, "d,t,0(s)", MATCH_SSAMOSWAP_W|MASK_AQRL, MASK_SSAMOSWAP_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"ssamoswap.w", 0, INSN_CLASS_ZICFISS, "d,t,0(s)", MATCH_SSAMOSWAP_W, MASK_SSAMOSWAP_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"ssamoswap.w.aq", 0, INSN_CLASS_ZICFISS, "d,t,0(s)", MATCH_SSAMOSWAP_W|MASK_AQ, MASK_SSAMOSWAP_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"ssamoswap.w.rl", 0, INSN_CLASS_ZICFISS, "d,t,0(s)", MATCH_SSAMOSWAP_W|MASK_RL, MASK_SSAMOSWAP_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"ssamoswap.w.aqrl", 0, INSN_CLASS_ZICFISS, "d,t,0(s)", MATCH_SSAMOSWAP_W|MASK_AQRL, MASK_SSAMOSWAP_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
{"ssamoswap.d", 64, INSN_CLASS_ZICFISS, "d,t,0(s)", MATCH_SSAMOSWAP_D, MASK_SSAMOSWAP_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
{"ssamoswap.d.aq", 64, INSN_CLASS_ZICFISS, "d,t,0(s)", MATCH_SSAMOSWAP_D|MASK_AQ, MASK_SSAMOSWAP_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
{"ssamoswap.d.rl", 64, INSN_CLASS_ZICFISS, "d,t,0(s)", MATCH_SSAMOSWAP_D|MASK_RL, MASK_SSAMOSWAP_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
--
2.34.1
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