[PATCH 1/2] RISC-V: Add OP_VE for .insn

[Kito Cheng]

OP_VE is the opcode space for crypto vector instructions.

Ref:
https://github.com/riscv/riscv-isa-manual/blob/main/src/vector-crypto.adoc#crypto-vector-cryptographic-instructions
---
 gas/config/tc-riscv.c                | 2 +-
 gas/doc/c-riscv.texi                 | 3 +++
 gas/testsuite/gas/riscv/insn-dwarf.d | 3 ++-
 gas/testsuite/gas/riscv/insn-na.d    | 3 ++-
 gas/testsuite/gas/riscv/insn.d       | 3 ++-
 gas/testsuite/gas/riscv/insn.s       | 2 ++
 6 files changed, 12 insertions(+), 4 deletions(-)

diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index cfaadea6c49..251a00e579a 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -902,7 +902,7 @@ static const struct opcode_name_t opcode_name_list[] =
   /*reserved    0x5b.  */
   {"JAL",       0x6f},
   {"SYSTEM",    0x73},
-  /*reserved    0x77.  */
+  {"OP_VE",     0x77},
   {"CUSTOM_3",  0x7b},
   /* >80b       0x7f.  */
 
diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index be3a09487f1..34b92e6adda 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -547,6 +547,9 @@ Opcode space for misc instructions.
 @item SYSTEM
 Opcode space for system instructions.
 
+@item OP_VE
+Opcode space for crypto vector instructions.
+
 @item CUSTOM_0
 @item CUSTOM_1
 @item CUSTOM_2
diff --git a/gas/testsuite/gas/riscv/insn-dwarf.d b/gas/testsuite/gas/riscv/insn-dwarf.d
index b8bd42dff18..d6c6e6e095e 100644
--- a/gas/testsuite/gas/riscv/insn-dwarf.d
+++ b/gas/testsuite/gas/riscv/insn-dwarf.d
@@ -82,5 +82,6 @@ insn.s +78 +0x16a.*
 insn.s +79 +0x180.*
 insn.s +80 +0x196.*
 insn.s +81 +0x1ac.*
-insn.s +- +0x1c2
+insn.s +83 +0x1c2.*
+insn.s +- +0x1c6
 #pass
diff --git a/gas/testsuite/gas/riscv/insn-na.d b/gas/testsuite/gas/riscv/insn-na.d
index 55bf301656b..47d12974af9 100644
--- a/gas/testsuite/gas/riscv/insn-na.d
+++ b/gas/testsuite/gas/riscv/insn-na.d
@@ -1,4 +1,4 @@
-#as: -march=rv32ifcv
+#as: -march=rv32ifcv_zvknha
 #source: insn.s
 #objdump: -dw -Mno-aliases
 
@@ -81,3 +81,4 @@ Disassembly of section .text:
 [^:]+:[ 	]+607f 33cc 55aa cdef 89ab 4567 0123 3210 7654 ba98 00dc[ 	]+\.insn[ 	]+22, 0x00dcba98765432100123456789abcdef55aa33cc607f
 [^:]+:[ 	]+607f 33cc 55aa cdef 89ab 4567 0123 3210 7654 ba98 fedc[ 	]+\.insn[ 	]+22, 0xfedcba98765432100123456789abcdef55aa33cc607f
 [^:]+:[ 	]+607f 33cc 55aa cdef 89ab 4567 0123 3210 7654 ba98 fedc[ 	]+\.insn[ 	]+22, 0xfedcba98765432100123456789abcdef55aa33cc607f
+[^:]+:[ 	]+ba862277[ 	]+vsha2ch\.vv[ 	]+v4,v8,v12
diff --git a/gas/testsuite/gas/riscv/insn.d b/gas/testsuite/gas/riscv/insn.d
index 9411a6b1e19..7ffb4e254ce 100644
--- a/gas/testsuite/gas/riscv/insn.d
+++ b/gas/testsuite/gas/riscv/insn.d
@@ -1,4 +1,4 @@
-#as: -march=rv32ifcv
+#as: -march=rv32ifcv_zvknha
 #objdump: -dr
 
 .*:[ 	]+file format .*
@@ -114,3 +114,4 @@ Disassembly of section .text:
 [^:]+:[ 	]+607f 33cc 55aa cdef[ 	]+\.insn[ 	]+22, 0xfedcba98765432100123456789abcdef55aa33cc607f
 [^:]+:[ 	]+89ab 4567 0123 3210 ?
 [^:]+:[ 	]+7654 ba98 fedc ?
+[^:]+:[ 	]+ba862277[ 	]+vsha2ch\.vv[ 	]+v4,v8,v12
diff --git a/gas/testsuite/gas/riscv/insn.s b/gas/testsuite/gas/riscv/insn.s
index 48db59b14e8..4f72d5be8f5 100644
--- a/gas/testsuite/gas/riscv/insn.s
+++ b/gas/testsuite/gas/riscv/insn.s
@@ -79,3 +79,5 @@ target:
 	.insn 22, 0x00dcba98765432100123456789abcdef55aa33cc607f
 	.insn 0xfedcba98765432100123456789abcdef55aa33cc607f
 	.insn 22, 0xfedcba98765432100123456789abcdef55aa33cc607f
+
+	.insn r  OP_VE, 0b010, 0b1011101, x4, x12, x8
-- 
2.34.1