[PATCH v3] RISC-V: Add support for ssdbltrp and smdbltrp extension.

[chendongyan@isrc.iscas.ac.cn]

This implements the ssdbltrp extensons, version 1.0[1] and the smdbltrp extensions, version1.0[2].

[1] https://github.com/riscv/riscv-isa-manual/blob/main/src/ssdbltrp.adoc
[2] https://github.com/riscv/riscv-isa-manual/blob/main/src/smdbltrp.adoc

Changes for v2:
- Move the additions in the "gas/News" section to the top of the file.
- Modify the indentation format of the case in the "gas/config/tc-riscv.c" file.

Changes for v3:
- Merge the two additions in the "gas/NEWS" into one.
- Remove the changes in the "config/tc-riscv.c".

bfd/ChangeLog:

      * elfxx-riscv.c: Add 'ssdbltrp' and 'smdbltrp' to the list of konwn standard extensions.

gas/ChangeLog:

      * NEWS: Updated.
      * testsuite/gas/riscv/march-help.l: Ditto.
---
 bfd/elfxx-riscv.c                    | 4 ++++
 gas/NEWS                             | 2 ++
 gas/testsuite/gas/riscv/march-help.l | 2 ++
 3 files changed, 8 insertions(+)

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 45da83e6926..49b4d5ca4eb 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1272,6 +1272,8 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"sstvala", "+zicsr", check_implicit_always},
   {"sstvecd", "+zicsr", check_implicit_always},
   {"ssu64xl", "+zicsr", check_implicit_always},
+  {"ssdbltrp", "+zicsr", check_implicit_always},
+  {"smdbltrp", "+zicsr", check_implicit_always},

   {"svade", "+zicsr", check_implicit_always},
   {"svadu", "+zicsr", check_implicit_always},
@@ -1458,6 +1460,8 @@ static struct riscv_supported_ext riscv_supported_std_s_ext[] =
   {"sstvala",          ISA_SPEC_CLASS_DRAFT,         1, 0, 0 },
   {"sstvecd",          ISA_SPEC_CLASS_DRAFT,         1, 0, 0 },
   {"ssu64xl",          ISA_SPEC_CLASS_DRAFT,         1, 0, 0 },
+  {"ssdbltrp",         ISA_SPEC_CLASS_DRAFT,         1, 0, 0 },
+  {"smdbltrp",         ISA_SPEC_CLASS_DRAFT,         1, 0, 0 },
   {"svade",            ISA_SPEC_CLASS_DRAFT,         1, 0, 0 },
   {"svadu",            ISA_SPEC_CLASS_DRAFT,         1, 0, 0 },
   {"svbare",           ISA_SPEC_CLASS_DRAFT,         1, 0, 0 },
diff --git a/gas/NEWS b/gas/NEWS
index 23eda334ec6..e8fa3f4a16e 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -13,6 +13,8 @@
   (xcvbitmanip, xcvsimd) extensions with version 1.0 and more SiFive
   extensions (xsfvqmaccdod, xsfvqmaccqoq and xsfvfnrclipxfqf).

+  Add support for the RISC-V s[sm]dbltrp extension, version 1.0.
+
 Changes in 2.43:

 * Add support for LoongArch .option for fine-grained control of assembly
diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l
index 71cccb77102..c3e51c0ca2b 100644
--- a/gas/testsuite/gas/riscv/march-help.l
+++ b/gas/testsuite/gas/riscv/march-help.l
@@ -127,6 +127,8 @@ All available -march extensions for RISC-V:
      sstvala                                 1.0
      sstvecd                                 1.0
      ssu64xl                                 1.0
+     ssdbltrp                                1.0
+     smdbltrp                                1.0
      svade                                   1.0
      svadu                                   1.0
      svbare                                  1.0
--
2.43.0
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