[EXT] [PATCH v1] Support for RFC02691

[Peter Bergner]

On 8/26/25 11:05 AM, Abhay Kandpal wrote:
> PowerPC: Vector Instructions for Deeply Compressed Weight for AI

Maybe add the RFC number similar to Surya's latest commits.




> opcodes/
> 	* Add support for vucmprhn, vucmprln, vucmprhb, vucmprlb,
> 		vucmprhh, vucmprlh, vupkhsntob, vupklsntob, vupkint4tobf16,
> 		vupkint8tobf16, vupkint4tofp32, vupkint8tofp32
> 	* Added new Macros to selector bit value with UIM
> 		(VXSEL5, VXSEL4, VXSEL3, VXSEL2, UIMM1)

The indentation of the lines following the "* Add ..." should be
directly under the "Add"s.




> +/* A VX_MASK with a UIMM1 field.  */
> +#define VXUIMM1_MASK (VX_MASK | (0xF << 17))

Let's be consistent and use 0xf here rather than 0xF.
I see there are some cases in the opcode table, but those are
much less common than the uses everywhere else.





>  {"vmaxuh",	VX (4,	66),	VX_MASK,     PPCVEC,	0,		{VD, VA, VB}},
> +{"vucmprln",	VX (4,   67),	VX_MASK,     FUTURE,	0,		{VD, VA, VB}},
>  {"vrlh",	VX (4,	68),	VX_MASK,     PPCVEC,	0,		{VD, VA, VB}},

...

>  {"vslh",	VX (4, 324),	VX_MASK,     PPCVEC,	0,		{VD, VA, VB}},
> +{"vucmprlh",	VX (4,  323),	VX_MASK,     FUTURE,	0,		{VD, VA, VB}},
>  {"vrlqnm",	VX (4, 325),	VX_MASK,     POWER10,	0,		{VD, VA, VB}},


There are some whitespace differences here and in the other new mnemonics.
The old code uses a TAB and you're using spaces.  Please match the surrounding
code.




> @@ -5394,6 +5410,12 @@ const struct powerpc_opcode powerpc_opcodes[] = {
>  {"vaddcuw",	VX (4, 384),	VX_MASK,     PPCVEC,	0,		{VD, VA, VB}},
>  {"vmaxsw",	VX (4, 386),	VX_MASK,     PPCVEC,	0,		{VD, VA, VB}},
>  {"vslw",	VX (4, 388),	VX_MASK,     PPCVEC,	0,		{VD, VA, VB}},
> +{"vupkhsntob",	VXSEL5 (4, 387, 0),	VXVA_MASK,   FUTURE,	0,		{VD, VB}},
> +{"vupklsntob",	VXSEL5 (4, 387, 1),	VXVA_MASK,   FUTURE,	0,		{VD, VB}},
> +{"vupkint4tobf16",	VXSEL3 (4, 387, 2),	VXUIMM2_MASK, FUTURE,	0,		{VD, VB, UIMM2}},
> +{"vupkint8tobf16",	VXSEL4 (4, 387, 1),	VXUIMM1_MASK, FUTURE,	0,		{VD, VB, UIMM1}},
> +{"vupkint4tofp32",	VXSEL2 (4, 387, 2),	VXUIMM3_MASK, FUTURE,	0,		{VD, VB, UIMM3}},
> +{"vupkint8tofp32",	VXSEL3 (4, 387, 3),	VXUIMM2_MASK, FUTURE,	0,		{VD, VB, UIMM2}},
>  {"vrlwnm",	VX (4, 389),	VX_MASK,     PPCVEC3,	0,		{VD, VA, VB}},

We sort the table by major opcode and then secondary opcode, so these new
mnemonics should be placed between the "vmaxsw" and "vslw" mnemonics.

As for the ordering between themselves, I think the order should be:

> +{"vupkhsntob",	VXSEL5 (4, 387, 0),	VXVA_MASK,   FUTURE,	0,		{VD, VB}},
> +{"vupklsntob",	VXSEL5 (4, 387, 1),	VXVA_MASK,   FUTURE,	0,		{VD, VB}},
> +{"vupkint8tobf16",	VXSEL4 (4, 387, 1),	VXUIMM1_MASK, FUTURE,	0,		{VD, VB, UIMM1}},
> +{"vupkint4tobf16",	VXSEL3 (4, 387, 2),	VXUIMM2_MASK, FUTURE,	0,		{VD, VB, UIMM2}},
> +{"vupkint8tofp32",	VXSEL3 (4, 387, 3),	VXUIMM2_MASK, FUTURE,	0,		{VD, VB, UIMM2}},
> +{"vupkint4tofp32",	VXSEL2 (4, 387, 2),	VXUIMM3_MASK, FUTURE,	0,		{VD, VB, UIMM3}},


Peter