[PATCH] RISC-V: Add support for sdtrig and ssstrict extensions.

[Dongyan Chen]

This implements the sdtrig and ssstrict extensions, version 1.0[1].

[1]https://github.com/riscv/riscv-profiles/blob/main/src/rva23-profile.adoc

bfd/ChangeLog:

	* elfxx-riscv.c: Handle sdtrig and ssstrict.

gas/ChangeLog:

	* NEWS: Updated.
	* testsuite/gas/riscv/march-help.l: Updated.

---
 bfd/elfxx-riscv.c                    | 2 ++
 gas/NEWS                             | 2 ++
 gas/testsuite/gas/riscv/march-help.l | 2 ++
 3 files changed, 6 insertions(+)

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index ec254915c76..187c3b8f410 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1447,6 +1447,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =

 static struct riscv_supported_ext riscv_supported_std_s_ext[] =
 {
+  {"sdtrig",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"shcounterenw",	ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"shgatpa",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"shtvala",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
@@ -1468,6 +1469,7 @@ static struct riscv_supported_ext riscv_supported_std_s_ext[] =
   {"sscounterenw",	ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"ssctr",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"ssstateen",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
+  {"ssstrict",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"sstc",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"sstvala",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"sstvecd",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
diff --git a/gas/NEWS b/gas/NEWS
index b4fc2e9e9be..9f5e7c3f091 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -16,6 +16,8 @@

 * Add support for the x86 Zhaoxin PadLock XMODX instructions.

+* Add support for RISC-V sdtrig and ssstrict extensions, v1.0.
+
 Changes in 2.44:

 * Add support for the x86 Intel Diamond Rapids AMX instructions, including
diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l
index d77472fda9c..a471623dbf4 100644
--- a/gas/testsuite/gas/riscv/march-help.l
+++ b/gas/testsuite/gas/riscv/march-help.l
@@ -107,6 +107,7 @@ All available -march extensions for RISC-V:
 	zcmop                                   1.0
 	zcmp                                    1.0
 	zcmt                                    1.0
+	sdtrig                                  1.0
 	shcounterenw                            1.0
 	shgatpa                                 1.0
 	shtvala                                 1.0
@@ -128,6 +129,7 @@ All available -march extensions for RISC-V:
 	sscounterenw                            1.0
 	ssctr                                   1.0
 	ssstateen                               1.0
+	ssstrict                                1.0
 	sstc                                    1.0
 	sstvala                                 1.0
 	sstvecd                                 1.0
--
2.43.0