[PATCH 13/21] MIPS: Update encoding of d16mule MXU instruction

[Jovan Dmitrovic]

From: Andrew Bennett <andrew.bennett@imgtec.com>

The code for the d16mule instruction has been modified to encode an
additional operand (xr4) in the instruction. This is reflected in the
new line of code for encoding, which now uses the mask 0xff00003f
instead of the previous 0xff3c003f, allowing for better precision in
operand encoding. In the file gas/testsuite/gas/mips/mxu.s, the operand
arguments for the d16mule instruction have been changed to now include
the additional operand xr4 for each of the instruction options.

Cherry-picked bc381d4
from https://github.com/MIPS/binutils-gdb

Signed-off-by: Andrew Bennett <andrew.bennett@imgtec.com>
Signed-off-by: Faraz Shahbazker <fshahbazker@wavecomp.com>
Signed-off-by: Milica Matic <milica.matic@htecgroup.com>
---
 gas/testsuite/gas/mips/mxu.d | 16 ++++++++--------
 gas/testsuite/gas/mips/mxu.s | 18 +++++++++---------
 opcodes/mips-opc.c           |  2 +-
 3 files changed, 18 insertions(+), 18 deletions(-)

diff --git a/gas/testsuite/gas/mips/mxu.d b/gas/testsuite/gas/mips/mxu.d
index 68a54ccb671..507bd9b6b3a 100644
--- a/gas/testsuite/gas/mips/mxu.d
+++ b/gas/testsuite/gas/mips/mxu.d
@@ -190,14 +190,14 @@ Disassembly of section \.text:
 [0-9a-f]+ <[^>]*> 7040c849 	d16mulf	xr1,xr2,xr3,LW
 [0-9a-f]+ <[^>]*> 7080c849 	d16mulf	xr1,xr2,xr3,HW
 [0-9a-f]+ <[^>]*> 70c0c849 	d16mulf	xr1,xr2,xr3,XW
-[0-9a-f]+ <[^>]*> 7100c849 	d16mule	xr1,xr2,xr3,WW
-[0-9a-f]+ <[^>]*> 7140c849 	d16mule	xr1,xr2,xr3,LW
-[0-9a-f]+ <[^>]*> 7180c849 	d16mule	xr1,xr2,xr3,HW
-[0-9a-f]+ <[^>]*> 71c0c849 	d16mule	xr1,xr2,xr3,XW
-[0-9a-f]+ <[^>]*> 7100c849 	d16mule	xr1,xr2,xr3,WW
-[0-9a-f]+ <[^>]*> 7140c849 	d16mule	xr1,xr2,xr3,LW
-[0-9a-f]+ <[^>]*> 7180c849 	d16mule	xr1,xr2,xr3,HW
-[0-9a-f]+ <[^>]*> 71c0c849 	d16mule	xr1,xr2,xr3,XW
+[0-9a-f]+ <[^>]*> 7110c849 	d16mule	xr1,xr2,xr3,xr4,WW
+[0-9a-f]+ <[^>]*> 7150c849 	d16mule	xr1,xr2,xr3,xr4,LW
+[0-9a-f]+ <[^>]*> 7190c849 	d16mule	xr1,xr2,xr3,xr4,HW
+[0-9a-f]+ <[^>]*> 71d0c849 	d16mule	xr1,xr2,xr3,xr4,XW
+[0-9a-f]+ <[^>]*> 7110c849 	d16mule	xr1,xr2,xr3,xr4,WW
+[0-9a-f]+ <[^>]*> 7150c849 	d16mule	xr1,xr2,xr3,xr4,LW
+[0-9a-f]+ <[^>]*> 7190c849 	d16mule	xr1,xr2,xr3,xr4,HW
+[0-9a-f]+ <[^>]*> 71d0c849 	d16mule	xr1,xr2,xr3,xr4,XW
 [0-9a-f]+ <[^>]*> 7010c84d 	s16mad	xr1,xr2,xr3,xr4,A,WW
 [0-9a-f]+ <[^>]*> 7050c84d 	s16mad	xr1,xr2,xr3,xr4,A,LW
 [0-9a-f]+ <[^>]*> 7090c84d 	s16mad	xr1,xr2,xr3,xr4,A,HW
diff --git a/gas/testsuite/gas/mips/mxu.s b/gas/testsuite/gas/mips/mxu.s
index 76504516e65..f9643d0624c 100644
--- a/gas/testsuite/gas/mips/mxu.s
+++ b/gas/testsuite/gas/mips/mxu.s
@@ -138,15 +138,15 @@ test_mxu:
 	d16mulf	xr1, xr2, xr3, 2
 	d16mulf	xr1, xr2, xr3, 3
 
-	d16mule	xr1, xr2, xr3, WW
-	d16mule	xr1, xr2, xr3, LW
-	d16mule	xr1, xr2, xr3, HW
-	d16mule	xr1, xr2, xr3, XW
-
-	d16mule	xr1, xr2, xr3, 0
-	d16mule	xr1, xr2, xr3, 1
-	d16mule	xr1, xr2, xr3, 2
-	d16mule	xr1, xr2, xr3, 3
+	d16mule	xr1, xr2, xr3, xr4, WW
+	d16mule	xr1, xr2, xr3, xr4, LW
+	d16mule	xr1, xr2, xr3, xr4, HW
+	d16mule	xr1, xr2, xr3, xr4, XW
+
+	d16mule	xr1, xr2, xr3, xr4, 0
+	d16mule	xr1, xr2, xr3, xr4, 1
+	d16mule	xr1, xr2, xr3, xr4, 2
+	d16mule	xr1, xr2, xr3, xr4, 3
 
 	s16mad	xr1, xr2, xr3, xr4,A,WW
 	s16mad	xr1, xr2, xr3, xr4,A,LW
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 19fd841c873..6a4fd20a9da 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -3245,7 +3245,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 /* MXU Extension.  */
 {"d16mul",		"`=,`b,`c,`d,`o",	0x70000008, 0xff00003f,	TRAP,		0,		0,		MXU,	0 },
 {"d16mulf",		"`=,`b,`c,`o",		0x70000009, 0xff3c003f,	TRAP,		0,		0,		MXU,	0 },
-{"d16mule",		"`=,`b,`c,`o",		0x71000009, 0xff3c003f,	TRAP,		0,		0,		MXU,	0 },
+{"d16mule",		"`=,`b,`c,`d,`o",	0x71000009, 0xff00003f,	TRAP,		0,		0,		MXU,	0 },
 {"d16mac",		"`=,`b,`c,`d,`a,`o",	0x7000000a, 0xfc00003f,	TRAP,		0,		0,		MXU,	0 },
 {"d16macf",		"`=,`b,`c,`d,`a,`o",	0x7000000b, 0xfc00003f,	TRAP,		0,		0,		MXU,	0 },
 {"d16madl",		"`=,`b,`c,`d,`a,`o",	0x7000000c, 0xfc00003f,	TRAP,		0,		0,		MXU,	0 },
-- 
2.34.1