[PATCH 0/5] x86: further templatization

Jiang, Haochen haochen.jiang@intel.com
Wed Sep 25 07:38:05 GMT 2024


> From: Jan Beulich <jbeulich@suse.com>
> Sent: Wednesday, September 25, 2024 3:02 PM
> 
> On 25.09.2024 08:59, Jiang, Haochen wrote:
> >> From: Jan Beulich <jbeulich@suse.com>
> >> Sent: Friday, September 6, 2024 6:24 PM
> >>
> >> ... in part to reduce churn by the upcoming AVX10.2 work.
> >>
> >> 1: templatize SIMD FP arithmetic templates
> >> 2: further templatize FMA templates
> >> 3: templatize SIMD FP binary-logic templates
> >> 4: templatize SIMD sign-/zero-extension templates
> >> 5: templatize SIMD narrowing-move templates
> >
> > When will you check in this patches? I suppose if the testcases
> > passed, they are ok.
> 
> I had been travelling, then on PTO. Later this week, I expect.

I c, then no worry since I will be on holiday soon.

Wish you a good trip!

Thx,
Haochen

> 
> Jan


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