[PATCH] RISC-V: Update the doc to match ISA manual
Kito Cheng
kito.cheng@gmail.com
Tue Oct 29 00:34:07 GMT 2024
Oh I realized I should also fix all other func* to funct*, let me send v2 patch
On Tue, Oct 29, 2024 at 8:32 AM Kito Cheng <kito.cheng@sifive.com> wrote:
>
> ISA manual use funct7 rather than func7[1], and I realized that may something I
> typo at beginning when I write the patch for `.insn` support...:P
>
> [1] https://github.com/riscv/riscv-isa-manual/blob/main/src/rv32.adoc#integer-register-register-operations
> ---
> gas/doc/c-riscv.texi | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
> index 5614e766988..915dfefe56b 100644
> --- a/gas/doc/c-riscv.texi
> +++ b/gas/doc/c-riscv.texi
> @@ -442,7 +442,7 @@ instruction formats:
> @multitable @columnfractions .15 .40
> @item opcode7 @tab Unsigned immediate or opcode name for 7-bits opcode.
> @item opcode2 @tab Unsigned immediate or opcode name for 2-bits opcode.
> -@item func7 @tab Unsigned immediate for 7-bits function code.
> +@item funct7 @tab Unsigned immediate for 7-bits function code.
> @item func6 @tab Unsigned immediate for 6-bits function code.
> @item func4 @tab Unsigned immediate for 4-bits function code.
> @item func3 @tab Unsigned immediate for 3-bits function code.
> @@ -554,10 +554,10 @@ The following table lists the RISC-V instruction formats that are available
> with the @samp{.insn} pseudo directive:
>
> @table @code
> -@item R type: .insn r opcode7, func3, func7, rd, rs1, rs2
> +@item R type: .insn r opcode7, func3, funct7, rd, rs1, rs2
> @verbatim
> +-------+-----+-----+-------+----+---------+
> -| func7 | rs2 | rs1 | func3 | rd | opcode7 |
> +| funct7 | rs2 | rs1 | func3 | rd | opcode7 |
> +-------+-----+-----+-------+----+---------+
> 31 25 20 15 12 7 0
> @end verbatim
> --
> 2.34.1
>
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