[PATCH v1] x86: Support ZHAOXIN GMI instructions

[Jiang, Haochen]

> From: mayshao-oc <mayshao-oc@zhaoxin.com>
> Sent: Monday, October 14, 2024 10:03 AM
> To: binutils@sourceware.org
> 
>         This patch adds support for Zhaoxin GMI instructions.
>         The documentation is attached for your reference.
>         Test ok, ok for trunk?

The disassembler part looks extremely weird to me.

I suppose the adding for this is not correct:

@@ -1315,7 +1320,8 @@ enum
 enum
 {
   THREE_BYTE_0F38 = 0,
-  THREE_BYTE_0F3A
+  THREE_BYTE_0F3A,
+  THREE_BYTE_0FA6
 };

My understanding comes following, correct me if I am wrong.

Let's take inst sm2 for example. The full encoding for sm2 is
0xf20fa6c0. In the encoding, a6 is opcode and c0 is modrm byte.
This means a6 should be the "index", not a6c0 in your this part
of patch:

@@ -1050,6 +1051,10 @@ enum
   PREFIX_0F7D,
   PREFIX_0F7E,
   PREFIX_0F7F,
+  PREFIX_0FA6C0,
+  PREFIX_0FA6C8,
+  PREFIX_0FA6D0,
+  PREFIX_0FA6E8,

You can translate modrm byte c0 to 11 000 000. Therefore, the REG
is always 0. That is why montmul occupies the first row of REG_0FA6
entry, since the opcode for it is 0xf30fa6c0.

The actual change should be something like adding prefix table pass
for montmul/sm2, since one of them is f2, the other is f3.

Thx,
Haochen

> 
> BR
> Mayshao