[PATCH] RISC-V: Check the Zca extension when disabling the C extension using .option norvc.

[Andrew Waterman]

On Mon, Oct 7, 2024 at 11:32 PM Nelson Chu <nelson@rivosinc.com> wrote:
>
> Hi,
>
> According to the newest ISA spec, https://github.com/riscv/riscv-isa-manual/blob/main/src/zc.adoc, the C is actually same as Zca, Zcf and Zcd, so this change looks conflict.  The original code should be correct, the RVC flag means enable the C extension, so NORVC means disable C, and it makes sense to disable the RVC flag.  But this patch also reminds us that the current toolchain needs to be updated to the newest spec.
>
> 1. C needs imply Zca, Zcf and Zcd, so the implicit table needs to be updated.
>
> 2. Removing extensions using ".option arch" is more complicated than the first implemented.  For this case, C is the set of Zca, Zcf and Zcd, so we need to imply those extensions when adding C, and should also need to remove those extensions when removing C.  That is - riscv_update_subset (&riscv_rps_as, "-c,-zca,-zcf,-zcd") for .option norvc.  But unfortunately it's not always work to directly remove the extension from the implicit table in reverse.  For example, zcd implies d and zca, but remove zcd doesn't mean remove d since zcd isn't a super set of d and zca.
>
> cc Andrew in case I am wrong ;)

Nelson's right about the ISA implications.

".option rvc" is of course not defined by the ISA, and the ASM manual
doesn't do a great job of defining it, either.  But the original
intent was to suppress automatic instruction compression (regardless
of exactly which extension it was). IOW, the intent was to make it so
that all instructions that are notionally 32 bits long remain 32 bits
long.  Enabling or disabling extensions was not the intent.

>
> Thanks
> Nelson
>
>
> On Fri, Oct 4, 2024 at 3:12 PM Ethan Yu-Cheng Liang(梁淯程) <ycl669@andestech.com> wrote:
>>
>> .option norvc disables only the C extension, not all 16-bit instructions.
>>
>> Signed-off-by: Ethan Yu-Cheng Liang <ycl669@andestech.com>
>> ---
>>  gas/config/tc-riscv.c | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
>> index ef455e449b9..4ef7b8e689e 100644
>> --- a/gas/config/tc-riscv.c
>> +++ b/gas/config/tc-riscv.c
>> @@ -4917,7 +4917,7 @@ s_riscv_option (int x ATTRIBUTE_UNUSED)
>>      {
>>        riscv_update_subset (&riscv_rps_as, "-c");
>>        riscv_set_arch_str (&riscv_rps_as.subset_list->arch_str);
>> -      riscv_set_rvc (false);
>> +      riscv_set_rvc (riscv_subset_supports (&riscv_rps_as, "zca"));
>>      }
>>    else if (strcmp (name, "pic") == 0)
>>      riscv_opts.pic = true;
>> --
>> 2.45.2
>>
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