[PATCH] RISC-V: Add an implicit dependency for Zawrs

Xiao Zeng zengxiao@eswincomputing.com
Tue Oct 8 06:06:58 GMT 2024


There is a description in <https://github.com/riscv/riscv-isa-manual/blob/main/src/zawrs.adoc>:

"The instructions in the Zawrs extension are only useful in conjunction
with the LR instruction, which is provided by the Zalrsc component
of the A extension."

It can be concluded that: zawrs -> zalrsc.

The implementation in gcc is as follows:
<https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=c01e3aaae79ecd439ad35063db3dee9775f3aefa>

bfd/ChangeLog:

	* elfxx-riscv.c: zawrs -> zalrsc.

gas/ChangeLog:

	* testsuite/gas/riscv/imply.d: Add implicit dependency
	testing for zawrs.
	* testsuite/gas/riscv/imply.s: Updated.

Signed-off-by: Xiao Zeng <zengxiao@eswincomputing.com>
---
 bfd/elfxx-riscv.c               | 1 +
 gas/testsuite/gas/riscv/imply.d | 1 +
 gas/testsuite/gas/riscv/imply.s | 1 +
 3 files changed, 3 insertions(+)

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 4b48d8ee9f0..b7b4d95195e 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1184,6 +1184,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
 
   {"zabha", "+zaamo", check_implicit_always},
   {"zacas", "+zaamo", check_implicit_always},
+  {"zawrs", "+zalrsc", check_implicit_always},
   {"a", "+zaamo,+zalrsc", check_implicit_always},
 
   {"xsfvcp", "+zve32x", check_implicit_always},
diff --git a/gas/testsuite/gas/riscv/imply.d b/gas/testsuite/gas/riscv/imply.d
index 26eff8c650a..64dda77a9f8 100644
--- a/gas/testsuite/gas/riscv/imply.d
+++ b/gas/testsuite/gas/riscv/imply.d
@@ -17,6 +17,7 @@ SYMBOL TABLE:
 [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_m2p0_zmmul1p0
 [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zaamo1p0_zabha1p0
 [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zaamo1p0_zacas1p0
+[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zalrsc1p0_zawrs1p0
 [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_a2p1_zaamo1p0_zalrsc1p0
 [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfvcp1p0
 [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0
diff --git a/gas/testsuite/gas/riscv/imply.s b/gas/testsuite/gas/riscv/imply.s
index dabb08d8c8b..c831ea63f04 100644
--- a/gas/testsuite/gas/riscv/imply.s
+++ b/gas/testsuite/gas/riscv/imply.s
@@ -18,6 +18,7 @@ imply m
 
 imply zabha
 imply zacas
+imply zawrs
 imply a
 
 imply xsfvcp
-- 
2.17.1



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