[PATCH 6/6] Support Intel AMX-MOVRS

[Jiang, Haochen]

> From: Jan Beulich <jbeulich@suse.com>
> Sent: Tuesday, November 19, 2024 5:08 PM
> 
> On 19.11.2024 06:46, Jiang, Haochen wrote:
> >> From: Jan Beulich <jbeulich@suse.com>
> >> Sent: Monday, November 18, 2024 11:39 PM
> >> To: Jiang, Haochen <haochen.jiang@intel.com>; Hu, Lin1
> <lin1.hu@intel.com>
> >> Cc: binutils@sourceware.org; H.J. Lu <hjl.tools@gmail.com>
> >> Subject: Re: [PATCH 6/6] Support Intel AMX-MOVRS
> >>
> >> Judging from VMOVRS{B,W,D,Q}, shouldn't the RS infix move a little earlier,
> >> ahead of the element width specifier: T2RPNTLVRSW{Z0,Z1}{,T1}?
> >> ...
> >> Same here: TILELOADRSD{,T1} would seem like a better match for
> >> VMOVRS{B,W,D,Q}.
> >
> > Per my understanding, D is the element size in tile, while RS hint is for whole
> > tile, not for the elements in tile. That is why RS will not appear before D.
> 
> Yet the same can be said for a vector then, when it's VMOVRS{B,W,D,Q}. Of
> course the question could also be put the other way around, requesting
> VMOVRS{B,W,D,Q} to be changed. Yet then for all vector and (prior) tile
> insns element size is last, with everything pertaining to the whole
> vector/tile coming first (take e.g. VGATHERPF<n>{D,Q}P{S,D}). All I'm
> - as usual - asking for is consistency. Which in this case may actually
> mean moving W to the very end of the mnemonics, unlike I said in my
> original reply: i.e. T2RPNTLVRS{Z0,Z1}W{,T1} or T2RPNTLVRS{Z0,Z1}{,T1}W.
> I didn't spell out these forms because there's no precedent for Z<n>
> (and maybe T<n>, albeit the S/G prefetches have some similarity there)
> combined with {B,W,D,Q}, and hence their ordering doesn't (currently)
> matter as far as consistency goes.

An update on this: I am confirming this with HW.

Thx,
Haochen