[PATCH 1/6] Support Intel AMX-TRANSPOSE
Jan Beulich
jbeulich@suse.com
Mon Nov 18 15:34:13 GMT 2024
On 13.11.2024 09:44, Haochen Jiang wrote:
> --- a/opcodes/i386-opc.tbl
> +++ b/opcodes/i386-opc.tbl
> @@ -3183,14 +3183,27 @@ xresldtrk, 0xf20f01e9, TSXLDTRK, NoSuf, {}
>
> // TSXLDTRK instructions end.
>
> +#define TMMPairOperand0 TMMPairOperand=1
> +#define TMMPairOperand1 TMMPairOperand=2
> +#define TMMPairOperand2 TMMPairOperand=4
> +
> // AMX instructions.
>
> ldtilecfg, 0x49/0, APX_F(AMX_TILE), Modrm|Vex128|EVex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex }
> sttilecfg, 0x6649/0, APX_F(AMX_TILE), Modrm|Vex128|EVex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex }
>
> +t2rpntlvwz0, 0x6e, AMX_TRANSPOSE, TMMPairOperand1|Sibmem|Vex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex, RegTMM }
> +t2rpntlvwz0t1, 0x6f, AMX_TRANSPOSE, TMMPairOperand1|Sibmem|Vex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex, RegTMM }
> +t2rpntlvwz1, 0x666e, AMX_TRANSPOSE, TMMPairOperand1|Sibmem|Vex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex, RegTMM }
> +t2rpntlvwz1t1, 0x666f, AMX_TRANSPOSE, TMMPairOperand1|Sibmem|Vex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex, RegTMM }
Question here as well: What about APX? With binutils already supporting APX,
the new features can't be considered complete without the APX forms also
implemented / tested. At the very least there shouldn't be a NEWS entry just
yet, or it shouldn't claim full support.
Jan
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