[PATCH 5/6] Support Intel AMX-FP8
Haochen Jiang
haochen.jiang@intel.com
Wed Nov 13 08:44:34 GMT 2024
From: Liwei Xu <liwei.xu@intel.com>
In this patch, we will support AMX-FP8 feature. No special handling.
gas/ChangeLog:
* NEWS: Support Intel AMX-FP8.
* config/tc-i386.c: Add amx_fp8.
* doc/c-i386.texi: Document .amx_fp8.
* testsuite/gas/i386/i386.exp: Run AMX-TRANSPOSE tests.
* testsuite/gas/i386/x86-64.exp: Run AMX-FP8 tests.
* testsuite/gas/i386/amx-fp8-inval.l: New test.
* testsuite/gas/i386/amx-fp8-inval.s: Ditto.
* testsuite/gas/i386/x86-64-amx-fp8-intel.d: Ditto.
* testsuite/gas/i386/x86-64-amx-fp8-inval.l: Ditto.
* testsuite/gas/i386/x86-64-amx-fp8-inval.s: Ditto.
* testsuite/gas/i386/x86-64-amx-fp8.d: Ditto.
* testsuite/gas/i386/x86-64-amx-fp8.s: Ditto.
opcodes/ChangeLog:
* i386-dis.c (PREFIX_VEX_MAP5_FD_X86_64_L_0_W_0): New.
(X86_64_VEX_MAP5_FD): Ditto.
(VEX_LEN_MAP5_FD_X86_64): Ditto.
(VEX_W_MAP5_FD_X86_64_L_0):Ditto.
(prefix_table): Add PREFIX_VEX_MAP5_FD_X86_64_L_0_W_0.
(x86_64_table): Add X86_64_VEX_MAP5_FD.
(vex_len_table): Add VEX_LEN_MAP5_FD_X86_64.
(vex_w_table): Add VEX_W_MAP5_FD_X86_64_L_0.
* i386-gen.c: Add CPU_AMX_FP8_FLAGS and
CPU_ANY_AMX_FP8_FLAGS.
* i386-init.h: Regenerated.
* i386-mnem.h: Ditto.
* i386-opc.h: Add cpuamx_fp8.
* i386-opc.tbl: Add AMX_FP8 instructions.
* i386-tbl.h: Regenerated.
---
gas/NEWS | 2 +
gas/config/tc-i386.c | 1 +
gas/doc/c-i386.texi | 3 +-
gas/testsuite/gas/i386/amx-fp8-inval.l | 9 +
gas/testsuite/gas/i386/amx-fp8-inval.s | 13 +
gas/testsuite/gas/i386/i386.exp | 1 +
gas/testsuite/gas/i386/x86-64-amx-fp8-intel.d | 19 +
gas/testsuite/gas/i386/x86-64-amx-fp8-inval.l | 9 +
gas/testsuite/gas/i386/x86-64-amx-fp8-inval.s | 13 +
gas/testsuite/gas/i386/x86-64-amx-fp8.d | 17 +
gas/testsuite/gas/i386/x86-64-amx-fp8.s | 23 +
gas/testsuite/gas/i386/x86-64.exp | 3 +
opcodes/i386-dis.c | 29 +-
opcodes/i386-gen.c | 3 +
opcodes/i386-init.h | 688 +++++-----
opcodes/i386-mnem.h | 1184 +++++++++--------
opcodes/i386-opc.h | 3 +
opcodes/i386-opc.tbl | 4 +
opcodes/i386-tbl.h | 272 ++--
19 files changed, 1260 insertions(+), 1036 deletions(-)
create mode 100644 gas/testsuite/gas/i386/amx-fp8-inval.l
create mode 100644 gas/testsuite/gas/i386/amx-fp8-inval.s
create mode 100644 gas/testsuite/gas/i386/x86-64-amx-fp8-intel.d
create mode 100644 gas/testsuite/gas/i386/x86-64-amx-fp8-inval.l
create mode 100644 gas/testsuite/gas/i386/x86-64-amx-fp8-inval.s
create mode 100644 gas/testsuite/gas/i386/x86-64-amx-fp8.d
create mode 100644 gas/testsuite/gas/i386/x86-64-amx-fp8.s
diff --git a/gas/NEWS b/gas/NEWS
index 56143b9b27e..ba63043002e 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,5 +1,7 @@
-*- text -*-
+* Add support for Intel AMX-FP8 instructions.
+
* Add support for Intel AMX-TF32 instructions.
* Add support for Intel AMX-AVX512 instructions.
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 574d7946dad..504d1e099f4 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -1185,6 +1185,7 @@ static const arch_entry cpu_arch[] =
SUBARCH (amx_transpose, AMX_TRANSPOSE, ANY_AMX_TRANSPOSE, false),
SUBARCH (amx_avx512, AMX_AVX512, ANY_AMX_AVX512, false),
SUBARCH (amx_tf32, AMX_TF32, ANY_AMX_TF32, false),
+ SUBARCH (amx_fp8, AMX_FP8, ANY_AMX_FP8, false),
SUBARCH (amx_tile, AMX_TILE, ANY_AMX_TILE, false),
SUBARCH (movdiri, MOVDIRI, MOVDIRI, false),
SUBARCH (movdir64b, MOVDIR64B, MOVDIR64B, false),
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index bfadb9317e3..bd2f585e1e3 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -231,6 +231,7 @@ accept various extension mnemonics. For example,
@code{amx_transpose},
@code{amx_avx512},
@code{amx_tf32},
+@code{amx_fp8}
@code{amx_tile},
@code{vmx},
@code{vmfunc},
@@ -1704,7 +1705,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
@item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk}
@item @samp{.amx_int8} @tab @samp{.amx_bf16} @tab @samp{.amx_fp16}
@item @samp{.amx_complex} @tab @samp{.amx_transpose} @tab @samp{.amx_avx512}
-@item @samp{.amx_tf32} @tab @samp{.amx_tile}
+@item @samp{.amx_tf32} @tab @samp {.amx_fp8} @tab @samp{.amx_tile}
@item @samp{.kl} @tab @samp{.widekl} @tab @samp{.uintr} @tab @samp{.hreset}
@item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
@item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme}
diff --git a/gas/testsuite/gas/i386/amx-fp8-inval.l b/gas/testsuite/gas/i386/amx-fp8-inval.l
new file mode 100644
index 00000000000..b74ff0c73e0
--- /dev/null
+++ b/gas/testsuite/gas/i386/amx-fp8-inval.l
@@ -0,0 +1,9 @@
+.* Assembler messages:
+.*:6: Error: `tdpbf8ps' is only supported in 64-bit mode
+.*:7: Error: `tdpbf8ps' is only supported in 64-bit mode
+.*:8: Error: `tdpbhf8ps' is only supported in 64-bit mode
+.*:9: Error: `tdpbhf8ps' is only supported in 64-bit mode
+.*:10: Error: `tdphbf8ps' is only supported in 64-bit mode
+.*:11: Error: `tdphbf8ps' is only supported in 64-bit mode
+.*:12: Error: `tdphf8ps' is only supported in 64-bit mode
+.*:13: Error: `tdphf8ps' is only supported in 64-bit mode
diff --git a/gas/testsuite/gas/i386/amx-fp8-inval.s b/gas/testsuite/gas/i386/amx-fp8-inval.s
new file mode 100644
index 00000000000..371c28db49d
--- /dev/null
+++ b/gas/testsuite/gas/i386/amx-fp8-inval.s
@@ -0,0 +1,13 @@
+# Check Illegal AMX-FP8 instructions
+
+ .allow_index_reg
+ .text
+_start:
+ tdpbf8ps %tmm4, %tmm5, %tmm6
+ tdpbf8ps %tmm1, %tmm2, %tmm3
+ tdpbhf8ps %tmm4, %tmm5, %tmm6
+ tdpbhf8ps %tmm1, %tmm2, %tmm3
+ tdphbf8ps %tmm4, %tmm5, %tmm6
+ tdphbf8ps %tmm1, %tmm2, %tmm3
+ tdphf8ps %tmm4, %tmm5, %tmm6
+ tdphf8ps %tmm1, %tmm2, %tmm3
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index 45e8adf7723..df0b7752ab6 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -549,6 +549,7 @@ if [gas_32_check] then {
run_list_test "amx-transpose-inval"
run_list_test "amx-avx512-inval"
run_list_test "amx-tf32-inval"
+ run_list_test "amx-fp8-inval"
run_list_test "sg"
run_dump_test "clzero"
run_dump_test "invlpgb"
diff --git a/gas/testsuite/gas/i386/x86-64-amx-fp8-intel.d b/gas/testsuite/gas/i386/x86-64-amx-fp8-intel.d
new file mode 100644
index 00000000000..8af297b1f92
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-amx-fp8-intel.d
@@ -0,0 +1,19 @@
+#objdump: -dw -Mintel
+#name: x86_64 AMX-FP8 insns (Intel disassembly)
+#source: x86-64-amx-fp8.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+#...
+[a-f0-9]+ <_intel>:
+\s*[a-f0-9]+:\s*c4 e5 58 fd f5\s+tdpbf8ps tmm6,tmm5,tmm4
+\s*[a-f0-9]+:\s*c4 e5 70 fd da\s+tdpbf8ps tmm3,tmm2,tmm1
+\s*[a-f0-9]+:\s*c4 e5 5b fd f5\s+tdpbhf8ps tmm6,tmm5,tmm4
+\s*[a-f0-9]+:\s*c4 e5 73 fd da\s+tdpbhf8ps tmm3,tmm2,tmm1
+\s*[a-f0-9]+:\s*c4 e5 5a fd f5\s+tdphbf8ps tmm6,tmm5,tmm4
+\s*[a-f0-9]+:\s*c4 e5 72 fd da\s+tdphbf8ps tmm3,tmm2,tmm1
+\s*[a-f0-9]+:\s*c4 e5 59 fd f5\s+tdphf8ps tmm6,tmm5,tmm4
+\s*[a-f0-9]+:\s*c4 e5 71 fd da\s+tdphf8ps tmm3,tmm2,tmm1
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-amx-fp8-inval.l b/gas/testsuite/gas/i386/x86-64-amx-fp8-inval.l
new file mode 100644
index 00000000000..726452418a0
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-amx-fp8-inval.l
@@ -0,0 +1,9 @@
+.* Assembler messages:
+.*:6: Error: all tmm registers must be distinct for `tdpbf8ps'
+.*:7: Error: all tmm registers must be distinct for `tdpbf8ps'
+.*:8: Error: all tmm registers must be distinct for `tdpbhf8ps'
+.*:9: Error: all tmm registers must be distinct for `tdpbhf8ps'
+.*:10: Error: all tmm registers must be distinct for `tdphbf8ps'
+.*:11: Error: all tmm registers must be distinct for `tdphbf8ps'
+.*:12: Error: all tmm registers must be distinct for `tdphf8ps'
+.*:13: Error: all tmm registers must be distinct for `tdphf8ps'
diff --git a/gas/testsuite/gas/i386/x86-64-amx-fp8-inval.s b/gas/testsuite/gas/i386/x86-64-amx-fp8-inval.s
new file mode 100644
index 00000000000..f3d7cafe73c
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-amx-fp8-inval.s
@@ -0,0 +1,13 @@
+# Check Illegal AMX-FP8 instructions
+
+ .allow_index_reg
+ .text
+_start:
+ tdpbf8ps %tmm1, %tmm1, %tmm2
+ tdpbf8ps %tmm1, %tmm2, %tmm2
+ tdpbhf8ps %tmm1, %tmm1, %tmm2
+ tdpbhf8ps %tmm1, %tmm2, %tmm2
+ tdphbf8ps %tmm1, %tmm1, %tmm2
+ tdphbf8ps %tmm1, %tmm2, %tmm2
+ tdphf8ps %tmm1, %tmm1, %tmm2
+ tdphf8ps %tmm1, %tmm2, %tmm2
diff --git a/gas/testsuite/gas/i386/x86-64-amx-fp8.d b/gas/testsuite/gas/i386/x86-64-amx-fp8.d
new file mode 100644
index 00000000000..fd81d0c52ff
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-amx-fp8.d
@@ -0,0 +1,17 @@
+#objdump: -dw
+#name: x86_64 AMX-FP8 insns
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*c4 e5 58 fd f5\s+tdpbf8ps %tmm4,%tmm5,%tmm6
+\s*[a-f0-9]+:\s*c4 e5 70 fd da\s+tdpbf8ps %tmm1,%tmm2,%tmm3
+\s*[a-f0-9]+:\s*c4 e5 5b fd f5\s+tdpbhf8ps %tmm4,%tmm5,%tmm6
+\s*[a-f0-9]+:\s*c4 e5 73 fd da\s+tdpbhf8ps %tmm1,%tmm2,%tmm3
+\s*[a-f0-9]+:\s*c4 e5 5a fd f5\s+tdphbf8ps %tmm4,%tmm5,%tmm6
+\s*[a-f0-9]+:\s*c4 e5 72 fd da\s+tdphbf8ps %tmm1,%tmm2,%tmm3
+\s*[a-f0-9]+:\s*c4 e5 59 fd f5\s+tdphf8ps %tmm4,%tmm5,%tmm6
+\s*[a-f0-9]+:\s*c4 e5 71 fd da\s+tdphf8ps %tmm1,%tmm2,%tmm3
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-amx-fp8.s b/gas/testsuite/gas/i386/x86-64-amx-fp8.s
new file mode 100644
index 00000000000..b8357b41ecb
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-amx-fp8.s
@@ -0,0 +1,23 @@
+# Check 64bit AMX-FP8 instructions
+
+ .text
+_start:
+ tdpbf8ps %tmm4, %tmm5, %tmm6
+ tdpbf8ps %tmm1, %tmm2, %tmm3
+ tdpbhf8ps %tmm4, %tmm5, %tmm6
+ tdpbhf8ps %tmm1, %tmm2, %tmm3
+ tdphbf8ps %tmm4, %tmm5, %tmm6
+ tdphbf8ps %tmm1, %tmm2, %tmm3
+ tdphf8ps %tmm4, %tmm5, %tmm6
+ tdphf8ps %tmm1, %tmm2, %tmm3
+
+_intel:
+ .intel_syntax noprefix
+ tdpbf8ps tmm6, tmm5, tmm4
+ tdpbf8ps tmm3, tmm2, tmm1
+ tdpbhf8ps tmm6, tmm5, tmm4
+ tdpbhf8ps tmm3, tmm2, tmm1
+ tdphbf8ps tmm6, tmm5, tmm4
+ tdphbf8ps tmm3, tmm2, tmm1
+ tdphf8ps tmm6, tmm5, tmm4
+ tdphf8ps tmm3, tmm2, tmm1
diff --git a/gas/testsuite/gas/i386/x86-64.exp b/gas/testsuite/gas/i386/x86-64.exp
index 9cb79eb0a4c..7d3f7ebe2b1 100644
--- a/gas/testsuite/gas/i386/x86-64.exp
+++ b/gas/testsuite/gas/i386/x86-64.exp
@@ -532,6 +532,9 @@ run_dump_test "x86-64-amx-avx512-intel"
run_dump_test "x86-64-amx-tf32"
run_dump_test "x86-64-amx-tf32-intel"
run_list_test "x86-64-amx-tf32-inval"
+run_dump_test "x86-64-amx-fp8"
+run_dump_test "x86-64-amx-fp8-intel"
+run_list_test "x86-64-amx-fp8-inval"
run_dump_test "x86-64-clzero"
run_dump_test "x86-64-mwaitx-bdver4"
run_list_test "x86-64-mwaitx-reg"
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 815e02a5d59..0fe2a5b48ec 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -1160,6 +1160,7 @@ enum
PREFIX_VEX_0F38F6_L_0,
PREFIX_VEX_0F38F7_L_0,
PREFIX_VEX_0F3AF0_L_0,
+ PREFIX_VEX_MAP5_FD_X86_64_L_0_W_0,
PREFIX_VEX_MAP7_F6_L_0_W_0_R_0_X86_64,
PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64,
@@ -1367,6 +1368,7 @@ enum
X86_64_VEX_0F386F,
X86_64_VEX_0F38Ex,
+ X86_64_VEX_MAP5_FD,
X86_64_VEX_MAP7_F6_L_0_W_0_R_0,
X86_64_VEX_MAP7_F8_L_0_W_0_R_0,
@@ -1498,6 +1500,7 @@ enum
VEX_LEN_0F3ADE_W_0,
VEX_LEN_0F3ADF,
VEX_LEN_0F3AF0,
+ VEX_LEN_MAP5_FD_X86_64,
VEX_LEN_MAP7_F6,
VEX_LEN_MAP7_F8,
VEX_LEN_XOP_08_85,
@@ -1674,6 +1677,7 @@ enum
VEX_W_0F3ACE,
VEX_W_0F3ACF,
VEX_W_0F3ADE,
+ VEX_W_MAP5_FD_X86_64_L_0,
VEX_W_MAP7_F6_L_0,
VEX_W_MAP7_F8_L_0,
@@ -4298,6 +4302,14 @@ static const struct dis386 prefix_table[][4] = {
{ "%XErorxS", { Gdq, Edq, Ib }, 0 },
},
+ /* PREFIX_VEX_MAP5_FD_X86_64_L_0_W_0 */
+ {
+ { "tdpbf8ps", { TMM, Rtmm, VexTmm }, 0 },
+ { "tdphbf8ps", { TMM, Rtmm, VexTmm }, 0 },
+ { "tdphf8ps", { TMM, Rtmm, VexTmm }, 0 },
+ { "tdpbhf8ps", { TMM, Rtmm, VexTmm }, 0 },
+ },
+
/* PREFIX_VEX_MAP7_F6_L_0_W_0_R_0_X86_64 */
{
{ Bad_Opcode },
@@ -4700,6 +4712,12 @@ static const struct dis386 x86_64_table[][2] = {
{ "%XEcmp%CCxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
},
+ /* X86_64_VEX_MAP5_FD */
+ {
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_MAP5_FD_X86_64) },
+ },
+
/* X86_64_VEX_MAP7_F6_L_0_W_0_R_0 */
{
{ Bad_Opcode },
@@ -7338,7 +7356,7 @@ static const struct dis386 vex_table[][256] = {
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { Bad_Opcode },
+ { X86_64_TABLE (X86_64_VEX_MAP5_FD) },
{ Bad_Opcode },
{ Bad_Opcode },
},
@@ -7781,6 +7799,11 @@ static const struct dis386 vex_len_table[][2] = {
{ PREFIX_TABLE (PREFIX_VEX_0F3AF0_L_0) },
},
+ /* VEX_LEN_MAP5_FD_X86_64 */
+ {
+ { VEX_W_TABLE (VEX_W_MAP5_FD_X86_64_L_0) },
+ },
+
/* VEX_LEN_MAP7_F6 */
{
{ VEX_W_TABLE (VEX_W_MAP7_F6_L_0) },
@@ -8417,6 +8440,10 @@ static const struct dis386 vex_w_table[][2] = {
/* VEX_W_0F3ADE */
{ VEX_LEN_TABLE (VEX_LEN_0F3ADE_W_0) },
},
+ {
+ /* VEX_W_MAP5_FD_X86_64 */
+ { PREFIX_TABLE (PREFIX_VEX_MAP5_FD_X86_64_L_0_W_0) },
+ },
{
/* VEX_W_MAP7_F6_L_0 */
{ REG_TABLE (REG_VEX_MAP7_F6_L_0_W_0) },
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index 6d2cdac6e4e..965eca2e640 100644
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -269,6 +269,8 @@ static const dependency isa_dependencies[] =
"AMX_TILE|AVX10_2" },
{ "AMX_TF32",
"AMX_TILE" },
+ { "AMX_FP8",
+ "AMX_TILE" },
{ "KL",
"SSE2" },
{ "WIDEKL",
@@ -438,6 +440,7 @@ static bitfield cpu_flags[] =
BITFIELD (AMX_TRANSPOSE),
BITFIELD (AMX_AVX512),
BITFIELD (AMX_TF32),
+ BITFIELD (AMX_FP8),
BITFIELD (AMX_TILE),
BITFIELD (MOVDIRI),
BITFIELD (MOVDIR64B),
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index 89a6396686a..a16ec56d355 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -256,6 +256,8 @@ enum i386_cpu
CpuAMX_AVX512,
/* Intel AMX-TF32 Instructions support required. */
CpuAMX_TF32,
+ /* AMX-FP8 instructions required */
+ CpuAMX_FP8,
/* AMX-TILE instructions required */
CpuAMX_TILE,
/* GFNI instructions required */
@@ -506,6 +508,7 @@ typedef union i386_cpu_flags
unsigned int cpuamx_complex:1;
unsigned int cpuamx_avx512:1;
unsigned int cpuamx_tf32:1;
+ unsigned int cpuamx_fp8:1;
unsigned int cpuamx_tile:1;
unsigned int cpugfni:1;
unsigned int cpuvaes:1;
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index b24f255307e..22c5653c313 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -3217,12 +3217,16 @@ tcvtrowps2phh, 0x07, AMX_AVX512, Modrm|EVex512|Space0F3A|VexW0|NoSuf, { Imm8, Re
tcvtrowps2phl, 0x666d, AMX_AVX512, Modrm|EVex512|Space0F38|Src2VVVV|VexW0|NoSuf, { Reg32, RegTMM, RegZMM }
tcvtrowps2phl, 0xf277, AMX_AVX512, Modrm|EVex512|Space0F3A|VexW0|NoSuf, { Imm8, RegTMM, RegZMM }
+tdpbf8ps, 0xfd, AMX_FP8, Modrm|Vex128|xVexMap5|Src2VVVV|VexW0|NoSuf, { RegTMM, RegTMM, RegTMM }
+tdpbhf8ps, 0xf2fd, AMX_FP8, Modrm|Vex128|xVexMap5|Src2VVVV|VexW0|NoSuf, { RegTMM, RegTMM, RegTMM }
tdpbf16ps, 0xf35c, AMX_BF16, Modrm|Vex128|Space0F38|Src2VVVV|VexW0|NoSuf, { RegTMM, RegTMM, RegTMM }
tdpfp16ps, 0xf25c, AMX_FP16, Modrm|Vex128|Space0F38|Src2VVVV|VexW0|NoSuf, { RegTMM, RegTMM, RegTMM }
tdpbssd, 0xf25e, AMX_INT8, Modrm|Vex128|Space0F38|Src2VVVV|VexW0|NoSuf, { RegTMM, RegTMM, RegTMM }
tdpbuud, 0x5e, AMX_INT8, Modrm|Vex128|Space0F38|Src2VVVV|VexW0|NoSuf, { RegTMM, RegTMM, RegTMM }
tdpbusd, 0x665e, AMX_INT8, Modrm|Vex128|Space0F38|Src2VVVV|VexW0|NoSuf, { RegTMM, RegTMM, RegTMM }
tdpbsud, 0xf35e, AMX_INT8, Modrm|Vex128|Space0F38|Src2VVVV|VexW0|NoSuf, { RegTMM, RegTMM, RegTMM }
+tdphbf8ps, 0xf3fd, AMX_FP8, Modrm|Vex128|xVexMap5|Src2VVVV|VexW0|NoSuf, { RegTMM, RegTMM, RegTMM }
+tdphf8ps, 0x66fd, AMX_FP8, Modrm|Vex128|xVexMap5|Src2VVVV|VexW0|NoSuf, { RegTMM, RegTMM, RegTMM }
tileloadd, 0xf24b, APX_F(AMX_TILE), Sibmem|Vex128|EVex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex, RegTMM }
tileloaddt1, 0x664b, APX_F(AMX_TILE), Sibmem|Vex128|EVex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex, RegTMM }
--
2.31.1
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