[PATCH 2/2] Support Intel MSR_IMM

[Hu, Lin1]

> -----Original Message-----
> From: Jan Beulich <jbeulich@suse.com>
> Sent: Friday, November 8, 2024 6:51 PM
> To: Hu, Lin1 <lin1.hu@intel.com>
> Cc: hongjiu.lu@intel.com; binutils@sourceware.org
> Subject: Re: [PATCH 2/2] Support Intel MSR_IMM
>
>
> On 06.11.2024 10:09, Hu, Lin1 wrote:
> > --- a/opcodes/i386-opc.tbl
> > +++ b/opcodes/i386-opc.tbl
> > @@ -964,6 +964,7 @@ cpuid, 0xfa2, i486, NoSuf, {}  // Pentium
> > extensions.
> >  wrmsr, 0xf30, i586, NoSuf, {}
> >  rdtsc, 0xf31, i586, NoSuf, {}
> > +rdmsr, 0xf2f6/0, APX_F(MSR_IMM),
> > +Modrm|Vex128|SpaceMap7|EVex128|VexW0|NoSuf, { Imm32, Reg64 }
> >  rdmsr, 0xf32, i586, NoSuf, {}
> >  cmpxchg8b, 0xfc7/1, i586,
> > Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64|HLEPrefixLock, {
> > Qword|Unspecified|BaseIndex }
> >
> > @@ -3373,6 +3374,9 @@ cmp<cc>xadd, 0x66e<cc:opc>,
> APX_F(CMPCCXADD),
> > Modrm|Vex|EVex128|Space0F38|Src2VV
> >
> >  // WRMSRNS instruction.
> >
> > +// Immediates want to be first; md_assemble() takes care of swapping
> > +operands // accordingly.
> > +wrmsrns, 0xf3f6/0, APX_F(MSR_IMM),
> > +Modrm|Vex128|SpaceMap7|EVex128|VexW0|NoSuf, { Imm32, Reg64 }
> >  wrmsrns, 0x0f01c6, WRMSRNS, NoSuf, {}
> >
> >  // WRMSRNS instruction end.
> 
> Unless there are specific reasons (which you then would want to state in the
> description), please add new forms _after_ pre-existing ones.
> 

Due to we add a handler for MSR's imm32

7000   if (i.imm_operands)
 7001     {
 7002       /* For USER_MSR and MSR_IMM instructions, imm32 stands for the name of an
 7003          model specific register (MSR). That's an unsigned quantity, whereas all
 7004          other insns with 32-bit immediate and 64-bit operand size use
 7005          sign-extended immediates (imm32s). Therefore these insns are
 7006          special-cased, bypassing the normal handling of immediates here.  */
 7007       if (is_cpu(current_templates.start, CpuUSER_MSR)
 7008           || is_cpu(current_templates.start, CpuMSR_IMM))
 7009         {
 7010           for (j = 0; j < i.operands; j++)
 7011             {
 7012               if (operand_type_check(i.types[j], imm))
 7013                 i.types[j] = smallest_imm_type (i.op[j].imms->X_add_number);
 7014             }
 7015         }
 7016       else
 7017         optimize_imm ();
 7018     }

So I need to put MSR_IMM before existing ones. I add two comments in i386-opc.tbl
Like this

3381 // MSR_IMM instructions' imm32 stands for the name of an model specific
3382 // register (MSR). The imm32 needs a special handler in tc-i386.c, hence put
3383 // wrmsrns of MSR_IMM firsty, since the logic is determined by is_cpu (...).


Thanks for you suggestions, the problem you mentioned has been modified,
please refer to the second version.

BRs,
Lin